JP2844058B2 - 半導体パッケージ - Google Patents
半導体パッケージInfo
- Publication number
- JP2844058B2 JP2844058B2 JP25296A JP25296A JP2844058B2 JP 2844058 B2 JP2844058 B2 JP 2844058B2 JP 25296 A JP25296 A JP 25296A JP 25296 A JP25296 A JP 25296A JP 2844058 B2 JP2844058 B2 JP 2844058B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- semiconductor
- semiconductor substrate
- fine electrodes
- fine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 55
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 8
- 239000002313 adhesive film Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10719—Land grid array [LGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
る半導体パッケージに係るもので、詳しくは、従来BG
A(Ball Grid Array )半導体パッケージの電導性ボー
ルの代わりに、微細な電極及びインタフェース伝導体を
用い、生産性を向上させた微細電導極を有する半導体パ
ッケージに関するものである。
は、文献(1994年5月号、NEKKEI ELECTRONICS誌、
P42−45)に記載され、図4に示したように、半導
体基板1上に半導体チップ3を接着剤2により接着し、
該半導体チップ3上両側部位と前記半導体基板1上の導
電部位(図示されず)とを金属ワイヤー4によりボンデ
ィングし、それら半導体基板1、半導体チップ3及び金
属ワイヤー4をエポキシ樹脂によりモールディングした
後、該エポキシ成形体7の半導体基板1下面に電極端子
5を夫々露出させる。次いで、それら電極端子5にソル
ダーボール6を夫々掛合し、リフロー(reflow)接合を
施してそれらソルダーボール6を半導体基板1下面の電
極端子5に夫々接着させていた。
来BGA半導体パッケージにおいては、半導体パッケー
ジの製造後に電気的検査を施し、電気的連結の不良状態
が発生した場合は、半導体パッケージ下面の各ソルダー
ボール6を全て除去し、クリーニングを施した後、それ
らソルダーボール6の付着工程を再施行するようになる
ため、極めて煩雑になり、生産性が低下するという不都
合な点があった。
位5に各ソルダーボール6を一々付着するようになって
いるため、それらソルダーボール6の付着ピッチ間隔が
1.0〜1.5mmに制限され、それら付着動作が極め
て煩雑であるという不都合な点があった。
ソルダーボールを使用せず、微細電極及びインタフェー
ス伝導体を用いて生産性を向上し得る微細電導極を有し
た半導体パッケージを提供しようとするものである。
ージの製造工程を簡単化し、原価を減少し得る微細電導
極を有した半導体パッケージを提供しようとするもので
ある。
体パッケージのエポキシ成形体基板下面露出部位に1.
0mm以下のピッチ間隔を有する複数の微細電極を形成
し、それら微細電極に対応して印刷回路基板上にも同様
な1.0mm以下のピッチ間隔を有する複数の微細電極
を形成し、エポキシ成形体基板の微細電極に接する厚さ
5〜200μm以下の異方性電導フィルムとその表面を
覆う厚さ200μm以下の光分解性接着フィルムとでな
るインタフェース伝導体を熱圧着させて微細電極を有す
る半導体パッケージを構成することにより達成される。
図面を用いて説明する。本発明に係る微細電導極を有す
る半導体パッケージにおいては、図1から図3に示した
ように、先ず、半導体基板11***部位に接着剤2に
より半導体チップ3が接着され、それら半導体チップ3
の両側辺部位と半導体基板11上の所定部位とが金属ワ
イヤー4によりボンディングされ、エポキシモールディ
ングされた後該エポキシ成形体7の基板11の下面露出
部位に複数の微細電極12が1mm以下のピッチ間隔を
有しかつ0.01cm2 程度の面積を有して形成され
る。このとき、それら微細電極12には金(Au)また
は銀(Ag)の鍍金が施される。
細電極12の形成された領域または半導体基板11の下
面全ての領域に5〜200μmの厚さを有しかつ微細な
可溶性電導ボール(図3参照)を含む異方性電導フィル
ム13を熱圧着し、さらにノボラックポリエステル系の
光分解性接着フィルム14をコーティングして該異方性
電導フィルム13の変質が防止され得るインタフェース
伝導体15が形成される。次いで、印刷回路基板20上
に前記各微細電極12に対応する複数の微細電極12a
が夫々所定ピッチ間隔を有して形成され、半導体パッケ
ージ基板11下面の各微細電極12を異方性電導フィル
ム13を介して印刷回路基板20上の各微細電極12a
に連結するとき、前記光分解性接着フィルム14が露光
に露出されかつ例えばドライエッチングが施行されて除
去された後に連結される。
電導極を有する半導体パッケージにおいては、従来のソ
ルダーボールを使用せず、微細電極とインターフェース
伝導体とを用いて半導体パッケージを構成し、印刷回路
基板上に電気的連結し得るようになっているため、従来
半導体基板下面に一々ソルダーボールを付着した後、電
気的検査を施してソルダーボールの付着不良が発生した
時、全てのソルダーボールを除去して再施行していた煩
雑な工程が省かれ、半導体パッケージの製造工程が簡単
化されて生産性が向上し、原価が低廉になるという効果
がある。
ージの構造を示した概略縦断面図である。
ージを印刷回路基板に接合した状態を示した概略縦断面
図である。
図1中のA部の拡大縦断面図である。
略縦断面図である。
Claims (5)
- 【請求項1】 半導体基板上に接着された半導体チップ
と、該半導体チップと前記半導体基板上の導電部位とに
ボンディングされた金属ワイヤーと、それら半導体チッ
プ、金属ワイヤー及び半導体基板上部がエポキシモール
ディングされて成形されたエポキシ成形体の半導体基板
露出部位に夫々形成された複数の微細電極と、それら微
細電極下面に形成されていてかつ印刷回路基板上の微細
電極に電気的に連結されるべきインタフェース伝導体と
を備えた半導体パッケージにおいて、 前記インタフェース伝導体は、前記半導体基板の各微細
電極下面に熱圧着された異方性電導フィルムとその表面
を覆う光分解性接着フィルムとを含み、前記光分解性接
着フィルムは前記異方性電導フィルムが前記印刷回路基
板上の微細電極に電気的に連結されるときには光照射と
エッチングによって分解除去されるものであることを特
徴とする半導体パッケージ。 - 【請求項2】 前記各微細電極は、前記半導体基板下面
に1mm以下のピッチ間隔を有して形成されている請求
項1に記載の半導体パッケージ。 - 【請求項3】 前記各微細電極は、金または銀にて鍍金
されている請求項1または2に記載の半導体パッケー
ジ。 - 【請求項4】 前記異方性電導フィルムは、5〜200
μmの厚さに形成されている請求項1から3のいずれか
の項に記載の半導体パッケージ。 - 【請求項5】 前記光分解性接着フィルムは、200μ
m以下の厚さに形成されている請求項1から4のいずれ
かの項に記載の半導体パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR95P36163 | 1995-10-19 | ||
KR1019950036163A KR100201383B1 (ko) | 1995-10-19 | 1995-10-19 | 인터페이스 조립체를 구비한 유에프비지에이 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09129779A JPH09129779A (ja) | 1997-05-16 |
JP2844058B2 true JP2844058B2 (ja) | 1999-01-06 |
Family
ID=19430674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25296A Expired - Fee Related JP2844058B2 (ja) | 1995-10-19 | 1996-01-05 | 半導体パッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US5877549A (ja) |
JP (1) | JP2844058B2 (ja) |
KR (1) | KR100201383B1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103901236A (zh) * | 2014-03-06 | 2014-07-02 | 广东工业大学 | 一种超精细无极金属丝栅网封装环 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6001672A (en) * | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
US7220615B2 (en) * | 2001-06-11 | 2007-05-22 | Micron Technology, Inc. | Alternative method used to package multimedia card by transfer molding |
KR100429856B1 (ko) * | 2001-11-15 | 2004-05-03 | 페어차일드코리아반도체 주식회사 | 스터드 범프가 있는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법 |
US20050176233A1 (en) * | 2002-11-15 | 2005-08-11 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
US20050012225A1 (en) * | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
US20040191955A1 (en) * | 2002-11-15 | 2004-09-30 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
US7728437B2 (en) * | 2005-11-23 | 2010-06-01 | Fairchild Korea Semiconductor, Ltd. | Semiconductor package form within an encapsulation |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4731282A (en) * | 1983-10-14 | 1988-03-15 | Hitachi Chemical Co., Ltd. | Anisotropic-electroconductive adhesive film |
DE3852563T2 (de) * | 1987-05-01 | 1995-05-11 | Canon Kk | Verfahren zum Anschliessen eines externen Schaltkreises und Verpackungsstruktur. |
US5283468A (en) * | 1988-05-30 | 1994-02-01 | Canon Kabushiki Kaisha | Electric circuit apparatus |
SG49842A1 (en) * | 1988-11-09 | 1998-06-15 | Nitto Denko Corp | Wiring substrate film carrier semiconductor device made by using the film carrier and mounting structure comprising the semiconductor |
US5001542A (en) * | 1988-12-05 | 1991-03-19 | Hitachi Chemical Company | Composition for circuit connection, method for connection using the same, and connected structure of semiconductor chips |
CA2034702A1 (en) * | 1990-01-23 | 1991-07-24 | Masanori Nishiguchi | Method for packaging semiconductor device |
US5304460A (en) * | 1992-09-30 | 1994-04-19 | At&T Bell Laboratories | Anisotropic conductor techniques |
US5291062A (en) * | 1993-03-01 | 1994-03-01 | Motorola, Inc. | Area array semiconductor device having a lid with functional contacts |
JPH0714966A (ja) * | 1993-06-17 | 1995-01-17 | Ibiden Co Ltd | 多端子複合リードフレームとその製造方法 |
US5434452A (en) * | 1993-11-01 | 1995-07-18 | Motorola, Inc. | Z-axis compliant mechanical IC wiring substrate and method for making the same |
-
1995
- 1995-10-19 KR KR1019950036163A patent/KR100201383B1/ko not_active IP Right Cessation
-
1996
- 1996-01-02 US US08/581,956 patent/US5877549A/en not_active Expired - Lifetime
- 1996-01-05 JP JP25296A patent/JP2844058B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103901236A (zh) * | 2014-03-06 | 2014-07-02 | 广东工业大学 | 一种超精细无极金属丝栅网封装环 |
CN103901236B (zh) * | 2014-03-06 | 2016-04-20 | 广东工业大学 | 一种超精细无极金属丝栅网封装环 |
Also Published As
Publication number | Publication date |
---|---|
JPH09129779A (ja) | 1997-05-16 |
KR100201383B1 (ko) | 1999-06-15 |
KR970024032A (ko) | 1997-05-30 |
US5877549A (en) | 1999-03-02 |
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