JP2830351B2 - Semiconductor device connection method - Google Patents
Semiconductor device connection methodInfo
- Publication number
- JP2830351B2 JP2830351B2 JP2095056A JP9505690A JP2830351B2 JP 2830351 B2 JP2830351 B2 JP 2830351B2 JP 2095056 A JP2095056 A JP 2095056A JP 9505690 A JP9505690 A JP 9505690A JP 2830351 B2 JP2830351 B2 JP 2830351B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- bump electrode
- semiconductor
- substrate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体チップ等の半導体装置の接続方法に
関する。The present invention relates to a method for connecting a semiconductor device such as a semiconductor chip.
［従来の技術］ 従来、ICチップ等の半導体チップは、半導体ウエハの
パッド電極上にバンプ電極を形成した上、半導体ウエハ
をダイシングすることにより、個々のチップ部品として
分割形成されている。2. Description of the Related Art Conventionally, a semiconductor chip such as an IC chip is divided into individual chip components by forming bump electrodes on pad electrodes of a semiconductor wafer and then dicing the semiconductor wafer.
この半導体チップを基板に搭載する方法として、TAB
（Tape Automated Bonding）方式が知られている。この
TAB方式では、フィルム基板にデバイスホールを形成し
た上、フィルム基板の表面に銅等の金属箔をラミネート
し、この金属箔をエッチングしてデバイスホールの縁か
ら内側へ突出するフィンガリードを形成し、このフィン
ガリードに半導体チップのバンプ電極をボンディングす
ることにより、半導体チップをフィルム基板に搭載して
いる。As a method of mounting this semiconductor chip on a substrate, TAB
(Tape Automated Bonding) method is known. this
In the TAB method, after forming a device hole in the film substrate, a metal foil such as copper is laminated on the surface of the film substrate, and this metal foil is etched to form finger leads projecting inward from the edge of the device hole, The semiconductor chip is mounted on a film substrate by bonding the bump electrodes of the semiconductor chip to the finger leads.
［発明が解決しようとする課題］ しかし、上述した半導体チップの接続方法では、フィ
ルム基板のフィンガリードに半導体チップのバンプ電極
をボンディングする際、フィンガリードが半導体チップ
の外端部に接触して短絡するという所謂エッジショート
を起し易い。そのため、ボンディング後にフィンガリー
ドが半導体チップの外端部に接触しないように、各半導
体チップ毎に、フィンガリードをフォーミング加工によ
り屈曲させたり、あるいは半導体チップの外端部に絶縁
シートを配置したりしなければならず、接続作業が煩雑
で、作業性が極めて悪いという問題がある。[Problems to be Solved by the Invention] However, in the above-described method for connecting a semiconductor chip, when bonding the bump electrode of the semiconductor chip to the finger lead of the film substrate, the finger lead contacts the outer end of the semiconductor chip and is short-circuited. That is, it is easy to cause a so-called edge short. Therefore, for each semiconductor chip, the finger lead is bent by forming processing or an insulating sheet is arranged at the outer end of the semiconductor chip so that the finger lead does not contact the outer end of the semiconductor chip after bonding. However, there is a problem that connection work is complicated and workability is extremely poor.
この発明の目的は、エッジショートを起さず、能率的
に半導体装置を接続することのできる半導体装置の接続
方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device connection method which can efficiently connect a semiconductor device without causing an edge short.
［課題を解決するための手段］ この発明は上述した目的を達成するために、半導体ウ
エハにバンプ電極を形成した上、前記半導体ウエハのバ
ンプ電極側の表面にスピンコーティングにより少なくと
も前記バンプ電極の高さとほぼ同じ膜厚で、絶縁膜の上
面が前記半導体ウエハの前記表面と平行になるように樹
脂を塗布し、その後硬化することにより該絶縁膜を形成
し、この絶縁膜をその膜厚の中間までエッチングして前
記バンプ電極の先端部分を絶縁膜の上方に突出させた
後、前記半導体ウエハをダイシングして個々の半導体装
置に分割し、この分割された半導体装置の絶縁膜から突
出した前記バンプ電極の先端部分を基板の接続端子にボ
ンディングすることである。Means for Solving the Problems In order to achieve the above-described object, the present invention forms bump electrodes on a semiconductor wafer and spin coats at least the bump electrodes on the surface of the semiconductor wafer on the bump electrode side. A resin is applied so that the upper surface of the insulating film is substantially the same as that of the semiconductor wafer, and then the resin is cured so that the insulating film is formed. After the tip portion of the bump electrode is protruded above the insulating film by etching until the semiconductor wafer is diced and divided into individual semiconductor devices, the bumps protruding from the insulating film of the divided semiconductor device. Bonding the tip of the electrode to the connection terminal of the substrate.
［作用］ この発明によれば、半導体ウエハの状態で、半導体ウ
エハのバンプ電極側の表面に絶縁膜を形成し、この絶縁
膜を膜厚の中間までエッチングすることにより前記バン
プ電極の先端部分を絶縁膜の上方に突出させたので、こ
の後、半導体ウエハをダイシングして個々の半導体装置
に分割しても、分割された個々の半導体装置の外端部に
は絶縁膜が形成されることとなる。そのため、個々の半
導体装置を基板の接続端子にボンディングする際、従来
のように各半導体装置毎に、基板の接続端子をフォーミ
ング加工により屈曲させたり、あるいは半導体装置の外
端部に絶縁シートを設けたりしなくても、エッジショー
トを起さず、半導体装置を基板の接続端子に簡単かつ容
易にボンディングでき、極めて能率的に接続することが
できる。According to the present invention, in the state of the semiconductor wafer, an insulating film is formed on the surface of the semiconductor wafer on the side of the bump electrode, and the insulating film is etched to an intermediate thickness to form a tip portion of the bump electrode. Since the semiconductor wafer is projected above the insulating film, even if the semiconductor wafer is subsequently diced and divided into individual semiconductor devices, the insulating film is formed at the outer ends of the divided individual semiconductor devices. Become. Therefore, when bonding an individual semiconductor device to a connection terminal of a substrate, the connection terminal of the substrate is bent by forming processing, or an insulating sheet is provided at the outer end of the semiconductor device for each semiconductor device as in the related art. Even if it does not occur, the semiconductor device can be easily and easily bonded to the connection terminal of the substrate without causing an edge short, and the connection can be made extremely efficiently.
［実施例］ 以下、第１図〜第３図を参照して、この発明の一実施
例を説明する。[Embodiment] One embodiment of the present invention will be described below with reference to FIGS.
まず、第２図に示すように、シリコン基板（半導体ウ
エハ）１のパッド電極２上にバンプ電極３を形成する。
この場合、シリコン基板１にはチップ形成領域が多数区
画されており、各チップ形成領域にはそれぞれ所定の集
積回路が形成されているとともにパッド電極２が形成さ
れている。First, as shown in FIG. 2, a bump electrode 3 is formed on a pad electrode 2 of a silicon substrate (semiconductor wafer) 1.
In this case, a large number of chip forming regions are defined on the silicon substrate 1, and a predetermined integrated circuit is formed in each chip forming region and a pad electrode 2 is formed.
そして、パッド電極２上にバンプ電極３を形成する場
合には、シリコン基板１の上面（パッド電極２側の面）
にフォトレジストを塗布し、このフォトレジストをフォ
トリソグラフィ法により露光し現像することにより、パ
ッド電極２と対応する箇所に開口を形成し、この状態で
メッキを施すと、開口を通してパッド電極２上にバンプ
電極３が形成される。このバンプ電極３は金や半田等の
金属よりなり、その高さは30μｍ程度に形成されてい
る。When the bump electrode 3 is formed on the pad electrode 2, the upper surface of the silicon substrate 1 (the surface on the side of the pad electrode 2)
An opening is formed at a location corresponding to the pad electrode 2 by exposing and developing the photoresist by a photolithography method, and plating is performed in this state. The bump electrode 3 is formed. The bump electrode 3 is made of a metal such as gold or solder, and has a height of about 30 μm.
この後、同図に示すように、バンプ電極３が形成され
たシリコン基板１の上面に絶縁膜４を設ける。この絶縁
膜４は絶縁性を有する液状のポリイミド樹脂等よりな
り、この樹脂をスピンコーディングにより塗布した上、
乾燥硬化することにより形成される。この場合、絶縁膜
４の膜厚は図ではバンプ電極３の高さよりも厚く形成さ
れているが、バンプ電極３の高さとほぼ同じ膜厚に形成
してもよい。しかし、いずれの場合においても、絶縁膜
４の上面はシリコン基板１の上面と平行に形成すること
が望ましい。Thereafter, as shown in FIG. 3, an insulating film 4 is provided on the upper surface of the silicon substrate 1 on which the bump electrodes 3 are formed. The insulating film 4 is made of an insulating liquid polyimide resin or the like, and the resin is applied by spin coding.
It is formed by drying and curing. In this case, the thickness of the insulating film 4 is formed to be larger than the height of the bump electrode 3 in the drawing, but may be formed to be substantially the same as the height of the bump electrode 3. However, in any case, it is desirable that the upper surface of the insulating film 4 be formed parallel to the upper surface of the silicon substrate 1.
次に、第３図に示すように、絶縁膜４の全表面をハー
フエッチングによりその上面から膜厚の中間まで除去し
てバンプ電極３の上端部分５を絶縁膜４の上方に突出さ
せる。この場合、ハーフエッチングはエッチング時間等
のエッチング条件を適宜設定することによりエッチング
量を調整することができる。また、エッチング後の絶縁
膜４の膜厚は、バンプ電極３の高さの80〜90％の厚さが
望ましい。例えば、バンプ電極３の高さが30μｍ程度あ
れば、絶縁膜４の厚さを25μｍ程度に形成する。Next, as shown in FIG. 3, the entire surface of the insulating film 4 is removed from the upper surface to the middle of the film thickness by half etching, and the upper end portion 5 of the bump electrode 3 is projected above the insulating film 4. In this case, the amount of half etching can be adjusted by appropriately setting etching conditions such as an etching time. The thickness of the insulating film 4 after the etching is desirably 80 to 90% of the height of the bump electrode 3. For example, if the height of the bump electrode 3 is about 30 μm, the thickness of the insulating film 4 is formed to be about 25 μm.
この後、同図に示すように、シリコン基板１のチップ
形成領域の境界に位置する箇所（２点鎖線で示す箇所）
の絶縁膜４にダイシング用の溝６を形成する。この場合
には、絶縁膜４の表面にフォトレジストを塗布して露光
し現像することにより、チップ形成領域の境界と対応す
る箇所のフォトレジストに開口を形成し、この開口を通
して絶縁膜４をエッチングすることにより、ダイシング
用の溝６が形成される。なお、この溝は断面形状が
「Ｖ」字状に形成されたものが望ましいが、これに限ら
れない。そして、ダイシング用の溝６に沿ってシリコン
基板１をダイヤモンドブレード等によりダイシングし
て、個々の半導体チップ７に分割する。Thereafter, as shown in the figure, a portion located at the boundary of the chip formation region of the silicon substrate 1 (a portion indicated by a two-dot chain line)
A dicing groove 6 is formed in the insulating film 4 of FIG. In this case, an opening is formed in a portion of the photoresist corresponding to the boundary of the chip formation region by applying a photoresist on the surface of the insulating film 4, exposing and developing, and etching the insulating film 4 through the opening. As a result, a dicing groove 6 is formed. The groove is desirably formed in a V-shaped cross section, but is not limited to this. Then, the silicon substrate 1 is diced along a dicing groove 6 with a diamond blade or the like, and divided into individual semiconductor chips 7.
次に、第１図に示すように、分割された半導体チップ
７をTAB方式によりフィルム基板８に搭載する。この場
合には、予めフィルム基板８にフィンガリード９を形成
する。すなわち、フィルム基板８の所定箇所にデバイス
ホール10を形成した上、フィルム基板８の表面に銅等の
金属箔をラミネートし、この金属箔をフォトリゾグラフ
ィ法を用いてエッチングし、金属箔の不要な部分を除去
することにより、デバイスホール10内に突出した所定形
状のフィンガリード９を形成する。なお、フィンガリー
ド９の全表面にはスズ、半田合金等のメッキを施す。す
なわち、バンプ電極３が金の場合にはスズメッキを施
し、バンプ電極３が半田の場合には半田合金のメッキを
施す。Next, as shown in FIG. 1, the divided semiconductor chips 7 are mounted on a film substrate 8 by a TAB method. In this case, the finger leads 9 are formed on the film substrate 8 in advance. That is, a device hole 10 is formed in a predetermined portion of the film substrate 8, and a metal foil such as copper is laminated on the surface of the film substrate 8, and the metal foil is etched by using a photolithography method. By removing unnecessary portions, finger leads 9 having a predetermined shape protruding into device holes 10 are formed. The entire surface of the finger lead 9 is plated with tin, a solder alloy, or the like. That is, when the bump electrode 3 is gold, tin plating is applied, and when the bump electrode 3 is solder, solder alloy plating is applied.
そして、半導体チップ７をフィルム基板８に搭載する
場合には、フィルム基板８のデバイスホール10内に半導
体チップ７を配置し、半導体チップ７のバンプ電極３を
フィンガリード９に対向させ、この状態でバンプ電極３
とフィンガリード９とを熱圧着によりボンディングす
る。このとき、半導体チップ７の上面、特に外端部11上
には絶縁膜４が形成されているので、バンプ電極３にフ
ィンガリード９をボンディングする際、従来のように各
半導体チップ７毎に、フィンガリード９をフォーミング
により屈曲させたり、あるいは半導体チップ７の外端部
11に絶縁シートを配置したりしなくても、フィンガリー
ド９が半導体チップ７の外端部11に接触して短絡するこ
とはない。この場合、半導体チップ７のレイアウト等、
半導体チップ７の外端部11との短絡を防ぐ以外にフィン
ガリード９をフォーミング加工により屈曲させることは
差し支えない。この後、バンプ電極３とフィンガリード
９の接合部分を樹脂12で封止して保護すればよいので、
半導体チップ７をフィルム基板８に簡単にかつ容易に接
続することができ、能率的に接続作業を行なうことがで
きる。When the semiconductor chip 7 is mounted on the film substrate 8, the semiconductor chip 7 is arranged in the device hole 10 of the film substrate 8, and the bump electrodes 3 of the semiconductor chip 7 are opposed to the finger leads 9. Bump electrode 3
And the finger leads 9 are bonded by thermocompression bonding. At this time, since the insulating film 4 is formed on the upper surface of the semiconductor chip 7, particularly on the outer end portion 11, when bonding the finger lead 9 to the bump electrode 3, The finger leads 9 are bent by forming, or the outer end of the semiconductor chip 7
Even if an insulating sheet is not provided on the semiconductor chip 7, the finger lead 9 does not contact the outer end 11 of the semiconductor chip 7 to cause a short circuit. In this case, the layout of the semiconductor chip 7, etc.
The finger lead 9 may be bent by forming in addition to preventing a short circuit with the outer end portion 11 of the semiconductor chip 7. Thereafter, the joint between the bump electrode 3 and the finger lead 9 may be sealed and protected with the resin 12.
The semiconductor chip 7 can be easily and easily connected to the film substrate 8, and the connection operation can be performed efficiently.
なお、この発明は上述した実施例に限定されるもので
はない。例えば、半導体チップ７が接続される基板は、
フィルム基板８である必要はなく、硬質の配線基板であ
ってもよい。また、半導体チップ７のバンプ電極３がボ
ンディングされる接続端子は、必ずしもフィンガリード
である必要はなく、基板上に設けられたパッド電極であ
ってもよい。さらに、半導体チップ７はTAB方式により
ボンディングする必要はなく、フリップチップ方式、あ
るいはフェイスダウン方式によりボンディングするよう
にしてもよい。The present invention is not limited to the embodiment described above. For example, the substrate to which the semiconductor chip 7 is connected is
It is not necessary to be the film substrate 8, and a hard wiring substrate may be used. The connection terminal to which the bump electrode 3 of the semiconductor chip 7 is bonded does not necessarily need to be a finger lead, and may be a pad electrode provided on a substrate. Further, the semiconductor chip 7 need not be bonded by the TAB method, but may be bonded by the flip chip method or the face-down method.
［発明の効果］ 以上詳細に説明したように、この発明によれば、半導
体ウエハの状態で、半導体ウエハのバンプ電極側の表面
に絶縁膜を形成した上、その膜厚の中間までエッチング
することにより前記バンプ電極の先端部分を絶縁膜の上
方に突出させたので、半導体ウエハをダイシングして個
々に分割された半導体チップを基板の接続端子にボンデ
ィングする際に、従来のように各半導体チップ毎に、基
板の接続端子を屈曲したり、あるいは半導体チップの外
端部に絶縁シートを設けたりしなくても、エッジショー
トを防ぐことができ、半導体チップを基板の接続端子に
簡単かつ容易に接続することができ、極めて能率的に接
続することができる。[Effects of the Invention] As described above in detail, according to the present invention, in a state of a semiconductor wafer, an insulating film is formed on a surface of a semiconductor wafer on a bump electrode side, and then etched to an intermediate thickness. As a result, the tip portion of the bump electrode protrudes above the insulating film. Therefore, when dicing the semiconductor wafer and bonding the individually divided semiconductor chips to the connection terminals of the substrate, each semiconductor chip has a In addition, the edge short-circuit can be prevented without bending the connection terminals of the substrate or providing an insulating sheet at the outer end of the semiconductor chip, and the semiconductor chip can be easily and easily connected to the connection terminals of the substrate. And can be connected very efficiently.
第１図はこの発明の接続方法によって半導体チップをフ
ィルム基板に接続した状態の断面図、第２図は半導体ウ
エハにバンプ電極を形成した上、絶縁膜を設けた状態の
要部断面図、第３図は第２図の絶縁膜をハーフエッチン
グしてバンプ電極の上端部分を突出させた状態の要部断
面図である。 １……シリコン基板（半導体ウエハ）、３……バンプ電
極、４……絶縁膜、５……上端部分（先端部分）、７…
…半導体チップ、８……フィルム基板、９……フィンガ
リード（接続端子）。FIG. 1 is a cross-sectional view showing a state in which a semiconductor chip is connected to a film substrate by the connection method of the present invention. FIG. 2 is a cross-sectional view showing a main part in a state in which a bump electrode is formed on a semiconductor wafer and an insulating film is provided. FIG. 3 is a sectional view of a main part in a state where the upper end portion of the bump electrode is projected by half-etching the insulating film of FIG. 1 ... Silicon substrate (semiconductor wafer), 3 ... Bump electrode, 4 ... Insulating film, 5 ... Top part (tip part), 7 ...
... Semiconductor chip, 8 ... Film substrate, 9 ... Finger lead (connection terminal).
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311Continuation of front page (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60 311
Claims (1)
と、前記半導体ウエハの前記バンプ電極側の表面にスピ
ンコーティングにより少なくとも前記バンプ電極の高さ
とほぼ同じ膜厚で、絶縁膜の上面が前記半導体ウエハの
前記表面と平行になるように樹脂を塗布し、その後硬化
することにより該絶縁膜を形成する工程と、前記絶縁膜
を該絶縁膜の全表面ハーフエッチングによりその膜厚の
中間までエッチングして前記バンプ電極の先端部分を前
記絶縁膜の上方に突出させる工程と、前記半導体ウエハ
をダイシングして個々の半導体装置に分割する工程と、
前記半導体装置の絶縁膜から突出した前記バンプ電極の
先端部分を基板の接続端子にボンディングする工程と、
からなる半導体装置の接続方法。A step of forming a bump electrode on a semiconductor wafer; and a step of spin-coating a surface of the semiconductor wafer on the bump electrode side to a thickness at least substantially equal to the height of the bump electrode, and forming an upper surface of the semiconductor film on the semiconductor film. Applying a resin so as to be parallel to the surface of the wafer, and then curing the resin to form the insulating film; and etching the insulating film to an intermediate thickness by half-etching the entire surface of the insulating film. Projecting the tip portion of the bump electrode above the insulating film, and dicing the semiconductor wafer into individual semiconductor devices,
Bonding a tip portion of the bump electrode protruding from the insulating film of the semiconductor device to a connection terminal of a substrate;
A method for connecting a semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2095056A JP2830351B2 (en) | 1990-04-12 | 1990-04-12 | Semiconductor device connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2095056A JP2830351B2 (en) | 1990-04-12 | 1990-04-12 | Semiconductor device connection method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10164470A Division JP3019065B2 (en) | 1998-05-29 | 1998-05-29 | Semiconductor device connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03293740A JPH03293740A (en) | 1991-12-25 |
| JP2830351B2 true JP2830351B2 (en) | 1998-12-02 |
Family
ID=14127392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2095056A Expired - Fee Related JP2830351B2 (en) | 1990-04-12 | 1990-04-12 | Semiconductor device connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2830351B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159837A (en) * | 1998-07-16 | 2000-12-12 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
| CN100435297C (en) * | 2003-09-30 | 2008-11-19 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0622845A3 (en) * | 1993-04-30 | 1995-03-29 | Hewlett Packard Co | Apparatus and method for tape automated bonding beam lead insulation. |
| JP3258764B2 (en) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same |
| CN1420538A (en) * | 1996-07-12 | 2003-05-28 | 富士通株式会社 | Method for mfg. semiconductor device, semiconductor device and assembling method trereof |
| US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
| JP3346320B2 (en) | 1999-02-03 | 2002-11-18 | カシオ計算機株式会社 | Semiconductor device and manufacturing method thereof |
| US6319851B1 (en) | 1999-02-03 | 2001-11-20 | Casio Computer Co., Ltd. | Method for packaging semiconductor device having bump electrodes |
| JP3223283B2 (en) | 1999-09-14 | 2001-10-29 | カシオ計算機株式会社 | Method for manufacturing semiconductor device |
| JP4898396B2 (en) * | 2006-11-17 | 2012-03-14 | 太陽誘電株式会社 | Elastic wave device |
-
1990
- 1990-04-12 JP JP2095056A patent/JP2830351B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159837A (en) * | 1998-07-16 | 2000-12-12 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
| CN100435297C (en) * | 2003-09-30 | 2008-11-19 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03293740A (en) | 1991-12-25 |
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