JP2812599B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2812599B2 JP2812599B2 JP2111492A JP2111492A JP2812599B2 JP 2812599 B2 JP2812599 B2 JP 2812599B2 JP 2111492 A JP2111492 A JP 2111492A JP 2111492 A JP2111492 A JP 2111492A JP 2812599 B2 JP2812599 B2 JP 2812599B2
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- Japan
- Prior art keywords
- oxide film
- film
- silicon oxide
- semiconductor device
- concave portion
- Prior art date
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- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の製造方
法に関し、より詳しくは、ＴＥＯＳ(テトラ・エトキシ
・シラン)−Ｏ3系常圧ＣＶＤ(化学気相成長)法を用いて
成膜を行うことにより、半導体基板上の凹凸を平坦化す
る半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a semiconductor device, and more particularly, a film is formed using a TEOS (tetraethoxysilane) -O 3 based atmospheric pressure CVD (chemical vapor deposition) The present invention relates to a method for manufacturing a semiconductor device which planarizes unevenness on a semiconductor substrate by performing the method.
【０００２】[0002]
【従来の技術】半導体素子の高密度化,高集積化に伴っ
て、半導体基板上の凹凸を平坦化する成膜技術が重要性
を増している。現在、成膜法としてＳiＨ4(シラン)−Ｏ
2系常圧ＣＶＤ法とＴＥＯＳ−Ｏ2系プラズマＣＶＤ法が
広く採用されているが、ＳiＨ4−Ｏ2系常圧ＣＶＤ法で
は、微細化が進んでくると、図５に示すように、下地９
０の段差上の部分１００aがオーバハング形状となり、
しかも、膜１００中にボイド(気泡)が発生するという問
題がある。また、ＴＥＯＳ−Ｏ2系プラズマＣＶＤ法で
は、図６に示すように、下地９０の断面に沿ったいわゆ
るコンフォーマル形状の膜２００しか得ることができな
い。2. Description of the Related Art Along with the increase in the density and integration of semiconductor elements, a film forming technique for flattening irregularities on a semiconductor substrate has become increasingly important. At present, SiH 4 (silane) -O is used as a film forming method.
Although 2 an atmospheric pressure CVD method and the TEOS-O 2 based plasma CVD method has been widely adopted, the SiH 4 -O 2 system atmospheric pressure CVD method, the come progressed miniaturization, as shown in FIG. 5, Base 9
The portion 100a on the step of 0 has an overhang shape,
In addition, there is a problem that voids (bubbles) are generated in the film 100. Further, in the TEOS-O 2 plasma CVD method, as shown in FIG. 6, only a so-called conformal film 200 along the cross section of the base 90 can be obtained.
【０００３】最近になって、ＴＥＯＳ−Ｏ3系常圧ＣＶ
Ｄ法が注目されている。ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法
では、Ｏ3濃度を調節することによって、図７に示すよ
うに、エッジ部分３００aがやや薄くなったいわゆるリ
フロー形状の膜３００を成長できるからである(なお、
比較のため、破線で等方成長のラインを示してい
る。)。また、膜３００中のボイドも比較的少ないとい
う特長を有する。そこで、従来は、下地９０の凹凸を平
坦化するために、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法によ
り、下地９０の上に直接シリコン酸化膜３００を成長さ
せていた。なお、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法は、Ｔ
ＥＯＳ(例えばＮ2ガスでバブリングしたもの)とＯ3(Ｏ2
をキャリアガスとする)とを温度４００℃程度に保持し
た基板に導き、常圧下で化学反応させて、上記基板にシ
リコン酸化膜を成長させる方法である。Recently, TEOS-O 3 system normal pressure CV
Attention is paid to the D method. This is because in the TEOS-O 3 -based normal pressure CVD method, by adjusting the O 3 concentration, a so-called reflow-shaped film 300 having a slightly thinner edge portion 300a can be grown as shown in FIG.
For comparison, a broken line indicates an isotropic growth line. ). Further, the film 300 has a feature that voids in the film 300 are relatively small. Therefore, conventionally, in order to planarize the unevenness of the underlying 90, the TEOS-O 3 based atmospheric pressure CVD method, had grown silicon oxide film 300 directly on the base 90. It should be noted that the TEOS-O 3 -based atmospheric pressure CVD method uses T
EOS (eg, bubbling with N 2 gas) and O 3 (O 2
Is used as a carrier gas) to a substrate maintained at a temperature of about 400 ° C., and chemically reacted under normal pressure to grow a silicon oxide film on the substrate.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上に述べた
ように下地９０の上に直接シリコン酸化膜３００を成長
させる場合、確かにエッジ部分３００aの形状を緩和す
ることができる。しかしながら、下地９０の凹凸による
段差がそのまま表面側に反映するため、有効に平坦化を
進めたということはできない。When the silicon oxide film 300 is grown directly on the underlayer 90 as described above, the shape of the edge portion 300a can be certainly relaxed. However, since the step due to the unevenness of the base 90 is directly reflected on the surface side, it cannot be said that the flattening has been effectively advanced.
【０００５】そこで、この発明の目的は、下地の凹凸に
よる段差を低減でき、一歩進んだ平坦化を行うことがで
きる半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing a step due to unevenness of a base and performing flattening one step further.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、請求項１に記載の半導体装置の製造方法は、凹凸を
有する下地の上に、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法によ
りシリコン酸化膜を成長させて、上記下地の凹凸を平坦
化する半導体装置の製造方法であって、上記下地の凹部
の内面のうちの少なくとも側面に、上記シリコン酸化膜
の成長を上記下地よりも増速する材料からなる膜を設け
た後、上記シリコン酸化膜の成長を行うことを特徴とし
ている。To achieve the above object, according to an aspect of manufacturing method of a semiconductor device according to claim 1, on a base having an irregular, silicon oxide film by TEOS-O 3 based atmospheric pressure CVD method A method of manufacturing a semiconductor device for flattening the irregularities of the underlayer by growing the material, wherein at least a side surface of the inner surface of the concave portion of the underlayer has a material for accelerating the growth of the silicon oxide film over the underlayer. The method is characterized in that the silicon oxide film is grown after providing a film made of
【０００７】請求項２に記載の半導体装置の製造方法
は、請求項１に記載の半導体装置の製造方法において、
上記シリコン酸化膜の成長を上記下地よりも増速する材
料からなる膜を、上記下地の凹部の側面及び底面に設け
ることを特徴とする。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect.
A film made of a material that accelerates the growth of the silicon oxide film over the underlayer is provided on the side surface and the bottom surface of the concave portion of the underlayer.
【０００８】[0008]
【作用】この発明は、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法に
よるシリコン酸化膜を種々の下地の上に形成する実験に
より、本発明者が創出したものである。本発明者は、Ｔ
ＥＯＳ−Ｏ3系常圧ＣＶＤ法によるシリコン酸化膜の成
膜速度が、下地の種類によって次表１のように変化する
ことを発見した。[Action] The present invention, experiments for forming a silicon oxide film by TEOS-O 3 based atmospheric pressure CVD method on the various underlying one in which the present inventor has created. The inventor believes that T
It has been found that the film formation rate of the silicon oxide film by the EOS-O 3 -based normal pressure CVD method changes as shown in the following Table 1 depending on the type of the underlayer.
【表１】 [Table 1]
【０００９】したがって、下地の凹部の内面のうちの少
なくとも側面に、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法による
シリコン酸化膜の成長を上記下地よりも増速する材料か
らなる膜(表１に基づいて選択する)を設けた後、上記シ
リコン酸化膜の成長を行う場合、下地の凸部上に比して
上記凹部上で膜厚が厚くなる。この結果、下地の凹凸に
よる段差が低減され、従来に比して平坦化が推進され
る。Therefore, a film made of a material that accelerates the growth of the silicon oxide film by the TEOS-O 3 -based atmospheric pressure CVD method at least on the side of the inner surface of the concave portion of the underlayer (based on Table 1). In the case where the silicon oxide film is grown after providing (selection), the film thickness is larger on the concave portion than on the convex portion of the base. As a result, the step due to the unevenness of the base is reduced, and flattening is promoted as compared with the related art.
【００１０】また、上記シリコン酸化膜の成長を上記下
地よりも増速する材料からなる膜を、上記下地の凹部の
側面及び底面に設ける場合、下地の凸部上に比して上記
凹部上で膜厚がさらに厚くなる。この結果、下地の凹凸
による段差がさらに低減され、さらに平坦化が推進され
る。In the case where a film made of a material which accelerates the growth of the silicon oxide film over the underlayer is provided on the side and bottom surfaces of the underlayer recess, the film is formed on the recess in comparison with the protrusion on the underlayer. The film thickness is further increased. As a result, the step due to the unevenness of the base is further reduced, and flattening is further promoted.
【００１１】[0011]
【実施例】以下、この発明の半導体装置の製造方法を実
施例により詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to embodiments.
【００１２】図１(a)に示すように、半導体基板(図示せ
ず)上に、下地として熱酸化膜(ＳiＯ2膜)１が設けら
れ、その表面に凹部１b,凸部１tが形成されているもの
とする。熱酸化膜１の凹凸による段差は０.３〜０.６μ
m、凹部１b,凸部１tの幅はそれぞれ０.３〜１.０μmと
なっている。この熱酸化膜１の凹凸を平坦化する場合、
まず、上記凹部１bの底面に、ＴＥＯＳ−Ｏ3系常圧ＣＶ
Ｄ法によるシリコン酸化膜の成長を上記熱酸化膜１より
も増速するＳiＮ膜(シリコン窒化膜)２を設ける(表１に
基づく。)。このＳiＮ膜２の膜厚は５００〜１０００Å
とし、例えばＬＰＣＶＤ法(減圧化学気相成長法)により
設ける。この後、同図(b)に示すように、ＴＥＯＳ−Ｏ3
系常圧ＣＶＤ法により、シリコン酸化膜３の成長を行
う。このシリコン酸化膜３の膜厚は、凸部１t上で０.２
〜０.６μmとする。このようにした場合、凸部１t上に
比して凹部１b上でシリコン酸化膜３の膜厚を厚く成長
することができる。したがって、熱酸化膜１の凹凸によ
る段差を低減でき、従来に比して平坦化を推進すること
ができる。As shown in FIG. 1A, a thermal oxide film (SiO 2 film) 1 is provided as a base on a semiconductor substrate (not shown), and a concave portion 1b and a convex portion 1t are formed on the surface thereof. It is assumed that Step due to unevenness of thermal oxide film 1 is 0.3 to 0.6 μm
m, the width of the concave portion 1b, and the width of the convex portion 1t are each 0.3 to 1.0 μm. When the unevenness of the thermal oxide film 1 is flattened,
First, a TEOS-O 3 system normal pressure CV is placed on the bottom of the concave portion 1b.
A SiN film (silicon nitride film) 2 is provided to accelerate the growth of the silicon oxide film by the D method as compared with the thermal oxide film 1 (based on Table 1). The thickness of the SiN film 2 is 500 to 1000 °.
And provided by, for example, an LPCVD method (a low pressure chemical vapor deposition method). Thereafter, as shown in FIG. (B), TEOS-O 3
The silicon oxide film 3 is grown by a system normal pressure CVD method. The thickness of the silicon oxide film 3 is 0.2 on the protrusion 1t.
〜0.6 μm. In this case, the silicon oxide film 3 can be grown thicker on the concave portion 1b than on the convex portion 1t. Therefore, a step due to the unevenness of the thermal oxide film 1 can be reduced, and flattening can be promoted as compared with the related art.
【００１３】なお、図２(a)に示すように、まず、上記
熱酸化膜１の凹部１bの側面（凸部１tの側面でもあ
る。）にＳiＮ膜１２を設けるようにしても良い。上の
例と同様に、このＳiＮ膜１２の膜厚は５００〜１００
０Åとし、例えばＬＰＣＶＤ法(減圧化学気相成長法)に
より設ける。この後、同図(b)に示すように、ＴＥＯＳ
−Ｏ3系常圧ＣＶＤ法により、シリコン酸化膜１３の成
長を行う。このシリコン酸化膜１３の膜厚は、凸部１t
上で０.２〜０.６μmとする。このようにした場合、凸
部１t上に比して凹部１b上でシリコン酸化膜１３の膜厚
を厚く成長することができる。したがって、熱酸化膜１
の凹凸による段差を低減でき、従来に比して平坦化を推
進することができる。As shown in FIG. 2A, first, a SiN film 12 may be provided on the side surface of the concave portion 1b (also the side surface of the convex portion 1t) of the thermal oxide film 1. As in the above example, the thickness of the SiN film 12 is 500 to 100.
0 °, for example, by LPCVD (low pressure chemical vapor deposition). Thereafter, as shown in FIG.
The -O 3 an atmospheric pressure CVD method, to grow a silicon oxide film 13. The thickness of this silicon oxide film 13 is
The thickness is set to 0.2 to 0.6 μm. In this case, the silicon oxide film 13 can be grown thicker on the concave portion 1b than on the convex portion 1t. Therefore, thermal oxide film 1
Can be reduced, and flattening can be promoted as compared with the related art.
【００１４】さらに、図３(a)に示すように、まず、上
記熱酸化膜１の凹部１bの底面および凹部１bの側面（凸
部１tの側面でもある。）にＳiＮ膜２２を設けるように
しても良い。上記各例と同様に、このＳiＮ膜２２の膜
厚は５００〜１０００Åとし、例えばＬＰＣＶＤ法(減
圧化学気相成長法)により設ける。この後、同図(b)に示
すように、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法により、シリ
コン酸化膜２３の成長を行う。このシリコン酸化膜２３
の膜厚は、凸部１t上で０.２〜０.６μmとする。このよ
うにした場合、凸部１t上に比して凹部１b上でシリコン
酸化膜２３の膜厚を厚く成長することができる。したが
って、熱酸化膜１の凹凸による段差を低減でき、従来に
比して平坦化を推進することができる。Further, as shown in FIG. 3A, first, a SiN film 22 is provided on the bottom surface of the concave portion 1b and the side surface of the concave portion 1b (also the side surface of the convex portion 1t) of the thermal oxide film 1. May be. As in the above examples, the SiN film 22 has a thickness of 500 to 1000 Å and is provided by, for example, LPCVD (low pressure chemical vapor deposition). Thereafter, as shown in FIG. 3B, a silicon oxide film 23 is grown by a TEOS-O 3 system normal pressure CVD method. This silicon oxide film 23
Has a thickness of 0.2 to 0.6 μm on the projection 1t. In this case, the silicon oxide film 23 can be grown thicker on the concave portion 1b than on the convex portion 1t. Therefore, a step due to the unevenness of the thermal oxide film 1 can be reduced, and flattening can be promoted as compared with the related art.
【００１５】次に、図４(a)に示すように、半導体基板
(図示せず)上に、下地としてポリシリコン膜(ポリＳi)
３１が設けられ、その表面に凹部３１b,凸部３１tが形
成されているものとする。ポリシリコン膜３１の凹凸に
よる段差は０.３〜０.６μm、凹部３１b,凸部３１tの幅
はそれぞれ０.３〜１.０μmとなっている。このポリシ
リコン膜３１の凹凸を平坦化する場合、まず、上記凸部
３１tの上面に、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法によるシ
リコン酸化膜の成長を上記ポリシリコン膜１よりも減速
するＳiＯ2膜３２を設ける(表１に基づく。)。このＳi
Ｏ2膜３２の膜厚は５００〜１０００Åとし、例えばプ
ラズマＣＶＤ法により設ける。この後、同図(b)に示す
ように、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法により、シリコ
ン酸化膜３３の成長を行う。このシリコン酸化膜３３の
膜厚は、凸部１t上で０.２〜０.６μmとする。このよう
にした場合、凹部１b上に比して凸部１t上でシリコン酸
化膜３３の膜厚を薄く成長することができる。したがっ
て、ポリシリコン膜３１の凹凸による段差を低減でき、
従来に比して平坦化を推進することができる。Next, as shown in FIG.
(Not shown), a polysilicon film (polySi) as a base
31 are provided, and a concave portion 31b and a convex portion 31t are formed on the surface thereof. The step due to the unevenness of the polysilicon film 31 is 0.3 to 0.6 μm, and the width of the concave portion 31b and the convex portion 31t is 0.3 to 1.0 μm, respectively. In planarizing unevenness of the polysilicon film 31, first, the upper surface of the convex portion 31 t, SiO 2 to decelerate than the polysilicon film 1 the growth of the silicon oxide film by TEOS-O 3 based atmospheric pressure CVD method A film 32 is provided (based on Table 1). This Si
The O 2 film 32 has a thickness of 500 to 1000 ° and is provided by, for example, a plasma CVD method. Thereafter, as shown in FIG. 2B, a silicon oxide film 33 is grown by a TEOS-O 3 system normal pressure CVD method. The thickness of the silicon oxide film 33 is set to 0.2 to 0.6 μm on the projection 1t. In this case, the silicon oxide film 33 can be grown thinner on the convex portion 1t than on the concave portion 1b. Therefore, the step due to the unevenness of the polysilicon film 31 can be reduced,
Flattening can be promoted as compared with the related art.
【００１６】[0016]
【発明の効果】以上より明らかなように、請求項１の半
導体装置の製造方法は、凹凸を有する下地の上に、ＴＥ
ＯＳ−Ｏ3系常圧ＣＶＤ法によりシリコン酸化膜を成長
させて、上記下地の凹凸を平坦化する半導体装置の製造
方法であって、上記下地の凹部の内面のうちの少なくと
も側面に、上記シリコン酸化膜の成長を上記下地よりも
増速する材料からなる膜を設けた後、上記シリコン酸化
膜の成長を行っているので、下地の凸部上に比して上記
凹部上で上記シリコン酸化膜の膜厚を厚く成長すること
ができる。したがって、下地の凹凸による段差を低減で
き、従来に比して平坦化を一層推進することができる。As is apparent from the above description, the method of manufacturing a semiconductor device according to the first aspect of the present invention includes the steps of:
And a silicon oxide film is grown by OS-O 3 based atmospheric pressure CVD method, a manufacturing method of a semiconductor device for planarizing the unevenness of the underlying, at least the side surface of the inner surface of the recess of the base, the silicon Since the silicon oxide film is grown after providing a film made of a material that accelerates the growth of the oxide film over the base, the silicon oxide film is formed on the concave portion as compared with the convex portion of the base. Can be grown thick. Therefore, a step due to the unevenness of the base can be reduced, and flattening can be further promoted as compared with the related art.
【００１７】また、請求項２の半導体装置の製造方法
は、上記シリコン酸化膜の成長を上記下地よりも増速す
る材料からなる膜を、上記下地の凹部の側面及び底面に
設ける場合、下地の凸部上に比して上記凹部上で膜厚が
さらに厚くなる。この結果、下地の凹凸による段差をさ
らに低減でき、さらに平坦化を推進できる。According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, when a film made of a material for accelerating the growth of the silicon oxide film is provided on the side surface and the bottom surface of the concave portion of the base, The film thickness is further increased on the concave portion than on the convex portion. As a result, a step due to the unevenness of the base can be further reduced, and flattening can be further promoted.
【図１】 この発明の一実施例の半導体装置の製造方法
を説明する工程図である。FIG. 1 is a process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】 この発明の一実施例の半導体装置の製造方法
を説明する工程図である。FIG. 2 is a process chart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
【図３】 この発明の一実施例の半導体装置の製造方法
を説明する工程図である。FIG. 3 is a process diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
【図４】 この発明の一実施例の半導体装置の製造方法
を説明する工程図である。FIG. 4 is a process chart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention;
【図５】 ＳiＨ4−Ｏ2系常圧ＣＶＤ法により平坦化を
行った状態を示す図である。FIG. 5 is a diagram showing a state where planarization is performed by a SiH 4 —O 2 system normal pressure CVD method.
【図６】 ＴＥＯＳ−Ｏ2系プラズマＣＶＤ法により平
坦化を行った状態を示す図である。FIG. 6 is a diagram showing a state where planarization is performed by a TEOS-O 2 plasma CVD method.
【図７】 ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法により、下地
に直接シリコン酸化膜を成長させて平坦化を行った状態
を示す図である。FIG. 7 is a diagram showing a state in which a silicon oxide film is directly grown on an underlayer and planarized by a TEOS-O 3 system normal pressure CVD method.
１ 熱酸化膜 １b,３１b 凹部 １t,３１t 凸部 ２,１２,２２ ＳiＮ膜 ３,１３,２３,３３ シリコン酸化膜 ３１ ポリシリコン膜 ３２ プラズマＳiＯ2膜Reference Signs List 1 thermal oxide film 1b, 31b concave portion 1t, 31t convex portion 2, 12, 22 SiN film 3, 13, 23, 33 silicon oxide film 31 polysilicon film 32 plasma SiO 2 film
Claims (2)
3系常圧ＣＶＤ法によりシリコン酸化膜を成長させて、
上記下地の凹凸を平坦化する半導体装置の製造方法であ
って、 上記下地の凹部の内面のうちの少なくとも側面に、上記
シリコン酸化膜の成長を上記下地よりも増速する材料か
らなる膜を設けた後、上記シリコン酸化膜の成長を行う
ことを特徴とする半導体装置の製造方法。1. A TEOS-O film is provided on an uneven base.
A silicon oxide film is grown by 3 system normal pressure CVD method,
What is claimed is: 1. A method for manufacturing a semiconductor device, comprising: flattening irregularities of an underlayer, wherein a film made of a material for accelerating the growth of the silicon oxide film is provided on at least a side surface of the inner surface of the concave portion of the underlayer. And then growing the silicon oxide film.
において、 上記シリコン酸化膜の成長を上記下地よりも増速する材
料からなる膜を、上記下地の凹部の側面及び底面に設け
ることを特徴とする半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein a film made of a material for accelerating the growth of the silicon oxide film over the underlayer is provided on a side surface and a bottom surface of the concave portion of the underlayer. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2111492A JP2812599B2 (en) | 1992-02-06 | 1992-02-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2111492A JP2812599B2 (en) | 1992-02-06 | 1992-02-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218031A JPH05218031A (en) | 1993-08-27 |
| JP2812599B2 true JP2812599B2 (en) | 1998-10-22 |
Family
ID=12045860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2111492A Expired - Fee Related JP2812599B2 (en) | 1992-02-06 | 1992-02-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2812599B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19629766C2 (en) * | 1996-07-23 | 2002-06-27 | Infineon Technologies Ag | Manufacturing method of shallow trench isolation areas in a substrate |
| US6541401B1 (en) * | 2000-07-31 | 2003-04-01 | Applied Materials, Inc. | Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate |
| JP6583081B2 (en) * | 2016-03-22 | 2019-10-02 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
-
1992
- 1992-02-06 JP JP2111492A patent/JP2812599B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218031A (en) | 1993-08-27 |
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