JP2812316B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2812316B2 JP2812316B2 JP8306461A JP30646196A JP2812316B2 JP 2812316 B2 JP2812316 B2 JP 2812316B2 JP 8306461 A JP8306461 A JP 8306461A JP 30646196 A JP30646196 A JP 30646196A JP 2812316 B2 JP2812316 B2 JP 2812316B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- insulating adhesive
- connection portion
- electrode connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置の製造
方法に係り、特に、フェ―スダウンボンディング法に関
する。
【０００２】
【従来の技術】半導体集積回路等の半導体チップをパッ
ケ―ジあるいは配線基板上に組み込むに際し、半導体チ
ップをフェ―スダウンすなわち下向きにし電極部との接
続をワイヤでなく、より広い面積を持った面で接続する
フェ―スダウンボンディング法は、ワイヤボンディング
を伴うフェ―スアップボンディング法に比べて、接続後
の機械的強度が強く、ボンディングすなわち接続の回数
も１回で済むことから有益な方法であるとされている。
【０００３】このフェ―スダウンボンディング法では通
常、半導体チップの電極部にあらかじめバンプを形成し
ておき下向きに融着して接続する（フリップチップ方
式）か又は、基板上の電極部にあらかじめバンプを形成
しておき、半導体チップを下向きにして融着する（ペデ
スタル方式）かの方式により半導体チップと基板（パッ
ケ―ジ）との接続を行なうようにしている。
【０００４】このバンプはクロム（Ｃｒ）−銅（Ｃ
ｕ），アルミニウム（Ａｌ）−シリコン（Ｓｉ），アル
ミニウム−銅，アルミニウム−銅−シリコン，鉛 （Ｐ
ｂ）−錫（Ｓｎ）等の合金、チタン（Ｔｉ），アルミニ
ウム，クロム，ニッケル等の金属あるいはこれらの積層
体から構成されており、基板上の所望の位置に半導体チ
ップを載置した状態で２００〜５００℃の高温に加熱
し、融着することにより電気的接続を達成するものであ
る。
【０００５】
【発明が解決しようとする課題】しかるに、これらの方
法では、
(1) バンプ形成に要する工程が複雑でコストが高い。
【０００６】(2) バンプを溶融状態に加熱する際、ク
ラックが発生し易い。
【０００７】(3) 半導体チップ内の素子領域にバンプ
を構成する金属が拡散し、素子の特性が劣化する。
【０００８】(4) バンプを構成する金属が加熱溶融す
る際に流れ、ショ―トが発生する等により、製造歩留り
が悪い。
【０００９】等の不都合があった。
【００１０】本発明は前記実情に鑑みてなされたもの
で、上記不都合を廃し、製造が容易で、信頼性の高い半
導体装置の実装方法を提供することを目的とする。
【００１１】
【課題を解決するための手段】そこで本発明の方法で
は、配線パタ―ンを具えた基板上に半導体集積回路素子
等からなる半導体チップを実装するに際し、該基板上の
電極接続部を除く所定の位置に熱硬化性の絶縁性接着剤
を塗布し、該基板上の所定の位置に前記半導体チップを
載置して、加圧し、該基板の電極接続部と該半導体チッ
プとの電気的接続が可能となるように、加熱し、該基板
上に該半導体チップを融着せしめるようにしたことを特
徴とする。
【００１２】つまり、本発明の第１では、配線パターン
を具えた基板上に半導体集積回路素子等の半導体チップ
を実装するに際し、該基板面の電極接続部を除く所定の
位置に、選択的に熱収縮性かつ熱硬化性の絶縁性接着剤
を塗布する塗布工程と、該半導体チップで、該絶縁性接
着剤を前記所定の位置より該電極接続部からはみ出す位
置まで押し出すとともに、該基板の電極接続部と該半導
体チップの接続部とを互いに当接させ、該絶縁性接着剤
の硬化による収縮力により、該基板と該半導体チップの
電極接続部間は直接接触状態で電気的接続が可能となる
ように、該基板と該半導体チップとを加圧後加熱し、該
基板上に該半導体チップを接着せしめる接着工程とを具
えたことを特徴とする。
【００１３】望ましくは、前記基板は電極接続部として
の電極パッド上にバンプを形成してなるものであること
を特徴とする。
【００１４】また望ましくは、前記半導体チップは電極
接続部としてのバンプを形成してなるものであることを
特徴とする。
【００１５】また望ましくは、前記固着工程の後、前記
半導体チップの周囲を覆うように樹脂被覆を行う樹脂封
止工程を含むことを特徴とする。
【００１６】本発明の第２によれば、配線パタ―ンを具
えた基板上に半導体集積回路素子等からなる半導体チッ
プを実装するに際し、該基板上の電極接続部を除く所定
の位置に熱硬化性の絶縁性接着剤を塗布する塗布工程
と、該基板上の所定の位置に前記半導体チップを載置
し、加圧により、該絶縁性接着剤を前記所定の位置より
該電極接続部からはみ出す位置まで押し出すとともに、
該基板の電極接続部と該半導体チップの接続部とを互い
に当接させ、仮接着する仮接着工程と、加熱して前記絶
縁性接着剤を収縮せしめながら、硬化させ、基板の前記
電極接続部と該半導体チップの接続部とを加圧状態で接
触させる一方、その周りの該基板と該半導体チップ面と
の間を前記絶縁性接着剤で固着せしめ、該基板上に該半
導体チップを固着せしめるようにしたことを特徴とす
る。
【００１７】また望ましくは、前記固着工程は、該基板
とこの上に搭載される半導体チップ面との間に形成され
る間隙が完全に充填されるように、該基板上に該半導体
チップを固着せしめる工程であることを特徴とする。
【００１８】すなわち本発明では、基板面の電極接続部
を除く所定の位置に、選択的に熱収縮性かつ熱硬化性の
絶縁性接着剤を塗布し、絶縁性接着剤を押し出しながら
両者を加圧した後加熱し、前記絶縁性接着剤を収縮せし
めながら、接着剤の硬化による接着を行う。
【００１９】つまり、絶縁性接着剤の塗布直後は基板上
の電極接続部には、この絶縁性接着剤が付着しておら
ず、半導体チップによる接着剤の押し出しにより、電極
接続部まで到達し、基板上の電極接続部と半導体チップ
の電極接続部とが当接した後、更に絶縁性接着剤は電極
接続部からはみ出す位置まで押し出される。この後、加
熱された接着剤は硬化反応により収縮し、半導体チップ
と基板の間の密着性を向上し、基板と半導体チップの電
極接続部間は加圧状態で接触し、良好な電気的接続が可
能となる。
【００２０】かかる構成によれば、半導体チップを配線
基板上に搭載するに際し、基板の電極接続部と半導体チ
ップの接続部とは加圧状態で直接接触することによって
のみ電気的接続を達成する一方、その周囲の半導体チッ
プと基板との間の間隙に絶縁性接着剤を充填し硬化させ
ることにより相互に固着し、物理的接続を達成する。
【００２１】この接続状態を得るため、本願発明の方法
では、基板面の電極接続部を除く所定の位置に、選択的
に熱収縮性かつ熱硬化性の絶縁性接着剤を塗布し、絶縁
性接着剤を押し出しながら両者を加圧したのち加熱し、
前記絶縁性接着剤を収縮せしめながら、接着剤の硬化に
よる接着を行う。
【００２２】つまり、絶縁性接着剤の塗布直後は基板上
の電極接続部には、この絶縁性接着剤が付着しておら
ず、半導体チップによる接着剤の押し出しにより、電極
接続部まで到達し、基板上の電極接続部と半導体チップ
の電極接続部とが当接した後、更に絶縁性接着剤は電極
接続部からはみ出す位置まで押し出される。この後、加
熱された接着剤は硬化反応により収縮し、半導体チップ
と基板の間の密着性を向上し、基板と半導体チップの電
極接続部間は加圧状態で接触し、良好な電気的接続が可
能となるもので、
1．加熱により体積が縮小する性質すなわち熱収縮性を
もつ絶縁性接着剤を用いること
2．基板面の電極接続部をのぞく領域に絶縁性接着剤を
塗布すること
3 . 電極接続部を除く領域に塗布された絶縁性接着剤を
該電極接続部からはみ出す位置まで押し出すように、加
圧すること
4． 加圧後加熱すること
以上４つの構成条件を合わせて具備してはじめて本願発
明は達成されることになる。
【００２３】従ってかかる構成により、絶縁性接着剤を
電極接続部からはみ出す位置まで押し出し、硬化するこ
とにより、電極接続部の周囲を絶縁性樹脂によって固着
するとともに良好に絶縁しており、高密度化に際して
も、隣接電極間のショートの発生もない。（本願の明細
書第１図(c) からも明らかなように、固着したとき絶縁
性接着剤は収縮して強固に固着し、また隣接電極間には
絶縁性接着剤が充填されているため、リーク電流のパス
は皆無となる上、より強固に固定することができる。）
また、半導体チップで絶縁性接着剤を押し出すため、行
き渡らなかった個所に接着剤を注入する工程が不要にな
る。
【００２４】また、電極接続部には絶縁性接着剤は塗布
されていないためこれを押し出す必要はなく、また電極
接続部への絶縁性接着剤の付着に伴う高抵抗化あるいは
接触不良を減少させることができる。また、チップと基
板の電極接続部間にははんだなどの導電性接着剤も介在
しないため、周囲への流出によるショートなどのおそれ
もない。また、単純な垂直加圧により、容易に接続が達
成され、また前記絶縁性接着剤の収縮により、各導電性
パターンと電極接続部との間が均一に加圧され電気的接
触性がより高められる。
【００２５】さらに、接合すべき基板上の電極接続部が
接着剤に覆われていないため、半導体チップの実装に際
し、位置合せが容易になる。
【００２６】また加圧状態で加熱すれば、空気を押し出
しながら接着せしめられるため、長期にわたって安定で
信頼性の高い接着が可能となる。また電極接続部自体は
固着されておらず、周囲のみで固着されている構造であ
るため、接続不良の発生時には、溶剤のみで簡単に剥離
でき、再度使用可能である。さらにまた、基板側にバン
プを形成すれば、絶縁性接着剤は、チップによる加圧に
よって押し出される際、基板面から突出するバンプの先
端をぬらすことなく、周りを良好に被覆し、バンプ先端
すなわち電極接続部の電気的接続を行う領域は半導体チ
ップ表面に良好に直接接触し、その周りは完全に絶縁性
接着剤で覆われることになり、より信頼性の高い接続を
達成することが可能となる。
【００２７】
【発明の実施の形態】すなわち、例えば、図１（ａ）に
示す如く半導体チップの電極部１ａに金属のバンプ２を
形成すると共に、基板３上の電極接続部３ａを除く所定
位置に熱収縮性であってかつ熱硬化性の絶縁性接着剤４
を充填する。
【００２８】そして、図１（ｃ）に示す如く基板上に半
導体チップを載置し加圧して仮接着した後、加圧しつつ
リフロ―炉で加熱し接着剤を硬化させる。
【００２９】このとき、接着剤は、硬化反応が進むにつ
れて、溶媒や反応生成物の揮発により、収縮するため、
半導体チップと基板の電極間での密着性が増し、電気的
接続性が向上する。
【００３０】このようにして確実な接続が可能となる。
【００３１】また、半導体チップの電極部にバンプを形
成する代わりに、図１（ｂ）に示す如く、基板３上の電
極接続部３ａにバンプ２を形成するようにしてもよい。
【００３２】
【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。
【００３３】第２図（ａ）乃至（ｄ）は、イメ―ジセン
サの駆動用ＩＣの実装工程を示す図である。
【００３４】まず、第２図（ａ）に示す如く、ガラス基
板 １１上に、受光素子部との接続用の金薄膜からなる
配線パタ―ン（信号引き出し線）１２を形成し、このう
ちの電極パッド部１２ａ上に、厚膜法により膜厚１μｍ
のアルミニウム（Ａｌ）からなるバンプ１３を形成す
る。
【００３５】次いで、第２図（ｂ）に示す如くレジンコ
―タにより、熱硬化型のエポキシ接着剤１４を順次、該
基板上の所定の位置に充填する。
【００３６】続いて、第２図（ｃ）に示す如く、１４３
ピンの駆動用ＩＣ１５を順次、該基板上の配線パタ―ン
１２の所定位置に載置し、加圧により仮接着する。
【００３７】そして最後に、シリコ―ン系の封止用樹脂
１６をレジンコ―タにより塗布し、リフロ―炉に入り、
１５０℃３０分で接着剤および封止樹脂を同時に硬化さ
せ、第２図（ｄ）に示す如く、駆動用ＩＣの接着および
封止を行なう。
【００３８】このようにして、１回の加熱工程で、多数
個の半導体チップの実装を行なうことができ、極めて作
業性が良好である上、電極間が、加圧状態で接着されて
いるため、電気的接続性が良好で信頼性も高い、また、
バンプは融着ではなく、押圧状態で、駆動用ＩＣの電極
部に接触していればよいため、加熱温度も低く（接着剤
の硬化温度）、素子領域へのバンプ構成金属の拡散等に
よる素子特性の劣化もない。
【００３９】更に、仮に接続不良が発生した場合、有機
溶剤等で、接着剤を融解除去するのみで、再使用するこ
とができるため、歩留りが向上する。
【００４０】加えて、ワイヤボンディング法等による実
装に加えて占有面積が小さいため、実装密度を上げるこ
とができ、装置の小形化をはかることができる。なお、
実施例ではイメ―ジセンサの駆動用ＩＣを複数個実装す
る場合について説明したが、単一の半導体チップの実装
あるいはハイブリッドＩＣの製造をはじめ、いろいろな
場合に適用可能であり、この方法はワイヤボンディング
実装や、タブ（ＴＡＢ）、インナ―リ―ドボンディング
等のギングボンディングに比べ、タクトタイム、材料コ
スト等、ト―タルコストの点でも十分に優れている。
【００４１】また、実施例では、バンプは、基板上に形
成したが、半導体チップ側に形成してもよく、また、回
路パタ―ン上、半導体チップあるいは基板上の電極部が
凸状となっている場合には、特にバンプを形成すること
なく、そのまま使用すればよい。更に、バンプを構成す
る金属については、実施例に限定されることなく、金
（Ｓｕ），銅（Ｃｕ），クロム（Ｃｒ）等あらゆる金属
を使用することが可能である。
【００４２】更に、接着剤は、エポキシ樹脂に限定され
ることなく、シリコ―ン系樹脂、ポリイミド系樹脂等、
熱収縮性であってかつ熱硬化性の接着剤であればよい。
【００４３】
【効果】以上説明してきたように、本発明によれば、絶
縁性の熱硬化性接着剤によって電極接続部以外の部分を
接着せしめることにより基板上の電極接続部と半導体チ
ップ上の電極接続部とが押圧状態で直接当接するように
しているため、接着温度が低い上工程が簡略であってコ
ストも低くかつ、信頼性の高い半導体装置を得ることが
できる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a face-down bonding method. 2. Description of the Related Art When a semiconductor chip such as a semiconductor integrated circuit is mounted on a package or a wiring board, the semiconductor chip is faced down, that is, turned downward, so that a connection with an electrode portion is not a wire but a wider area. The face-down bonding method of connecting on the holding surface is advantageous because the mechanical strength after connection is higher and the bonding, that is, the number of times of connection is only one, as compared with the face-up bonding method involving wire bonding. It is said that it is a method. In the face-down bonding method, usually, a bump is formed in advance on an electrode portion of a semiconductor chip and then connected by fusing downward (flip chip method), or a bump is formed on an electrode portion on a substrate in advance. The semiconductor chip is connected to the substrate (package) by a method of fusing the semiconductor chip downward (pedestal method). The bump is made of chromium (Cr) -copper (C
u), aluminum (Al) -silicon (Si), aluminum-copper, aluminum-copper-silicon, lead (P
b) An alloy such as tin (Sn), a metal such as titanium (Ti), aluminum, chromium, nickel, or a laminate thereof, and a semiconductor chip mounted on a desired position on a substrate. Heating to a high temperature of 200 to 500 ° C. and fusing to achieve electrical connection. However, in these methods, (1) the steps required for forming the bumps are complicated and the cost is high. (2) When a bump is heated to a molten state, cracks are likely to occur. (3) The metal constituting the bumps diffuses into the element region in the semiconductor chip, and the characteristics of the element deteriorate. (4) The production yield is poor because the metal constituting the bumps flows when heated and melted and shorts are generated. There are inconveniences such as: The present invention has been made in view of the above circumstances, and has as its object to provide a method of mounting a semiconductor device which eliminates the above-mentioned disadvantages, is easy to manufacture, and has high reliability. According to the method of the present invention, when a semiconductor chip composed of a semiconductor integrated circuit element or the like is mounted on a substrate provided with a wiring pattern, an electrode connecting portion on the substrate is mounted. A thermosetting insulating adhesive is applied to a predetermined position except for the above, the semiconductor chip is placed at a predetermined position on the substrate, and pressure is applied. The semiconductor chip is heated so that electrical connection is possible, and the semiconductor chip is fused to the substrate. That is, according to the first aspect of the present invention, when a semiconductor chip such as a semiconductor integrated circuit element is mounted on a substrate provided with a wiring pattern, the semiconductor chip is selectively placed at a predetermined position excluding an electrode connection portion on the substrate surface. A coating step of applying a heat-shrinkable and thermosetting insulating adhesive, and extruding the insulating adhesive from the predetermined position to a position protruding from the electrode connection portion with the semiconductor chip; The connection portion and the connection portion of the semiconductor chip are brought into contact with each other, and the substrate and the electrode connection portion of the semiconductor chip can be electrically connected in a direct contact state by a contraction force caused by curing of the insulating adhesive. And a bonding step of pressing the substrate and the semiconductor chip and then heating the semiconductor chip to bond the semiconductor chip to the substrate. Preferably, the substrate is formed by forming a bump on an electrode pad as an electrode connecting portion. Preferably, the semiconductor chip is formed by forming a bump as an electrode connecting portion. Preferably, after the fixing step, the method further comprises a resin sealing step of covering the periphery of the semiconductor chip with a resin. According to the second aspect of the present invention, when a semiconductor chip composed of a semiconductor integrated circuit element or the like is mounted on a substrate provided with a wiring pattern, heat is applied to a predetermined position on the substrate except for an electrode connection portion. A coating step of applying a curable insulating adhesive, placing the semiconductor chip at a predetermined position on the substrate, and pressing the insulating adhesive from the electrode connection portion from the predetermined position to press the semiconductor chip. While pushing to the position where it protrudes,
A temporary bonding step of bringing the electrode connection portion of the substrate and the connection portion of the semiconductor chip into contact with each other and temporarily bonding the same; and heating and shrinking the insulating adhesive to shrink the insulating adhesive. And the connecting portion of the semiconductor chip are brought into contact with each other in a pressurized state, and the surrounding substrate and the semiconductor chip surface are fixed with the insulating adhesive, and the semiconductor chip is fixed on the substrate. It is characterized by doing so. Preferably, in the fixing step, the semiconductor chip is fixed on the substrate so that a gap formed between the substrate and a surface of the semiconductor chip mounted thereon is completely filled. It is characterized in that it is a squeezing step. That is, in the present invention, a heat-shrinkable and thermosetting insulating adhesive is selectively applied to a predetermined position on the substrate surface excluding the electrode connection portion, and both are applied while extruding the insulating adhesive. After the pressure is applied, the adhesive is heated so that the insulating adhesive is shrunk, and the adhesive is bonded by curing. That is, immediately after the application of the insulating adhesive, the insulating adhesive is not adhered to the electrode connecting portion on the substrate, and reaches the electrode connecting portion by extrusion of the adhesive by the semiconductor chip. After the electrode connection portion on the substrate and the electrode connection portion of the semiconductor chip come into contact with each other, the insulating adhesive is further extruded to a position protruding from the electrode connection portion. Thereafter, the heated adhesive shrinks due to the curing reaction, improves the adhesion between the semiconductor chip and the substrate, and makes contact between the substrate and the electrode connection portion of the semiconductor chip in a pressurized state, resulting in good electrical connection. Becomes possible. According to this structure, when the semiconductor chip is mounted on the wiring board, the electrical connection is achieved only by directly contacting the electrode connecting portion of the substrate and the connecting portion of the semiconductor chip in a pressurized state. A gap between the surrounding semiconductor chip and the substrate is filled with an insulative adhesive and cured to be fixed to each other to achieve a physical connection. In order to obtain this connection state, according to the method of the present invention, a heat-shrinkable and thermosetting insulating adhesive is selectively applied to a predetermined position on the substrate surface except for the electrode connection portion. Pressing both while extruding the adhesive, then heating,
Adhesion is performed by curing the adhesive while shrinking the insulating adhesive. That is, immediately after the application of the insulating adhesive, the insulating adhesive is not attached to the electrode connecting portion on the substrate, and reaches the electrode connecting portion by extrusion of the adhesive by the semiconductor chip. After the electrode connection portion on the substrate and the electrode connection portion of the semiconductor chip come into contact with each other, the insulating adhesive is further extruded to a position protruding from the electrode connection portion. Thereafter, the heated adhesive shrinks due to the curing reaction, improves the adhesion between the semiconductor chip and the substrate, and makes contact between the substrate and the electrode connection portion of the semiconductor chip in a pressurized state, resulting in good electrical connection. Is possible. 1. Use an insulating adhesive that has the property of reducing its volume by heating, that is, heat shrinkage. Apply the insulating adhesive to the area other than the electrode connection part on the board surface. 3. Apply pressure so that the insulating adhesive applied to the area other than the electrode connection part is pushed to the position protruding from the electrode connection part. Four. The invention of the present application can be achieved only when the above-mentioned four conditions are combined and heating is performed after pressurization. Therefore, with this configuration, the insulating adhesive is extruded to a position protruding from the electrode connecting portion and is hardened, so that the periphery of the electrode connecting portion is fixed by the insulating resin and is well insulated, thereby achieving high density. In this case, there is no short circuit between adjacent electrodes. (As apparent from FIG. 1 (c) of the specification of the present application, when the insulating adhesive is fixed, the insulating adhesive contracts and firmly adheres, and the insulating adhesive is filled between the adjacent electrodes. In addition, there is no leakage current path, and it can be fixed more firmly.)
In addition, since the insulating adhesive is extruded with the semiconductor chip, a step of injecting the adhesive into a part that has not been spread is unnecessary. Further, since the insulating adhesive is not applied to the electrode connecting portion, it is not necessary to extrude the insulating adhesive, and the resistance increase or the contact failure due to the adhesion of the insulating adhesive to the electrode connecting portion is reduced. be able to. In addition, since no conductive adhesive such as solder is interposed between the chip and the electrode connection portion of the substrate, there is no danger of short-circuit due to outflow to the surroundings. In addition, the connection is easily achieved by simple vertical pressing, and the contraction of the insulating adhesive uniformly pressurizes each conductive pattern and the electrode connecting portion to further increase the electrical contact. Can be Further, since the electrode connection portion on the substrate to be joined is not covered with the adhesive, the positioning becomes easy when mounting the semiconductor chip. Further, by heating in a pressurized state, bonding can be performed while extruding air, so that stable and reliable bonding can be performed for a long period of time. In addition, since the electrode connection portion itself is not fixed, but is fixed only at the periphery, when a connection failure occurs, it can be easily peeled off only with a solvent and can be used again. Furthermore, if the bumps are formed on the substrate side, the insulating adhesive, when extruded by the pressure of the chip, does not wet the tips of the bumps protruding from the substrate surface, but covers the periphery well, and the bump tips, The area where the electrical connection of the electrode connection section makes good direct contact with the semiconductor chip surface, and the surrounding area is completely covered with insulating adhesive, making it possible to achieve a more reliable connection. Become. DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, for example, as shown in FIG. 1A, a metal bump 2 is formed on an electrode portion 1a of a semiconductor chip, and a predetermined position excluding an electrode connection portion 3a on a substrate 3. Heat-shrinkable and thermosetting insulating adhesive 4
Fill. Then, as shown in FIG. 1 (c), the semiconductor chip is placed on the substrate and temporarily bonded by pressing, and then heated in a reflow furnace while pressing to harden the adhesive. At this time, the adhesive shrinks due to the volatilization of the solvent and the reaction product as the curing reaction proceeds.
The adhesion between the electrodes of the semiconductor chip and the substrate is increased, and the electrical connectivity is improved. [0030] In this way, reliable connection can be achieved. Instead of forming bumps on the electrode portions of the semiconductor chip, bumps 2 may be formed on electrode connection portions 3a on substrate 3, as shown in FIG. 1 (b). Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 2 (a) to 2 (d) are views showing a mounting process of a driving IC of the image sensor. First, as shown in FIG. 2 (a), a wiring pattern (signal lead-out line) 12 made of a gold thin film for connection to a light receiving element is formed on a glass substrate 11. A film thickness of 1 μm is formed on the electrode pad portion 12a by a thick film method.
The bump 13 made of aluminum (Al) is formed. Next, as shown in FIG. 2 (b), a thermosetting epoxy adhesive 14 is sequentially filled in a predetermined position on the substrate by a resin coater. Subsequently, as shown in FIG.
The pin driving ICs 15 are sequentially placed at predetermined positions of the wiring pattern 12 on the substrate, and are temporarily bonded by applying pressure. Finally, a silicone-based sealing resin 16 is applied with a resin coater, and the resin enters a reflow furnace.
The adhesive and the sealing resin are simultaneously cured at 150 ° C. for 30 minutes, and the bonding and sealing of the driving IC are performed as shown in FIG. In this way, a large number of semiconductor chips can be mounted in a single heating step, so that the workability is extremely good and the electrodes are bonded under pressure. , Good electrical connectivity and high reliability,
The heating temperature is low (the curing temperature of the adhesive) because the bumps need only be in contact with the electrodes of the driving IC in a pressed state instead of being fused. There is no deterioration of characteristics. Furthermore, if a connection failure occurs, the adhesive can be reused only by melting and removing the adhesive with an organic solvent or the like, thereby improving the yield. In addition, since the occupied area is small in addition to the mounting by the wire bonding method or the like, the mounting density can be increased and the device can be downsized. In addition,
In the embodiment, the case where a plurality of image sensor driving ICs are mounted is described. However, the present invention can be applied to various cases such as mounting a single semiconductor chip or manufacturing a hybrid IC. As compared with the mounting, the tab (TAB), and the ging bonding such as the inner lead bonding, the total cost such as the tact time and the material cost is sufficiently superior. In the embodiment, the bumps are formed on the substrate. However, the bumps may be formed on the semiconductor chip side, and the electrode portions on the circuit pattern, the semiconductor chip or the substrate may have a convex shape. In this case, the bumps may be used without forming any bumps. Further, the metal constituting the bump is not limited to the embodiment, and any metal such as gold (Su), copper (Cu), and chromium (Cr) can be used. The adhesive is not limited to an epoxy resin, but may be a silicone resin, a polyimide resin, or the like.
What is necessary is just a heat-shrinkable and thermosetting adhesive. As described above, according to the present invention, the portions other than the electrode connection portions are adhered to each other by the insulating thermosetting adhesive, so that the electrode connection portions on the substrate and the semiconductor chip are not bonded. Since the electrode connection portion is directly contacted in a pressed state, a highly reliable semiconductor device having a low bonding temperature, a simple process, a low cost, and a low cost can be obtained.
【図面の簡単な説明】
【図１】本発明の半導体装置の実装方法の概略的説明図
である。
【図２】本発明実施例のイメ―ジセンサ駆動用ＩＣの実
装工程図である。
【符号の説明】
１ 半導体チップ、
１ａ 電極接続部、
２ バンプ、
３ 基板、
３ａ 電極接続部、
４ 絶縁性接着剤、
１１ ガラス基板、
１２ 配線パタ―ン、
１２ａ 電極パッド部、
１３ バンプ、
１４ エポキシ接着剤、
１５ 駆動用ＩＣ、
１６ 封止用樹脂。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic explanatory view of a method for mounting a semiconductor device according to the present invention. FIG. 2 is a mounting process diagram of an image sensor driving IC according to the embodiment of the present invention. [Description of Signs] 1 semiconductor chip, 1a electrode connection portion, 2 bump, 3 substrate, 3a electrode connection portion, 4 insulating adhesive, 11 glass substrate, 12 wiring pattern, 12a electrode pad portion, 13 bump, 14 Epoxy adhesive, 15 drive IC, 16 sealing resin.
Claims (1)
等の半導体チップを実装するに際し、 該基板面の電極接続部を除く所定の位置に、選択的に収
縮性かつ硬化性の絶縁性接着剤を選択的に塗布する塗布
工程と、 該半導体チップで、該絶縁性接着剤を前記所定の位置よ
り該電極接続部からはみ出す位置まで押し出すととも
に、該基板の電極接続部と該半導体チップの接続部とを
互いに当接させ、該絶縁性接着剤の硬化による収縮力に
より、該基板と該半導体チップの電極接続部間は直接接
触状態で電気的接続が可能となるように、該基板と該半
導体チップの加圧後該絶縁性接着剤を硬化させて、該基
板上に該半導体チップを接着せしめる接着工程とを具え
た半導体装置の製造方法。 ２．前記基板は電極接続部としての電極パッド上にバン
プを形成してなるものであることを特徴とする請求項１
記載の半導体装置の製造方法。 ３．前記半導体チップは電極接続部としてのバンプを形
成してなるものであることを特徴とする請求項１記載の
半導体装置の製造方法。 ４．前記固着工程の後、前記半導体チップの周囲を覆う
ように樹脂被覆を行う樹脂封止工程を含むことを特徴と
する請求項１記載の半導体装置の製造方法。 ５．配線パターンを具えた基板上に半導体集積回路素子
等からなる半導体チップを実装するに際し、 該基板上の電極接続部を除く所定の位置に硬化性の絶縁
性接着剤を塗布する塗布工程と、 該基板上の所定の位置に前記半導体チップを載置し、加
圧により、該絶縁性接着剤を前記所定の位置より該電極
接続部からはみ出す位置まで押し出すとともに、該基板
の電極接続部と該半導体チップの接続部とを互いに当接
させ、仮接着する仮接着工程と、 前記絶縁性接着剤を収縮させながら硬化させて、基板の
前記電極接続部と該半導体チップの接続部とを加圧状態
で接触させる一方、その周りの該基板と該半導体チップ
面との間を前記絶縁性接着剤で固着せしめ、該基板上に
該半導体チップを固着せしめる固着工程とを具えた半導
体装置の製造方法。 ６．前記固着工程は、該基板とこの上に搭載される半導
体チップ面との間に形成される隙間が完全に充填される
ように、該基板上に該半導体チップを固着せしめるよう
にした工程であることを特徴とする請求項５記載の半導
体装置の製造方法。(57) [Claims] When mounting a semiconductor chip such as a semiconductor integrated circuit element on a substrate having a wiring pattern, a contractible and curable insulating adhesive is selectively selected at a predetermined position on the surface of the substrate except for an electrode connection portion. And applying the insulating adhesive with the semiconductor chip from the predetermined position to a position protruding from the electrode connection portion, and the electrode connection portion of the substrate and the connection portion of the semiconductor chip. The substrate and the semiconductor chip are brought into contact with each other, and the substrate and the semiconductor chip are electrically connected in a state of direct contact between the substrate and the electrode connection portion of the semiconductor chip by a contraction force caused by curing of the insulating adhesive. Bonding the semiconductor chip onto the substrate by curing the insulating adhesive after pressurizing, and a bonding step of bonding the semiconductor chip to the substrate. 2. 2. The substrate according to claim 1, wherein the substrate is formed by forming a bump on an electrode pad as an electrode connecting portion.
The manufacturing method of the semiconductor device described in the above. 3. 2. The method according to claim 1, wherein the semiconductor chip is formed by forming a bump as an electrode connection. 4. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a resin sealing step of performing resin coating so as to cover a periphery of the semiconductor chip after the fixing step. 5. When mounting a semiconductor chip made of a semiconductor integrated circuit element or the like on a substrate provided with a wiring pattern, a coating step of applying a curable insulating adhesive to a predetermined position on the substrate except for an electrode connection portion; The semiconductor chip is placed at a predetermined position on a substrate, and the insulating adhesive is extruded from the predetermined position to a position protruding from the electrode connection portion by pressing, and the electrode connection portion of the substrate and the semiconductor A temporary bonding step in which the connecting portions of the chips are brought into contact with each other and temporarily bonded, and the insulating adhesive is cured while being contracted, so that the electrode connecting portions of the substrate and the connecting portions of the semiconductor chip are pressed. And a fixing step of fixing the semiconductor chip on the substrate with the insulating adhesive between the substrate and the semiconductor chip surface around the substrate. 6. The fixing step is a step in which the semiconductor chip is fixed on the substrate so that a gap formed between the substrate and the surface of the semiconductor chip mounted thereon is completely filled. 6. The method for manufacturing a semiconductor device according to claim 5, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8306461A JP2812316B2 (en) | 1996-11-18 | 1996-11-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8306461A JP2812316B2 (en) | 1996-11-18 | 1996-11-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09306951A JPH09306951A (en) | 1997-11-28 |
| JP2812316B2 true JP2812316B2 (en) | 1998-10-22 |
Family
ID=17957296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8306461A Expired - Lifetime JP2812316B2 (en) | 1996-11-18 | 1996-11-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2812316B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000019516A1 (en) | 1998-09-30 | 2000-04-06 | Seiko Epson Corporation | Semiconductor device, connection method for semiconductor chip, circuit board and electronic apparatus |
| US6796481B2 (en) | 2000-01-14 | 2004-09-28 | Toray Engineering Co., Ltd. | Chip mounting method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1996
- 1996-11-18 JP JP8306461A patent/JP2812316B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09306951A (en) | 1997-11-28 |
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