JPH04119644A - Mounting of semicondctor element - Google Patents

Mounting of semicondctor element

Info

Publication number
JPH04119644A
JPH04119644A JP2240284A JP24028490A JPH04119644A JP H04119644 A JPH04119644 A JP H04119644A JP 2240284 A JP2240284 A JP 2240284A JP 24028490 A JP24028490 A JP 24028490A JP H04119644 A JPH04119644 A JP H04119644A
Authority
JP
Japan
Prior art keywords
connection
chip
semiconductor element
transfer body
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2240284A
Other languages
Japanese (ja)
Inventor
Toshio Ofusa
俊雄 大房
Hidekatsu Sekine
秀克 関根
Sotaro Toki
土岐　荘太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2240284A priority Critical patent/JPH04119644A/en
Publication of JPH04119644A publication Critical patent/JPH04119644A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the processes ranging from an IC chip to a mounting substrate, to make possible an increase in the uniformity of the processes for connecting many electrodes at once and to improve the reliability of connection by a method wherein conductors for connection use are formed on a filmlike transfer material base having flexibility and these conductors for connection use are pressed and heated and are connected. CONSTITUTION:An IC chip 1 is fixed on a mounting substrate 4 via a heat dissipation layer 6. Bumps 5 for connection use respectively exist on each electrode on the chip 1, bumps 5 respectively exist also on each end part of a wiring layer 3 on the substrate 4 and connection terminals are formed on the substrate 4. A transfer material base 7 and conductors 2 for connection use are faced downward over the chip and the connection terminals, are made to oppose to the chip 1 and the connection terminals to set the position of a transfer material, a press body 8, which is provided with a built-in heating heater and can be subjected to temperature control, is made to descend and a heating and pressing process is performed. Whereupon, the bumps 5 are melted with heat, are jointed with the conductors 2 for connection use and at the same time, the conductors 2 are peeled from the base 7. The electrodes on the chip 1 and the connection terminals on the substrate 4 are electrically connected to each other through the conductors 2 for connection use.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路（以下単にＩＣという）等の半導体
素子を、プリント配線板等の搭載基板に接続する実装方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting method for connecting a semiconductor element such as an integrated circuit (hereinafter simply referred to as IC) to a mounting substrate such as a printed wiring board.

〔従来技術〕[Prior art]

従来、半導体素子を実装するには、半導体装置から延ば
したリードをプリント配線板等の搭載基板表面に設けた
バンド上に精度良く置き、位置ずれしないように半導体
素子を接着剤等で仮固定しバンド上に予め印刷しておい
た接続用のはんだを加熱・溶融させ、冷却する事によっ
て電気的に接続させていた。そのため、実装時に半導体
素子に必要以上の熱をかけることが多かった。また、接
続のための工程が煩雑で、その全てを安定して行うこと
は難しかった。Conventionally, in order to mount a semiconductor element, the leads extending from the semiconductor device are precisely placed on a band provided on the surface of a mounting board such as a printed wiring board, and the semiconductor element is temporarily fixed with adhesive to prevent it from shifting. Electrical connections were made by heating and melting the connecting solder printed on the band in advance and cooling it. Therefore, more heat than necessary is often applied to semiconductor elements during mounting. In addition, the connection process was complicated, and it was difficult to perform all of the processes stably.

また、半導体素子としてベアチップ（フリップチップ）
を使用した場合は、基板と半導体素子との熱膨張率に差
があり、このため発生するストレスを解放することがで
きないので、接続部の割れが発生しやすく、半導体素子
の接続信頼性が十分でなかった。Also, bare chips (flip chips) are used as semiconductor devices.
When using , there is a difference in the coefficient of thermal expansion between the substrate and the semiconductor element, and the stress that occurs due to this cannot be released, so cracks are likely to occur at the connection part, and the connection reliability of the semiconductor element is not sufficient. It wasn't.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記の如（、半導体チップから接続用の導体を引き出す
場合、従来法では先ず、ワイヤーボンディングによりリ
ードフレームのインナーリードに接続させ、さらに、リ
ードフレームのアウターリードから搭載基板上のバンド
に接続するので、全体の接続回数が多くなり、そのため
の全ての工程を安定して行うことは難しく、信較性の低
下を招きやすかった。As mentioned above (when drawing out a conductor for connection from a semiconductor chip, in the conventional method, it is first connected to the inner lead of the lead frame by wire bonding, and then the outer lead of the lead frame is connected to the band on the mounting board. , the total number of connections increases, and it is difficult to perform all the processes stably, which tends to lead to a decrease in reliability.

また、上記以外の従来の実装方法として、半導体素子に
フリップチップを使用して、直接、基板に搭載するもの
があるが、チップと搭載基板とが半田ハンプを介しただ
けで接続されているため、チップと基板との熱膨張率の
違いから生ずるストレスを解放できず、接続部の割れが
発生しやすいので接続信頼性は十分でなかった。In addition, as a conventional mounting method other than the above, there is a method in which the semiconductor element is mounted directly on the board using a flip chip, but the chip and the mounting board are connected only through solder humps. However, the stress caused by the difference in coefficient of thermal expansion between the chip and the substrate could not be relieved, and the connection was likely to crack, resulting in insufficient connection reliability.

〔課題を解決するための手段］ すなわち、本発明は、半導体素子上に形成した電極から
外部に接続用導体を引き出し、予めプリント配線板等の
搭載基板表面に形成しておいた接続端子へ電気的に接続
させる半導体素子の実装方法であって、常温あるいは加
熱下において可撓性を有し、かつ表面剥離性のあるフィ
ルムもしくは板状物を転写体ベースとし、その上に、導
電層を印刷法により接続用導体を形成して転写体となし
、該転写体を接続位置に配置して、加圧・加熱すること
によって、前記接続用導体を転写体ベースがら転写させ
て、半導体素子上に形成した！極とプリント配線板等の
搭載基板表面に形成しておいた接続端子とを電気的に接
続することを特徴とする半導体素子の実装方法である。[Means for Solving the Problems] That is, the present invention draws out a connecting conductor from an electrode formed on a semiconductor element to the outside, and supplies electricity to a connecting terminal formed in advance on the surface of a mounting board such as a printed wiring board. A method for mounting semiconductor elements that connects electrically, using a film or plate-like material that is flexible at room temperature or under heating and whose surface is peelable as a transfer body, and printing a conductive layer on it. A connecting conductor is formed by a method to form a transfer body, and the transfer body is placed at a connection position, and by applying pressure and heating, the connecting conductor is transferred from the transfer body base and onto a semiconductor element. Formed! This is a semiconductor device mounting method characterized by electrically connecting poles and connection terminals formed on the surface of a mounting substrate such as a printed wiring board.

また、本発明においては、接続用導体が、印刷法Ｉｔえ
て、真空蒸着、スパッタリング、イオンプレーティング
、めっき法から選択されたすくなくとも一種の手段によ
り形成されたものであっても良い。Further, in the present invention, the connecting conductor may be formed by at least one method selected from vacuum deposition, sputtering, ion plating, and plating in addition to the printing method.

さらに、本発明にあっては、転写体の接続用導体を転写
するとともに、転写体ベースを加熱・溶融させた後、冷
却・硬化させて、半導体素子及び接続用導体の保護膜と
することも、実施態様に含まれる。Furthermore, in the present invention, in addition to transferring the connection conductor of the transfer body, the base of the transfer body may be heated and melted, and then cooled and hardened to form a protective film for the semiconductor element and the connection conductor. , included in the embodiments.

なお、転写体ベースの材質は、樹脂を用いるのが実際的
であるが、樹脂のほかに、金属箔、常温あるいは加熱下
で可撓性を有する金属板、もしくは半導体材料であって
も、実施可能な範囲で、その使用を妨げるものではない
。また、上記の材Ｒを複数用い、例えば積層体にしても
良い。Note that it is practical to use resin as the material for the base of the transfer body, but in addition to resin, metal foil, a metal plate that is flexible at room temperature or under heat, or a semiconductor material may also be used. This does not preclude its use to the extent possible. Further, a plurality of the above-mentioned materials R may be used, for example, to form a laminate.

上記のような本発明では、半導体素子と搭載基板との電
気的かつ物理的な接続を一度で行うことによって接続信
頼性の向上を図った。また、転写体ベース上に接続用導
体を形成し、これを転写することによって同時に全ての
電極を接続するという、半導体素子の実装方法である。In the present invention as described above, connection reliability is improved by electrically and physically connecting the semiconductor element and the mounting substrate at one time. Furthermore, this is a semiconductor element mounting method in which a connecting conductor is formed on a transfer body base and all electrodes are connected at the same time by transferring the connecting conductor.

このとき使用する半導体素子は、ｔＣ等のパッケージ、
ベアチップ等形態及び搭載する向きは問わない、また、
半導体素子と基板との接続を一度で行っても良いし、半
導体素子との接続と、基板との接続を別々に行ってもよ
い。The semiconductor element used at this time is a package such as tC,
The form and mounting direction of bare chips etc. do not matter, and
The semiconductor element and the substrate may be connected at once, or the semiconductor element and the substrate may be connected separately.

Ｃ作用〕 本発明では、可撓性を有するフィルム状の転写体ベース
に接続用導体を形成し、これを加圧・加熱することによ
って接続するため、多くの電極を一度に接続できる。さ
らに、接続用導体に可撓性があるため、熱膨張率の差な
どによって生ずるストレスを緩和でき、接続信頼性が向
上した。C Effect] In the present invention, a connecting conductor is formed on a flexible film-like transfer body base, and the connection is made by applying pressure and heating, so that many electrodes can be connected at once. Furthermore, since the connecting conductor is flexible, stress caused by differences in thermal expansion coefficients can be alleviated, improving connection reliability.

〔発明の詳述〕[Detailed description of the invention]

以下に図面に基いて本発明の詳細な説明する。 The present invention will be described in detail below based on the drawings.

第１図（ａ）において、ＩＣチップ（１）は、放熱層（
６）を介してプリント基板等の搭載基板（４）の上に固
定されている。放熱層（６）は良熱伝導体からなってい
る。ＩＣチップ（１）の電極には、接続用のバンブ（５
）が形成されており、同様にバンブ（５）は、搭載基板
（４）の配線層（３）の端部にも形成されて、接続端子
を形造っている。上方に、転写体ベース（７）と接続用
導体（２）とからなる転写体が、接続用導体（２）を下
向きにして、かつＩＣチップ（１）および接続端子と対
向するように位置設定されている。なお、その上方に加
熱・加圧用のプレス体（８）が設置されている。In FIG. 1(a), the IC chip (1) has a heat dissipation layer (
6) onto a mounting board (4) such as a printed circuit board. The heat dissipation layer (6) is made of a good heat conductor. The electrode of the IC chip (1) has a connection bump (5
) are formed, and similarly bumps (5) are also formed at the ends of the wiring layer (3) of the mounting board (4) to form connection terminals. The transfer body consisting of the transfer body base (7) and the connection conductor (2) is positioned above so that the connection conductor (2) faces downward and faces the IC chip (1) and the connection terminal. has been done. Note that a press body (8) for heating and pressurizing is installed above it.

プレス体（８）は、図示されていないが、電熱ヒーター
を内蔵し、温度制御を可能とする。また、その表面はシ
リコーンゴム等の弾性体で構成されるものである。Although not shown, the press body (8) has a built-in electric heater to enable temperature control. Further, its surface is made of an elastic material such as silicone rubber.

第１図（ｂ）に示すように、プレス体（８）を下降させ
、加熱・加圧する工程を行う。この時点で、ハンプ（５
）は、熱により若干溶融し、接続用導体（２）と接合す
るとともに、接続用導体（２）が転写体ベース（７）か
ら剥離する。As shown in FIG. 1(b), the press body (8) is lowered and a process of heating and pressurizing is performed. At this point, the hump (5
) is slightly melted by heat and joined to the connecting conductor (2), and the connecting conductor (2) is peeled off from the transfer body base (7).

第１図（Ｃ）に示すように、プレス体（８）を上昇させ
れば、ＩＣチップ（１）の電極と搭載基板（４）の接続
端子とが、接続用導体（２）により電気的に接続されて
いるものである。As shown in FIG. 1(C), when the press body (8) is raised, the electrodes of the IC chip (1) and the connection terminals of the mounting board (4) are connected electrically by the connection conductor (2). is connected to.

第１図の実施例では、転写体の転写ベース（７）は分離
されて、ＩＣチップ（１）を実装された搭載基板（４）
には関与していない。しかし、その他の実施例として、
転写体の接続用導体（２）を転写するとともに、転写体
ベース（７）を加熱・溶融させた後、冷却・硬化させて
、ＩＣチップ（１）および接続用導体（２）の絶縁性保
護膜とすることもできる。In the embodiment shown in FIG. 1, the transfer base (7) of the transfer body is separated and the mounting board (4) on which the IC chip (1) is mounted is attached.
is not involved. However, in other embodiments,
While transferring the connection conductor (2) of the transfer body, the transfer body base (7) is heated and melted, and then cooled and hardened to provide insulation protection for the IC chip (1) and the connection conductor (2). It can also be a membrane.

第２図は、本発明の他の実施例を示す。図示するように
、ＩＣチップ（１）を樹脂成形体（９）の凹部に固定し
、該樹脂成形体（９）の上面に印刷等の手段によりイン
ナーリードに相当する導電層０ωを形成する。その後、
ＩＣチップ（１）と導電層ＧＯ）を電気的に接続するワ
イヤーＯＤを用いてポンディングし、絶縁性樹脂を施し
てＩＣチップ（１）を封止して半導体素子とする。FIG. 2 shows another embodiment of the invention. As shown in the figure, an IC chip (1) is fixed in a recessed part of a resin molded body (9), and a conductive layer 0ω corresponding to an inner lead is formed on the upper surface of the resin molded body (9) by means such as printing. after that,
The IC chip (1) and the conductive layer GO) are bonded using a wire OD that electrically connects them, and an insulating resin is applied to seal the IC chip (1) to form a semiconductor element.

この状態で、本発明を通用することもできる。The present invention can also be applied in this state.

すなわち半導体素子を搭載基板（４）の上に固定し、上
方に、転写体ベース（７）と接続用導体（２）とからな
る転写体を、接続用導体（２）を下向きにして、対向設
置する。プレス体（８）を下降させ、加熱・加圧する工
程を行うのは、第１図と同様である。That is, a semiconductor element is fixed on a mounting substrate (4), and a transfer body consisting of a transfer body base (7) and a connecting conductor (2) is placed above, and the connecting conductor (2) is facing downward. Install. The process of lowering the press body (8) and heating and pressurizing it is the same as in FIG. 1.

〔実施例１〕 転写体ベースとして、厚みが５０μ−のフン素樹脂フィ
ルム（ＰＦＡフィルム）を用い、接続用導体パターンを
スクリーン印刷で形成した。このとき、接続用導体は銅
ペーストをインキに使用した。１２０℃で３０分間加熱
し、印刷した銅ペーストを硬化させ接続用導体とした０
次いで、半導体素子を接続する部分とプリント配線板上
のパッドを接続する部分にバンブを印刷形成した。ハン
プには銅ペーストを厚盛りして形成した。[Example 1] A fluorine resin film (PFA film) having a thickness of 50 μm was used as a transfer body base, and a conductor pattern for connection was formed by screen printing. At this time, copper paste was used as ink for the connecting conductor. Heated at 120°C for 30 minutes to harden the printed copper paste and use it as a connecting conductor.
Next, bumps were printed and formed on the parts where the semiconductor elements were to be connected and the parts where the pads on the printed wiring board were to be connected. The hump was formed by applying a thick layer of copper paste.

プリント配線板のチップ搭載部は、あらかじめチップの
高さに相当する深さの溝を設けておき、溝の底部に接着
剤を塗布した。そして、ＩＣチップ（ヘアチップ）を、
電極面が上になるように溝に差し込み、接着剤を硬化さ
せ、チップが動かないようにした。In the chip mounting area of the printed wiring board, a groove with a depth corresponding to the height of the chip was prepared in advance, and an adhesive was applied to the bottom of the groove. Then, the IC chip (hair chip)
The chip was inserted into the groove with the electrode side facing up, and the adhesive was cured to prevent the chip from moving.

ＰＦＡフィルムの接続用導体印刷面を下にして、プリン
ト配線板のチップ搭載部の周囲に設けたパッドとＩＣチ
ップ上の電極がきちんと接続するように位置合わせし、
フィルムの裏面（上側）から軽く押さえ、１３０　’Ｃ
で３０分間加熱・加圧し、印刷したハンプを硬化させる
ことによって、接続用導体を通して、ＩＣチップとプリ
ント配線板上の配線とを接続させた。そして、転写体ベ
ースとして用いたＰＦＡフィルムを剥離した。With the connection conductor printed side of the PFA film facing down, align it so that the pads provided around the chip mounting area of the printed wiring board and the electrodes on the IC chip are properly connected.
Lightly press the film from the back (top) and heat it to 130'C.
By heating and pressurizing the printed wiring board for 30 minutes to harden the printed hump, the IC chip and the wiring on the printed wiring board were connected through the connecting conductor. Then, the PFA film used as the transfer body base was peeled off.

〔実施例２〕 転写体ベースとして、厚みが約１００μ−のポリイミド
フィルム　（商品名；ユーピレックス）を用い、接続用
導体を形成する部分にめっき用触媒（パラジウム）を印
刷し、接続用導体を無電解ニッケルめっきで形成した。[Example 2] A polyimide film (trade name: Upilex) with a thickness of about 100μ was used as the transfer body base, and a plating catalyst (palladium) was printed on the part where the connecting conductor was to be formed, so that the connecting conductor was not formed. Formed by electrolytic nickel plating.

プリント配線板上に設けたパッドには予め、はんだペー
ストを印刷した。Solder paste was printed in advance on the pads provided on the printed wiring board.

そして、ＩＣチップ（フリップチップ）を載せる部分に
接着剤を塗布し、電極面を上側にし、目的の位置に正確
にＩＣチップを置き、接着剤を硬化させ、チップが動か
ないように固定した。Adhesive was then applied to the area on which the IC chip (flip chip) would be placed, the electrode surface facing up, the IC chip was placed exactly at the desired position, the adhesive was cured, and the chip was fixed so that it would not move.

ポリイミドフィルム上の接続用導体形成面を下にして、
プリント配ｍｉのチップ搭載部の周囲に設けたバンドと
ＩＣチップ上の電極がきちんと接続するように位置合わ
せし、フィルムの裏面（上側）から軽く押さえ、はんだ
ペースト印刷部分を２００℃で４５秒間加熱し、印刷し
たバンプを溶融後、冷却・硬化させて形成した接続用導
体を通して、ＩＣチップの電極とプリント配線板上の配
線層とを接続させた。With the connection conductor forming side on the polyimide film facing down,
Align the band around the chip mounting part of the printed wiring board so that it connects properly with the electrodes on the IC chip, press lightly from the back (top) of the film, and heat the solder paste printed area at 200°C for 45 seconds. Then, the electrodes of the IC chip and the wiring layer on the printed wiring board were connected through a connecting conductor formed by melting, cooling and hardening the printed bumps.

〔発明の効果〕〔Effect of the invention〕

本発明では、可撓性を有するフィルム状の転写体ベース
に接続用導体を形成し、これを加圧・加熱することによ
って接続するため、ＩＣチップから搭載基板への接続に
必要な工程が簡素化されるまた、多くの電極を一度に接
続するため、端子数の多少に関わらず同一時間で接続で
き、工程の均一化が図れる。特に、半導体素子の端子数
が多い場合には、接続に要する時間が端子数に伴って増
加しないので、半導体素子の端子数が多いほど効果が大
きい。In the present invention, a connecting conductor is formed on a flexible film-like transfer body base, and the connection is made by applying pressure and heating, which simplifies the process required to connect an IC chip to a mounting board. In addition, since many electrodes are connected at once, connections can be made in the same time regardless of the number of terminals, making the process uniform. In particular, when the number of terminals on the semiconductor element is large, the time required for connection does not increase with the number of terminals, so the effect is greater as the number of terminals on the semiconductor element increases.

さらに、接続用導体に可撓性があるため、熱膨張率の差
などによって生ずるストレスを緩和でき、接続信鯨性が
向上した。Furthermore, since the connection conductor is flexible, stress caused by differences in thermal expansion coefficients can be alleviated, improving connection reliability.

また、搭載基板の半導体素子搭載部に放熱用回路を形成
すれば、半導体素子の動作時に発生する熱を効率良く発
散させることが可能である。Further, by forming a heat dissipation circuit in the semiconductor element mounting portion of the mounting substrate, it is possible to efficiently dissipate heat generated during operation of the semiconductor element.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（Ｃ）は、本発明の半導体素子の実装方
法の一実施例を工程順に示す説明図であり、第２図は、
本発明の半導体素子の実装方法の他の実施例の主要工程
を示す説明図である。 （１）　−Ｉ　Ｃチップ　　　（２）−・−接続用導体
（３）−一−−配線層　　　　　（４）−・−搭載基板
（５１−−−一−バンブ　　　　　（６）　−放熱用回
路１図（ａ） 第１図（ｂ） 第１図（Ｃ） 第２図FIGS. 1(a) to (C) are explanatory diagrams showing one embodiment of the semiconductor element mounting method of the present invention in the order of steps, and FIG.
FIG. 6 is an explanatory diagram showing the main steps of another embodiment of the semiconductor device mounting method of the present invention. (1) -I C chip (2)--Connecting conductor (3)--Wiring layer (4)--Mounting board (51--1-bump) (6)--Heat dissipation circuit 1 diagram (a) Figure 1 (b) Figure 1 (C) Figure 2

Claims (4)

【特許請求の範囲】[Claims] （１）半導体素子上に形成した電極から外部に接続用導
体を引き出し、予めプリント配線板等の搭載基板表面に
形成しておいた接続端子へ電気的に接続させる半導体素
子の実装方法において、常温あるいは加熱下において可
撓性を有し、かつ表面剥離性のあるフィルムもしくは板
状物を転写体ベースとし、その上に、導電層を印刷法に
より接続用導体を形成して転写体となし、該転写体を接
続位置に配置して、加圧・加熱することによって、前記
接続用導体を転写体ベースから転写させて、半導体素子
上に形成した電極とプリント配線板等の搭載基板表面に
形成しておいた接続端子とを電気的に接続することを特
徴とする半導体素子の実装方法。(1) In a semiconductor element mounting method in which a connecting conductor is drawn out from an electrode formed on a semiconductor element and electrically connected to a connecting terminal formed in advance on the surface of a mounting board such as a printed wiring board, the semiconductor element is mounted at room temperature. Alternatively, a transfer body is formed by using a film or a plate-like material that is flexible under heating and has a surface peeling property as a transfer body, and forming a connecting conductor thereon by printing a conductive layer thereon to form a transfer body; By placing the transfer body at a connection position and applying pressure and heat, the connection conductor is transferred from the transfer body base and formed on the electrode formed on the semiconductor element and the surface of a mounting substrate such as a printed wiring board. 1. A method for mounting a semiconductor device, comprising electrically connecting connection terminals that have been previously connected. （２）接続用導体が、印刷法に代えて、真空蒸着、スパ
ッタリング、イオンプレーティング、めっき法から選択
されたすくなくとも一種の手段により形成されたもので
ある請求項（１）記載の半導体素子の実装方法。(2) The semiconductor device according to claim 1, wherein the connecting conductor is formed by at least one method selected from vacuum evaporation, sputtering, ion plating, and plating instead of the printing method. How to implement. （３）転写体の接続用導体を転写するとともに、転写体
ベースを加熱・溶融させた後、冷却・硬化させて、半導
体素子及び接続用導体の保護膜とすることを特徴とする
請求項（１）記載の半導体素子の実装方法。(3) A claim characterized in that the connection conductor of the transfer body is transferred, and the base of the transfer body is heated and melted, and then cooled and hardened to form a protective film for the semiconductor element and the connection conductor. 1) Method for mounting the semiconductor element described above. （４）転写体ベースの材質が、樹脂、金属箔、もしくは
常温あるいは加熱下で可撓性を有する金属板、または、
半導体材料であることを特徴とする請求項（１）または
（３）記載の半導体素子の実装方法。(4) The material of the transfer body base is resin, metal foil, or a metal plate that is flexible at room temperature or under heating, or
4. The method for mounting a semiconductor element according to claim 1, wherein the semiconductor element is a semiconductor material.
JP2240284A 1990-09-11 1990-09-11 Mounting of semicondctor element Pending JPH04119644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2240284A JPH04119644A (en) 1990-09-11 1990-09-11 Mounting of semicondctor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2240284A JPH04119644A (en) 1990-09-11 1990-09-11 Mounting of semicondctor element

Publications (1)

Publication Number Publication Date
JPH04119644A true JPH04119644A (en) 1992-04-21

Family

ID=17057196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2240284A Pending JPH04119644A (en) 1990-09-11 1990-09-11 Mounting of semicondctor element

Country Status (1)

Country Link
JP (1) JPH04119644A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194414A (en) * 2006-01-19 2007-08-02 Fuji Xerox Co Ltd Wiring method and donor substrate
JP2011119438A (en) * 2009-12-03 2011-06-16 Fuji Electric Systems Co Ltd Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194414A (en) * 2006-01-19 2007-08-02 Fuji Xerox Co Ltd Wiring method and donor substrate
JP2011119438A (en) * 2009-12-03 2011-06-16 Fuji Electric Systems Co Ltd Method for manufacturing semiconductor device

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