JP2800884B2 - Semiconductor device having lateral DSA power MOSFET - Google Patents

Semiconductor device having lateral DSA power MOSFET

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Publication number
JP2800884B2
JP2800884B2 JP7280085A JP28008595A JP2800884B2 JP 2800884 B2 JP2800884 B2 JP 2800884B2 JP 7280085 A JP7280085 A JP 7280085A JP 28008595 A JP28008595 A JP 28008595A JP 2800884 B2 JP2800884 B2 JP 2800884B2
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JP
Japan
Prior art keywords
layer
source
contact hole
substrate
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7280085A
Other languages
Japanese (ja)
Other versions
JPH09129867A (en
Inventor
幸雄 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7280085A priority Critical patent/JP2800884B2/en
Publication of JPH09129867A publication Critical patent/JPH09129867A/en
Application granted granted Critical
Publication of JP2800884B2 publication Critical patent/JP2800884B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は，半導体装置に関
し，特に，横型ＤＳＡ（２重拡散自己整合方式）パワー
ＭＯＳＦＥＴ（絶縁ゲート電界効果トランジスタ）のユ
ニットセル構造に関する。The present invention relates to a semiconductor device, and more particularly to a unit cell structure of a lateral DSA (double diffusion self-alignment type) power MOSFET (insulated gate field effect transistor).

【０００２】[0002]

【従来の技術】横型ＤＳＡパワーＭＯＳＦＥＴは，半導
体基板の表面に絶縁ゲートをマスクとして不純物の２重
拡散により自己整合的にチャネル長を規定するものであ
り，図５の平面図と図６による図５のII−II' 線に沿う
断面図の夫々に示すように，ゲート電極２３を従来から
あるメッシュ状に配置したものと，特開平２−３６５７
２号公報（以下，従来例１と呼ぶ）に開示された変形ス
トライプ状に配置されたものとがある。従来例１に示さ
れた変形ストライプ配置のＭＯＳＦＥＴは，図７の平面
図と図８による図７のIV−IV' 線に沿う断面図に示すよ
うに，ソースコンタクト及びドレインコンタクトを規定
する縦横方向に所定間隔に配置された正方形のソース及
びドレインコンタクトホール２５及び２７を交互に囲む
ように変形されたストライプ状ゲートを形成し，これら
が矩形波状に配置されているレイアウトを有する。この
ような変形ストライプ状配置の絶縁ゲートを有するＭＯ
ＳＦＥＴは，従来のメッシュ状配置のそれに比べて単位
面積当りのゲート幅を長く形成することができ，それだ
けオン抵抗が小さくしたがって損失も小さくＭＯＳＦＥ
Ｔとしての効率がよい。2. Description of the Related Art A lateral DSA power MOSFET defines a channel length in a self-aligned manner by double diffusion of impurities on the surface of a semiconductor substrate using an insulating gate as a mask. As shown in the cross-sectional views taken along the line II-II ′ of FIG.
Japanese Patent Application Laid-Open No. 2 (hereinafter referred to as Conventional Example 1) discloses an arrangement arranged in a deformed stripe shape. As shown in the plan view of FIG. 7 and the cross-sectional view taken along the line IV-IV ′ of FIG. 8 in FIG. Are formed so as to alternately surround square source and drain contact holes 25 and 27 arranged at predetermined intervals, and have a layout in which these are arranged in a rectangular wave shape. An MO having such a modified striped arrangement of insulated gates
The SFET can be formed with a longer gate width per unit area than that of the conventional mesh arrangement, and accordingly, the ON resistance is small and the loss is small, so
The efficiency as T is good.

【０００３】[0003]

【発明が解決しようとする課題】この従来の変形ストラ
イプ状ゲート電極のパワーＭＯＳＦＥＴでは等ピッチで
規則的にソースコンタクトを配置し，その対角線交差点
上にドレインコンタクトを配置した構造で，ドレインコ
ンタクトがソースコンタクトと同一形状の正方形パター
ンのため各ソースコンタクト間距離を縮少することがで
きず単位面積に占めるゲート幅の割合が充分に大きいと
は言えない。また，変形ストライプ状ゲート電極は矩形
波状に形成されるためセル面積の大きなパワーＭＯＳＦ
ＥＴではゲート抵抗の影響を受け，各ユニットセルの均
一な動作が難しい。これらのことにより，上記構造のパ
ワーＭＯＳＦＥＴではオン抵抗が低減できないという問
題があった。In this conventional power MOSFET having a modified striped gate electrode, a source contact is regularly arranged at an equal pitch, and a drain contact is arranged on a diagonal intersection thereof. Since the square pattern has the same shape as the contacts, the distance between the source contacts cannot be reduced, and the ratio of the gate width to the unit area cannot be said to be sufficiently large. Further, since the deformed striped gate electrode is formed in a rectangular wave shape, a power MOSF having a large cell area is formed.
In ET, uniform operation of each unit cell is difficult due to the influence of gate resistance. For these reasons, there is a problem that the on-resistance cannot be reduced in the power MOSFET having the above structure.

【０００４】そこで，本発明の技術的課題は，ゲート抵
抗を低減しソースコンタクト間距離を縮少したことによ
るオン抵抗の低減の効果を最大限に発揮する構造を有し
た横型ＤＳＡパワーＭＯＳＦＥＴを備えた半導体装置を
提供することにある。It is an object of the present invention to provide a lateral DSA power MOSFET having a structure that maximizes the effect of reducing the on-resistance by reducing the gate resistance and reducing the distance between the source contacts. To provide a semiconductor device.

【０００５】[0005]

【課題を解決するための手段】上記技術的課題を解決す
るために，本発明の横型ＤＳＡパワーＭＯＳＦＥＴを備
えた半導体装置では，第１導電型Ｓｉ基板と，該Ｓｉ基
板上に形成された複数の八角形のチャンネル領域であり
このチャンネル領域同士が等ピッチ間隔で互いに縦横に
直交する方向に形成される第２導電型ベース層と，隣接
する４個の前記ベース層からなる正方形の中心位置に形
成され，前記４個の前記ベース層の前記八角形の短辺の
内の前記中心位置に一番近い短辺に夫々対向するように
４辺を持つ菱形状の第１導電型ドレイン層と，このドレ
イン層の中心上の絶縁膜中に形成され，前記ベース層か
らなる正方形の対角線に沿う四辺を備えた正方形を含む
菱形状に形成されるドレインコンタクトホールと，前記
Ｓｉ基板上の前記ベース層と前記ドレイン層との間にあ
るフィールド酸化膜と，前記ベース層内に八角形の枠状
に形成された第１導電型ソース層と，このソース層の中
心上の前記絶縁膜に形成されたソースコンタクトホール
と，前記ソース層の外側と前記フィールド酸化膜との間
に前記ベース層の絶縁部と前記フィールド酸化膜の一部
を覆って形成されたゲート酸化膜と，前記ソース層の縁
を前記ゲート酸化膜を介して八角形の枠状に覆い，前記
ソースコンタクトホールとドレインコンタクトホールと
を前記絶縁膜を挟んで囲む曲折したメッシュ状に形成さ
れているゲート電極とを備えていることを特徴としてい
る。In order to solve the above technical problem, a lateral DSA power MOSFET according to the present invention is provided.
In the obtained semiconductor device, the first conductivity type Si substrate and the Si-based
A plurality of octagonal channel regions formed on a plate
These channel regions are vertically and horizontally aligned at equal pitch intervals.
A second conductivity type base layer formed in a direction orthogonal to
At the center of the square consisting of the four base layers
And the short sides of the octagon of the four base layers
So as to face the short sides closest to the center position in
A first-conductivity-type drain layer having a rhombus shape having four sides;
Formed in the insulating film on the center of the
Includes squares with four sides along the diagonal of the square
A drain contact hole formed in a diamond shape;
A gap is formed between the base layer and the drain layer on the Si substrate.
Field oxide film and an octagonal frame in the base layer
A first conductivity type source layer formed in
A source contact hole formed in the insulating film above the core
Between the outside of the source layer and the field oxide film
The insulating portion of the base layer and part of the field oxide film
A gate oxide film formed so as to cover the edge of the source layer;
Is covered in an octagonal frame shape through the gate oxide film,
Source contact hole and drain contact hole
Are formed in a bent mesh shape surrounding the insulating film.
And a gate electrode .

【０００６】[0006]

【発明の実施の形態】次に，本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【０００７】図１は本発明の第１の実施の形態による半
導体装置の平面図であり，図２は図１の半導体装置のVI
−VI′線に沿う断面図である。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 6 is a cross-sectional view along the line VI ′.

【０００８】図１及び図２を参照して，Ｎ型エピタキシ
ャル層又はＮ型ウェル層からなるＮ型Ｓｉ基板１１に
は，平面が角の無い正方形つまり八角形のチャンネル領
域となるＰ型ベース層１３が，等ピッチ間隔で互いに直
交する方向に形成され，隣接する４個のＰ型ベース層１
３からなる正方形の頂点位置に夫々配置されている。そ
の正方形の中心位置に，八角形のＰ型ベース層１３の領
域の内側の短辺に夫々接するように４辺を持つ菱形のＮ
+ 型ドレイン層１５が，フィールド酸化膜１７を介して
形成されている。Ｐ型ベース層１３には，Ｎ+ 型ソース
層１９が角の無い四角の枠状に形成されている。Ｐ型ベ
ース層１３の縁部とフィールド酸化膜１７の一部を覆っ
て，Ｎ+ 型ソース層１９の外側一端とフィールド酸化膜
１７との間には，ゲート酸化膜２１が形成され，その上
にポリＳｉ等で形成されるゲート電極２３が，平面図で
は角の無い正方形つまり八角形に形成されている。ゲー
ト電極２３は，半導体基板平面でＮ+ 型ソース層１９の
中心上に形成された正方形のソースコンタクトホール２
５及びＮ+ 型ドレイン層１５の中心上に形成されたドレ
インコンタクトホール２７を囲み，曲折したメッシュ状
に形成されている。ゲート電極２３を覆いかつ，Ｐ型ベ
ース層１３の中心部で，Ｎ+ 型ソース層１９に囲まれた
部分の表面上のソースコンタクトホール２５及びＮ+ 型
ドレイン層１５の中心部の表面上のドレインコンタクト
ホール２７を残して，第１層間絶縁膜２９が設けられて
いる。尚，符号３３ａはＮ+ 型ドレイン引き出し領域を
形成するためのゲート電極開口部である。また，符号１
５ａはＮ+ 型ドレイン引き出し層である。ゲート電極開
口部３３ａは，セルフアラインでＮ+ 型ドレイン引き出
し領域１５ａを形成するために設けられている。ここ
で，フィールド酸化膜１７は，目標耐圧を得るためゲー
ト電極２３の端部の電界緩和を行う。ソースコンタクト
ホール２５及びドレインコンタクトホール２７上には，
Ｔ字状の側断面を有する第１金属電極３１が夫々設けら
れている。これら第１金属電極３１は，ドレインコンタ
クトホール２７上の第１金属部分上を残して，第２層間
絶縁膜３３が形成され，さらにその上に第２金属電極３
５が設けられている。第１金属電極３１と第２金属電極
３５とは，Ｎ+ 型ドレイン層１５上に位置するコンタク
トホール３７を介して電気的に接続されている。Referring to FIGS. 1 and 2, an N-type Si substrate 11 composed of an N-type epitaxial layer or an N-type well layer is provided with a P-type base layer having a square with no corners, that is, an octagonal channel region. 13 are formed in the directions orthogonal to each other at equal pitch intervals, and four adjacent P-type base layers 1 are formed.
3 are arranged at the vertices of a square. At the center position of the square, a diamond-shaped N having four sides so as to be in contact with the short sides inside the region of the octagonal P-type base layer 13 respectively.
The + type drain layer 15 is formed via the field oxide film 17. In the P-type base layer 13, an N + -type source layer 19 is formed in a square frame shape without corners. A gate oxide film 21 is formed between an outer end of the N + type source layer 19 and the field oxide film 17 so as to cover an edge of the P-type base layer 13 and a part of the field oxide film 17. A gate electrode 23 made of poly-Si or the like is formed in a square having no corners, that is, an octagon in a plan view. The gate electrode 23 is a square source contact hole 2 formed on the center of the N + type source layer 19 on the semiconductor substrate plane.
5 and the drain contact hole 27 formed on the center of the N + type drain layer 15 is formed in a bent mesh shape. The source contact hole 25 on the surface of the portion surrounded by the N + -type source layer 19 at the center of the P-type base layer 13 and on the surface of the center of the N + -type drain layer 15 at the center of the P-type base layer 13. A first interlayer insulating film 29 is provided except for the drain contact hole 27. Reference numeral 33a denotes a gate electrode opening for forming an N + type drain lead region. In addition, code 1
5a is an N + -type drain lead-out layer. The gate electrode opening 33a is provided for forming the N + -type drain lead-out region 15a by self-alignment. Here, the field oxide film 17 reduces the electric field at the end of the gate electrode 23 to obtain the target breakdown voltage. On the source contact hole 25 and the drain contact hole 27,
First metal electrodes 31 each having a T-shaped side cross section are provided. These first metal electrodes 31 are provided with a second interlayer insulating film 33 except for the first metal portions on the drain contact holes 27, and the second metal electrodes 3 are further formed thereon.
5 are provided. The first metal electrode 31 and the second metal electrode 35 are electrically connected via a contact hole 37 located on the N + type drain layer 15.

【０００９】上述した第１の実施の形態において，等ピ
ッチで規則的に配置するソースコンタクトに対して対角
線交差点上に配置するドレインコンタクトの形状が，こ
の対角線に沿う四辺を備えた正方形を含む菱形状に形成
されている。すなわち，菱形にすることで，ソースコン
タクト間距離が縮小され，オン抵抗の低減が可能とな
る。In the above-described first embodiment, the shape of the drain contact disposed on the diagonal intersection with respect to the source contact regularly disposed at the same pitch is a diamond including a square having four sides along the diagonal. It is formed in a shape. In other words, the rhombus reduces the distance between the source contacts and the on-resistance.

【００１０】また，前述したように，Ｐ型ベース層上に
形成されたゲート酸化膜２１とともに絶縁ゲートを形成
するゲート電極２３は，ソースコンタクトホール２５と
ドレインコンタクトホール２７を囲み，曲折したメッシ
ュ状を有している。そうすることで，ゲート抵抗が低減
し，各ユニットセルの均一なＭＯＳ動作が可能となる。Further, as described above, the gate electrode 23 forming an insulating gate together with the gate oxide film 21 formed on the P-type base layer surrounds the source contact hole 25 and the drain contact hole 27 and has a bent mesh shape. have. By doing so, the gate resistance is reduced, and uniform MOS operation of each unit cell becomes possible.

【００１１】Ｎ+ 型ソース層１９とＰ型ベース層１３は
ゲート電極２３をマスクに２重拡散するＤＳＡ構造であ
って自己整合的にチャネル長，閾値電圧の制御がされ
る。Ｎ+ 型ソース層１９とＮ+ 型ドレイン層１５は同一
工程で形成してもよいし別々の工程で形成してもよい。The N + -type source layer 19 and the P-type base layer 13 have a DSA structure in which the gate electrode 23 is used as a mask, and the channel length and the threshold voltage are controlled in a self-aligned manner. The N + -type source layer 19 and the N + -type drain layer 15 may be formed in the same step or in separate steps.

【００１２】また，図示はしてないがソース電極とドレ
イン電極は１層目の金属層で別々に形成してもよい。Although not shown, the source electrode and the drain electrode may be formed separately from the first metal layer.

【００１３】図３は本発明の第２の実施の形態に係る半
導体装置の平面図であり図１と等価な部分には同一符号
を付してある。また，図４は図３のVIII−VIII′線で切
断した断面図であり図２と等価な部分には，図３と同様
に同一符号を付してある。図３及び図４を参照して，ゲ
ート電極２３にはＮ+ 型ドレイン引出し層形成のための
開口部は設けられていない。平面図において八角形のゲ
ート電極に囲まれたＮ+ 型ドレイン層１５は正方形を含
む菱形の４つの角を切り落とした八角形状に形成され，
この八角形の長辺が，八角形のゲート電極領域の短辺の
外接するように形成されている。Ｎ+ 型ドレイン引出し
層１５ａの形成は，フォトレジストをマスクにしてリン
の数１００ｋｅＶ高エネルギーイオン注入を行うことで
ゲート電極２３の下のＳｉ表面に形成する。これで第１
の実施の形態と同じ効果を有するセルパターンとなる。
図４では図２と比較してＮ+ 型ドレイン層１５が高エネ
ルギーのイオン注入で形成されるため深い拡散層となっ
ている。FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention, and portions equivalent to those in FIG. 1 are denoted by the same reference numerals. FIG. 4 is a cross-sectional view taken along the line VIII-VIII 'in FIG. 3, and portions equivalent to those in FIG. 2 are denoted by the same reference numerals as in FIG. Referring to FIGS. 3 and 4, the gate electrode 23 is not provided with an opening for forming an N + -type drain extraction layer. In the plan view, the N + -type drain layer 15 surrounded by the octagonal gate electrode is formed in an octagonal shape obtained by cutting off four corners of a rhombus including a square.
The long side of the octagon is formed so as to circumscribe the short side of the octagonal gate electrode region. The N + -type drain extraction layer 15a is formed on the Si surface below the gate electrode 23 by performing high-energy ion implantation of several hundred keV of phosphorus using a photoresist as a mask. This is the first
This is a cell pattern having the same effect as that of the embodiment.
4, the N + -type drain layer 15 is a deep diffusion layer because it is formed by high-energy ion implantation as compared with FIG.

【００１４】[0014]

【発明の効果】以上説明したように，本発明では，横型
ＤＳＡパワーＭＯＳＦＥＴにおいては，ソースコンタク
ト間距離の縮少可で単位面積当たりのチャネル幅が増加
し，オン抵抗を小さくすることができる。As described above, according to the present invention, in the lateral DSA power MOSFET, the distance between the source contacts can be reduced, the channel width per unit area increases, and the on-resistance can be reduced.

【００１５】また，本発明においては，絶縁ゲートをメ
ッシュ状に形成することでユニットセルの均一なＭＯＳ
動作を可能にしオン抵抗をさらに小さくすることができ
る。In the present invention, a uniform MOS of a unit cell is formed by forming an insulating gate in a mesh shape.
The operation is enabled, and the on-resistance can be further reduced.

【００１６】また，本発明においては，互いに隣接する
４つのソースコンタクトの中心間を結ぶ線分で作られた
四角形の対角線との内の少なくとも１本に並行した２辺
を備えた四角形，例えば，ひし形形状のドレインコンタ
クトを，ソースコンタクト間の対角線と並行した辺を有
するように配置してソースコンタクト間距離を縮少した
ので，オン抵抗が低減する。Further, in the present invention, a quadrangle having two sides parallel to at least one of a quadrangular diagonal line formed by a line segment connecting the centers of four adjacent source contacts, for example, Since the diamond-shaped drain contacts are arranged so as to have sides parallel to the diagonal line between the source contacts and the distance between the source contacts is reduced, the on-resistance is reduced.

【００１７】さらに，本発明においては，絶縁ゲートが
変形メッシュ状の構造でチップ全体に連続しているの
で，特に大きなチップ面積においても，各ユニットセル
の均一なＭＯＳ動作が可能になりスイッチ等の特性にお
いて安定した特性が得られる。Further, in the present invention, since the insulating gates are continuous with the entire chip in a deformed mesh structure, uniform MOS operation of each unit cell is possible even in a particularly large chip area, and switches and the like can be used. Stable characteristics can be obtained.

【００１８】以上から本発明の横型ＤＳＡパワーＭＯＳ
ＦＥＴを備えた半導体装置は，安定したデバイス特性が
得られ，オン抵抗が３０％程度低減するという効果を有
する。As described above, the lateral DSA power MOS of the present invention
A semiconductor device having an FET has an effect that stable device characteristics are obtained and the on-resistance is reduced by about 30%.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を示すパワーＭＯＳ
ＦＥＴの一部平面図である。FIG. 1 is a power MOS showing a first embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

【図２】図１のVI−VI線で切断した断面図である。FIG. 2 is a sectional view taken along line VI-VI of FIG.

【図３】本発明の第２の実施の形態を示すパワーＭＯＳ
ＦＥＴの一部平面図である。FIG. 3 shows a power MOS showing a second embodiment of the present invention.
FIG. 3 is a partial plan view of the FET.

【図４】図３のVIII−VIII′線で切断した断面図であ
る。FIG. 4 is a sectional view taken along the line VIII-VIII ′ of FIG.

【図５】従来のパワーＭＯＳＦＥＴの一例を示す一部平
面図である。FIG. 5 is a partial plan view showing an example of a conventional power MOSFET.

【図６】図５のII−II′線で切断した断面図である。FIG. 6 is a sectional view taken along the line II-II ′ of FIG.

【図７】従来のパワーＭＯＳＦＥＴの他の例を示す一部
平面図である。FIG. 7 is a partial plan view showing another example of a conventional power MOSFET.

【図８】図７のIV−IV′線で切断した断面図である。FIG. 8 is a sectional view taken along line IV-IV ′ of FIG. 7;

【符号の説明】[Explanation of symbols]

１１ Ｎ型Ｓｉ基板（Ｎ型エピタキシャル層Ｎ型ウェ
ル層） １３ Ｐ型ベース層 １５ Ｎ+ 型ドレイン層 １５ａ Ｎ+ 型ドレイン引出し層 １７ フィールド酸化膜 １９ Ｎ+ 型ソース層 ２１ ゲート酸化膜 ２３ ゲート電極 ３３ａ ゲート電極開口部 ２５ ソースコンタクトホール ２７ ドレインコンタクトホール ２９ 第１層間絶縁膜 ３１ 第１金属電極 ３３ 第２層間絶縁膜 ３５ 第２金属電極 ３７ コンタクトホールReference Signs List 11 N-type Si substrate (N-type epitaxial layer N-type well layer) 13 P-type base layer 15 N + -type drain layer 15 a N + -type drain extraction layer 17 Field oxide film 19 N + -type source layer 21 Gate oxide film 23 Gate electrode 33a Gate electrode opening 25 Source contact hole 27 Drain contact hole 29 First interlayer insulating film 31 First metal electrode 33 Second interlayer insulating film 35 Second metal electrode 37 Contact hole

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１導電型Ｓｉ基板と，該Ｓｉ基板上に
形成された複数の八角形のチャンネル領域でありこのチ
ャンネル領域同士が等ピッチ間隔で互いに縦横に直交す
る方向に形成される第２導電型ベース層と，隣接する４
個の前記ベース層からなる正方形の中心位置に形成さ
れ，前記４個の前記ベース層の前記八角形の短辺の内の
前記中心位置に一番近い短辺に夫々対向するように４辺
を持つ菱形状の第１導電型ドレイン層と，このドレイン
層の中心上の絶縁膜中に形成され，前記ベース層からな
る正方形の対角線に沿う四辺を備えた正方形を含む菱形
状に形成されるドレインコンタクトホールと，前記Ｓｉ
基板上の前記ベース層と前記ドレイン層との間にあるフ
ィールド酸化膜と，前記ベース層内に八角形の枠状に形
成された第１導電型ソース層と，このソース層の中心上
の前記絶縁膜に形成されたソースコンタクトホールと，
前記ソース層の外側と前記フィールド酸化膜との間に前
記ベース層の絶縁部と前記フィールド酸化膜の一部を覆
って形成されたゲート酸化膜と，前記ソース層の縁を前
記ゲート酸化膜を介して八角形の枠状に覆い，前記ソー
スコンタクトホールとドレインコンタクトホールとを前
記絶縁膜を挟んで囲む曲折したメッシュ状に形成されて
いるゲート電極とを備えていることを特徴とする横型Ｄ
ＳＡパワーＭＯＳＦＥＴを備えた半導体装置。A first conductivity type Si substrate and a first conductivity type Si substrate on the Si substrate;
A plurality of octagonal channel areas formed
The channel regions are vertically and horizontally orthogonal to each other at equal pitch intervals.
And a second conductive type base layer formed in
Formed at the center of a square consisting of the base layers.
Of the short sides of the octagon of the four base layers
4 sides so as to face the short sides closest to the center position, respectively
Diamond-shaped first conductivity type drain layer having
Formed in the insulating film on the center of the layer,
Including a square with four sides along the diagonal of the square
A drain contact hole formed in the shape of
A substrate between the base layer and the drain layer on the substrate;
Field oxide film and an octagonal frame in the base layer.
A source layer of the first conductivity type formed on the center of the source layer;
A source contact hole formed in said insulating film;
Between the outside of the source layer and the field oxide
Cover the insulating portion of the base layer and a part of the field oxide film.
The edge of the source oxide layer and the gate oxide film
The gate is covered with an octagonal frame through a gate oxide film.
Contact hole and drain contact hole
It is formed in a bent mesh shape surrounding the insulating film
Horizontal D, characterized in that a gate electrode are
A semiconductor device including an SA power MOSFET .
JP7280085A 1995-10-27 1995-10-27 Semiconductor device having lateral DSA power MOSFET Expired - Lifetime JP2800884B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7280085A JP2800884B2 (en) 1995-10-27 1995-10-27 Semiconductor device having lateral DSA power MOSFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7280085A JP2800884B2 (en) 1995-10-27 1995-10-27 Semiconductor device having lateral DSA power MOSFET

Publications (2)

Publication Number Publication Date
JPH09129867A JPH09129867A (en) 1997-05-16
JP2800884B2 true JP2800884B2 (en) 1998-09-21

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ID=17620109

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Country Link
JP (1) JP2800884B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2003060197A (en) * 2001-08-09 2003-02-28 Sanyo Electric Co Ltd Semiconductor device
JP4574134B2 (en) * 2003-07-23 2010-11-04 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4868710B2 (en) 2004-03-24 2012-02-01 富士通セミコンダクター株式会社 Horizontal MOS transistor
US7730119B2 (en) 2006-07-21 2010-06-01 Sony Computer Entertainment Inc. Sub-task processor distribution scheduling
US7955893B2 (en) 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US8222078B2 (en) 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
US8362606B2 (en) 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
JP5920407B2 (en) * 2013-07-16 2016-05-18 株式会社デンソー Semiconductor device
CN108538925B (en) * 2018-06-15 2024-05-14 深圳基本半导体有限公司 Silicon carbide junction barrier Schottky diode
CN116344530A (en) * 2021-12-24 2023-06-27 长鑫存储技术有限公司 Transistor unit, array thereof and integrated circuit

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NL8302092A (en) * 1983-06-13 1985-01-02 Philips Nv SEMICONDUCTOR DEVICE CONTAINING A FIELD-EFFECT TRANSISTOR.
JPH07112064B2 (en) * 1986-02-10 1995-11-29 株式会社東芝 Insulated gate field effect transistor
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