JP2798605B2 - Manufacturing method of mounting device - Google Patents

Manufacturing method of mounting device

Info

Publication number
JP2798605B2
JP2798605B2 JP6089280A JP8928094A JP2798605B2 JP 2798605 B2 JP2798605 B2 JP 2798605B2 JP 6089280 A JP6089280 A JP 6089280A JP 8928094 A JP8928094 A JP 8928094A JP 2798605 B2 JP2798605 B2 JP 2798605B2
Authority
JP
Japan
Prior art keywords
pin
female
substrate
male
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6089280A
Other languages
Japanese (ja)
Other versions
JPH07297197A (en
Inventor
健一郎 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6089280A priority Critical patent/JP2798605B2/en
Publication of JPH07297197A publication Critical patent/JPH07297197A/en
Application granted granted Critical
Publication of JP2798605B2 publication Critical patent/JP2798605B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H01L2224/81899—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other using resilient parts in the bump connector or in the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は実装装置およびその製造
方法に係わり、特に半導体チップとパッケージ基板間、
あるいは半導体チップと他の半導体チップ間の電気的接
続を行うことにより構成された実装装置およびその製造
方法に関し、コンタクトパッド間の間隔が小さい高密度
実装の技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting apparatus and a method for manufacturing the same, and more particularly, to a method for mounting a semiconductor chip and a package substrate.
Alternatively, the present invention relates to a mounting apparatus configured by making electrical connection between a semiconductor chip and another semiconductor chip and a method of manufacturing the same, and relates to a high-density mounting technique with a small interval between contact pads.

【０００２】[0002]

【従来の技術】図１１に特開昭６４−８１２６４号公報
に開示されてあるような従来の実装技術を示す。2. Description of the Related Art FIG. 11 shows a conventional mounting technique as disclosed in Japanese Patent Application Laid-Open No. 64-81264.

【０００３】一方のチップの基板に設けられたコンタク
トパッド９５の上に先端が半径方向に張りだした張出し
部９３を有する雄ピン９１が形成されている。また、他
方のチップの基板に設けられたコンタクトパッド９６の
上に先端の開口が狭くなった凹部９４を有する雌ピン９
２が形成されている。そしてこの二つの基板を矢印９に
示すように相対的に近づけ互いに押しつけ張出し部９３
を凹部９４内に噛み合せることによって雄ピン９１が雌
ピン９２の中に嵌合され、雄ピン９１の張出し部９３の
先端面がコンタクトパッド９６に当接することにより、
コンタクトパッド９５と９６が電気的に接続される。A male pin 91 having a projecting portion 93 whose tip projects in the radial direction is formed on a contact pad 95 provided on the substrate of one chip. A female pin 9 having a concave portion 94 with a narrower opening at the tip is provided on a contact pad 96 provided on the substrate of the other chip.
2 are formed. Then, the two substrates are relatively brought close to each other as shown by the arrow 9 and pressed against each other to form an overhang portion 93.
The male pin 91 is fitted into the female pin 92 by meshing the male pin 91 into the concave portion 94, and the distal end surface of the projecting portion 93 of the male pin 91 comes into contact with the contact pad 96.
Contact pads 95 and 96 are electrically connected.

【０００４】またこの構造は、紫外線を利用したフォト
リソグラフィ−によってレジストに開口部を設け、この
開口部に蒸着あるいはスパッタ−により金属を堆積させ
た後、レジストを剥離するという一連の工程を複数回繰
り返すことによって作製されている。特に、雄ピン９１
の先端に形成される張出し部９３および雌ピン９２の先
端に形成される凹部９４を形成するために、ポジレジス
トを用いたフォトリソグラフィ−工程と同時にネガレジ
ストを用いたフォトリソグラフィ−工程を同一ピンを形
成する際に繰り返し使用する作製方法である。In this structure, a series of steps of providing an opening in a resist by photolithography using ultraviolet rays, depositing a metal in the opening by vapor deposition or sputtering, and then removing the resist are performed a plurality of times. It is made by repeating. In particular, male pin 91
In order to form the overhang portion 93 formed at the tip of the pin and the concave portion 94 formed at the tip of the female pin 92, a photolithography process using a positive resist and a photolithography process using a negative resist are performed at the same time. This is a manufacturing method that is used repeatedly when forming a.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら上述した
図１１に示す構造では次に示す欠点があることが明らか
になった。すなわち、１）チップの面積が大きくなるに
従って、基板の反りの影響を受けるため先端部に設けら
れた凹凸構造の嵌合の接触部に大きな力が発生する。こ
の基板の反りは、４インチのシリコン基板の場合は通常
３０μｍ程度であるが、パッケージ基板や化合物基板で
はさらに大きくなる。このために、先端部の破壊が頻繁
に生じるようになった。また、雌ピン９２の先端部に設
けられている凹部９４は図で下方向の力に比べて上方向
の力に対して変形し易いという構造的な問題がある。こ
のような理由により、雄ピンと雌ピンとの嵌合を保持で
きなくなり、接続が離れ易いという欠点がある。２）雄
ピンと雌ピンは主に先端部の凹凸構造において互いに接
触するために、この接触面積が小さいことから、接続に
あたって配線抵抗が大きくなるという問題がある。ま
た、個々のピンの配線抵抗はピンの張出し部９３と凹部
９４との接触面積の大きさに大きく依存するために、個
々のピンの形状のばらつきによって個々の配線抵抗がば
らつくという問題がある。この問題は、ピンの寸法が小
さくなるに従ってますます深刻になった。３）また、反
りの大きな基板ではチップ全体を完全に嵌合することが
困難になるため、チップの面積が大きくなるに従って、
未接続ピンの数が増大した。この嵌合の困難さは、高さ
と紫外線のフォトリソグラフィ−によって作製できるパ
ターンの比（高さ／パターン：アスペクト比）が３−４
程度と小さなものであるという制限から生じる。例え
ば、雄ピンの直径が５μｍ程度、雌ピンの肉厚が１μｍ
としたとき、作製できるピンの高さは雌ピンの高さの制
約から４μｍ以下となる。このように、雌ピンの中に雄
ピンを挿入する遊びが小さいことから完全に雄ピンと雌
ピンを嵌合させることが困難となるため、ピンの間隔が
著しく小さい高密度実装を実現することが不可能であっ
た。４）また、ピンの高さが低いために基板の間の間隔
が狭くなり、これにより基板を冷却する効率が低くな
る。５）さらに、一種類のピンを作製するのに、ポジ型
とネガ型のフォトリソグラフィ−工程を同時に多数回使
用することに加えて蒸着やスパッタ−工程を繰り返し使
用することから、作製方法が複雑となる。以上の欠点か
ら、図１１の従来技術では５０μｍ程度のピッチをもつ
実装装置を提供するのが限度であった。However, it has been found that the structure shown in FIG. 11 has the following disadvantages. That is, 1) as the area of the chip increases, the chip is affected by the warpage of the substrate, so that a large force is generated at the fitting contact portion of the concavo-convex structure provided at the front end. The warpage of this substrate is usually about 30 μm in the case of a 4-inch silicon substrate, but becomes larger in the case of a package substrate or a compound substrate. This has led to frequent breakage of the tip. Further, there is a structural problem that the concave portion 94 provided at the distal end of the female pin 92 is easily deformed by an upward force as compared with a downward force in the figure. For this reason, there is a disadvantage that the fitting between the male pin and the female pin cannot be maintained, and the connection is easily separated. 2) Since the male pin and the female pin are mainly in contact with each other in the concave-convex structure at the tip, the contact area is small, so that there is a problem in that the wiring resistance increases in connection. Further, since the wiring resistance of each pin largely depends on the size of the contact area between the protruding portion 93 and the concave portion 94 of the pin, there is a problem that the wiring resistance varies due to variations in the shape of each pin. This problem became more severe as the pin dimensions became smaller. 3) Further, since it is difficult to completely fit the entire chip with a substrate having a large warp, as the chip area increases,
The number of unconnected pins has increased. The difficulty of the fitting is that the ratio (height / pattern: aspect ratio) of the height and the pattern that can be produced by photolithography of ultraviolet rays is 3-4.
It arises from the limitations of being of a small degree. For example, the diameter of the male pin is about 5 μm and the thickness of the female pin is 1 μm
In this case, the height of the pin that can be produced is 4 μm or less due to the restriction of the height of the female pin. As described above, it is difficult to completely fit the male pin and the female pin because the play for inserting the male pin into the female pin is small, so that it is possible to realize high-density mounting in which the interval between the pins is extremely small. It was impossible. 4) Also, since the height of the pins is low, the spacing between the substrates is narrowed, thereby reducing the efficiency of cooling the substrates. 5) In addition, since a positive pin and a negative photolithography process are used many times at the same time, and a vapor deposition and a sputtering process are repeatedly used for manufacturing one kind of pin, the manufacturing method is complicated. Becomes Due to the above disadvantages, the prior art shown in FIG. 11 has been limited to providing a mounting device having a pitch of about 50 μm.

【０００６】 したがって本発明の目的は、基板の反り
によっても接続が確保でき、かつ接触抵抗を小にするこ
とができる実装装置の製造方法を提供することである。Therefore, an object of the present invention is to provide a method of manufacturing a mounting apparatus which can secure connection even by warpage of a substrate and can reduce contact resistance.

【０００７】 本発明の他の目的は、未接続ピンが発生
しないように、ピン間隔を小にしてより高密度実装とな
るように、また基板の冷却効率を高めるようにピン構造
のアスペクト比を大きくすることができる製造方法を適
用することが可能な実装装置の製造方法を提供すること
である。Another object of the present invention is to reduce the aspect ratio of the pin structure so that unconnected pins do not occur, pin spacing is reduced to achieve higher-density mounting, and cooling efficiency of the substrate is increased. An object of the present invention is to provide a method of manufacturing a mounting device to which a manufacturing method that can be enlarged can be applied.

【０００８】本発明の別の目的は、複雑な工程を用いる
ことなく接続ピン構造を得ることができる実装装置の製
造方法を提供することである。Another object of the present invention is to provide a method of manufacturing a mounting device capable of obtaining a connection pin structure without using complicated steps.

【０００９】[0009]

【課題を解決するための手段】 本発明は、第１の基板
のコンタクトパッド上に金属メッキによって作製された
雄ピンと第２の基板のコンタクトパッド上に金属メッキ
によって作製された雌ピンとを嵌合して、前記雄ピンと
前記雌ピンを互いの側壁で接触させることにより電気的
接続を行い、かつ前記雄ピンと前記雌ピンが互いの側壁
で接触する面積を、前記雄ピンの先端と前記雌ピンに接
続するコンタクトパッドに接触する面積以上となるよう
に前記雄ピンと前記雌ピンの高さを高くした高密度実装
装置の製造方法であって、Ｘ線に感光する二層のネガ型
レジストの間に紫外線に感光するネガ型レジストを設け
てＸ線と紫外線を順次照射した後現像し、メッキにより
高さ方向の中間部に前記くびれ構造を有する一方の雄ピ
ンもしくは雌ピンを作製し、Ｘ線に感光する二層のポジ
型レジストの間に紫外線に感光するポジ型レジストを設
けてＸ線と紫外線を順次照射した後現像し、メッキによ
り高さ方向の中間部に前記くびれ構造と嵌合可能な突起
構造を一体構造で設けた他方の雌ピンもしくは雄ピンを
作製することを特徴とする高密度実装装置の製造方法で
ある。 Means for Solving the Problems According to the present invention, a male pin formed by metal plating on a contact pad of a first substrate and a female pin formed by metal plating on a contact pad of a second substrate are fitted. The male pin and the female pin are brought into contact with each other on their side walls to make electrical connection , and the male pin and the female pin are
Contact area between the male pin and the female pin.
So that it is at least larger than the area in contact with the subsequent contact pads.
High-density mounting in which the height of the male pin and the female pin is increased
A method of manufacturing a device, comprising a two-layer negative type sensitive to X-rays.
Negative resist that is sensitive to ultraviolet light is provided between resists
X-rays and ultraviolet rays are sequentially irradiated, developed, and plated.
One male pin having the constricted structure at the middle in the height direction
Or female pin, and a two-layer positive
A positive resist that is exposed to ultraviolet light
X-rays and ultraviolet rays are sequentially irradiated, developed, and plated.
A protrusion which can be fitted to the constricted structure at an intermediate portion in the height direction
The other female pin or male pin with the integrated structure
Manufacturing method of high-density mounting equipment characterized by manufacturing
is there.

【００１０】[0010]

【００１１】ここで前記くびれ構造もしくは前記突起構
造が設けられた前記雄ピンの外側および前記突起構造も
しくは前記くびれ構造が設けられた前記雌ピンの内側
に、これらピンを構成する主要材料より融点が低い金属
膜が形成されており、前記嵌合後の前記金属膜の溶融に
より互いに接続していることが好ましい。また前記雄ピ
ンは円柱状の形状であり、前記雌ピンは円筒状の形状で
あることができる。あるいは前記雄ピンは基板の表面と
平行方向の断面が長方形の角柱形状であり、前記雌ピン
は基板の表面と平行方向の断面が長方形の一対の角柱形
状であり、前記雌ピンの一対の角柱形状間に前記雄ピン
の角柱形状を嵌合させて電気的接続を行うこともでき
る。また前記第１および第２の基板のうち一方の基板は
半導体チップを構成する半導体基板であり、他方の基板
は前記半導体チップを搭載するパッケージのパッケージ
基板であることができる。あるいは前記第１および第２
の基板のそれぞれは半導体チップを構成する半導体基板
であることもできる。Here, the melting point of the main material constituting these pins is outside the male pin provided with the constricted structure or the protruding structure and inside the female pin provided with the protruding structure or the constricted structure. It is preferable that a low metal film is formed, and the metal films are connected to each other by melting of the metal films after the fitting. The male pin may have a columnar shape, and the female pin may have a cylindrical shape. Alternatively, the male pin has a rectangular prism shape in a cross section parallel to the surface of the substrate, and the female pin has a pair of rectangular prisms in a cross section parallel to the surface of the substrate, and a pair of prisms of the female pin. The electrical connection can also be made by fitting the prismatic shape of the male pin between the shapes. Further, one of the first and second substrates may be a semiconductor substrate constituting a semiconductor chip, and the other substrate may be a package substrate of a package on which the semiconductor chip is mounted. Alternatively, the first and second
Each of the substrates may be a semiconductor substrate constituting a semiconductor chip.

【００１２】[0012]

【実施例】以下、本発明を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【００１３】図１は本発明の第１の実施例を示す断面図
である。Ｎ型シリコン基体３１に形成されたＰ+ 不純物
領域３２と、この領域にオーミック接続するアルミから
なるコンタクトパッド５と、基体を全体的に被覆しコン
タクトパッド５を露出する開口を形成したシリコン酸化
膜３３とを有してシリコン基板３０が半導体チップとし
て構成されている。またこの半導体チップを搭載するパ
ッケージのパッケージ基板４０は、セラミック基体４１
と、この基体４１の表面上に形成されたアルミ配線と、
アルミ配線を含む基体を全体的に被覆し、アルミ配線の
コンタクトパッド６の部分を露出する開口を形成したコ
ーティング絶縁膜４３とを有して構成されている。そし
てシリコン基板３０のコンタクトパッド５上には雄ピン
１が接続形成され、パッケージ基板４０のコンタクトパ
ッド６上には雌ピン２が接続形成されている。FIG. 1 is a sectional view showing a first embodiment of the present invention. P + impurity region 32 formed in N-type silicon substrate 31, contact pad 5 made of aluminum for ohmic connection to this region, and silicon oxide film covering the entire substrate and forming an opening exposing contact pad 5 33, the silicon substrate 30 is configured as a semiconductor chip. The package substrate 40 of the package on which the semiconductor chip is mounted is formed of a ceramic base 41.
And aluminum wiring formed on the surface of the base 41;
And a coating insulating film 43 which entirely covers the base including the aluminum wiring and has an opening for exposing the contact pad 6 of the aluminum wiring. The male pins 1 are formed on the contact pads 5 of the silicon substrate 30, and the female pins 2 are formed on the contact pads 6 of the package substrate 40.

【００１４】シリコン基板３０の水平方向（以下、Ｘ方
向、と称す）に延在するコンタクトパッド５から垂直方
向（以下、Ｙ方向、と称す）に雄ピン１が延在して接続
形成されている。雄ピン１は主要材料のメッキ部１１と
薄い金属膜１２から構成され、メッキ部の側壁すなわち
雄ピン１の側壁（外側壁）１３のＹ方向の中央部にくび
れ３が形成されている。A male pin 1 extends from a contact pad 5 extending in a horizontal direction (hereinafter, referred to as an X direction) of a silicon substrate 30 in a vertical direction (hereinafter, referred to as a Y direction). I have. The male pin 1 is composed of a plated portion 11 of a main material and a thin metal film 12, and a constriction 3 is formed in the side wall of the plated portion, that is, the center of the side wall (outer wall) 13 of the male pin 1 in the Y direction.

【００１５】一方、パッケージ基板４０のＸ方向に延在
するコンタクトパッド６からＹ方向に雌ピン２が延在し
て接続形成されている。雌ピン２は主要材料のメッキ部
２１と薄い金属膜２２から構成され、その内側壁２３す
なわちメッキ部の側壁の中央部に突起４の構造を有して
いる。この突起４の寸法はくびれ３の寸法よりも少し小
さくなるように設計されている。On the other hand, the female pins 2 extend in the Y direction from the contact pads 6 extending in the X direction of the package substrate 40 and are connected to each other. The female pin 2 is composed of a plated portion 21 of a main material and a thin metal film 22, and has a structure of a projection 4 on an inner side wall 23, that is, a central portion of a side wall of the plated portion. The dimension of the projection 4 is designed to be slightly smaller than the dimension of the constriction 3.

【００１６】そしてこの二つの基板を矢印９に示すよう
に相対的に近づけ互いに押しつけくびれ３内に突起４を
噛み合せれ、雄ピン３が雌ピン２中に嵌合される。The two substrates are brought closer to each other as shown by an arrow 9 and pressed together to engage the projection 4 in the constriction 3 so that the male pin 3 is fitted into the female pin 2.

【００１７】尚、上記図１では半導体チップに雄ピンを
設けパッケージに雌ピンを設けた例を示したが、半導体
チップに雌ピンを設けパッケージに雄ピンを設けてもよ
いことは言うまでもない。Although FIG. 1 shows an example in which male pins are provided on a semiconductor chip and female pins are provided on a package, it goes without saying that female pins may be provided on a semiconductor chip and male pins may be provided on a package.

【００１８】図２はこれら二つのピンを互いに接続させ
たときの状態を示す断面図である。尚、図２ではコンタ
クトパッド以外の基板要素は図示を省略してあり、また
図１と同一の構成要素は同じ符号で示している。FIG. 2 is a sectional view showing a state when these two pins are connected to each other. In FIG. 2, the substrate elements other than the contact pads are not shown, and the same components as those in FIG. 1 are denoted by the same reference numerals.

【００１９】図２に示すように、突起４の寸法がくびれ
３よりも少し小さいために、両者の間に間隙１８が存在
している。このため、雄ピン１と雌ピン２はそれぞれの
側壁１３，２３において互いに接触することができる。As shown in FIG. 2, since the size of the projection 4 is slightly smaller than that of the constriction 3, a gap 18 exists between them. Therefore, the male pin 1 and the female pin 2 can contact each other on the respective side walls 13 and 23.

【００２０】雄ピン１は、例えば直径２μｍの円形の平
面積で高さ（Ｙ方向の寸法）が５００μｍの円柱状であ
り、円筒状の雌ピン２の内壁側も同じ寸法である。この
ようなときには、雄ピン１の先端面とコンタクトパッド
６との接触面積および雌ピン２の先端面とコンタクトパ
ッド５との接触面積の大きさは、両ピンが接触する側壁
１３，２３の大きさに比べて小さなものとなる。The male pin 1 has a circular plane area of, for example, a diameter of 2 μm and a height (dimension in the Y direction) of 500 μm. The inner wall of the cylindrical female pin 2 has the same dimensions. In such a case, the size of the contact area between the tip surface of the male pin 1 and the contact pad 6 and the size of the contact area between the tip surface of the female pin 2 and the contact pad 5 are determined by the size of the side walls 13 and 23 with which both pins contact. It is smaller than that.

【００２１】このために、従来はコンタクトパッドとピ
ンの先端面とを十分に接触させなければならないという
要求が、本発明では重要なものではなくなった。For this reason, in the present invention, the requirement that the contact pad and the tip end face of the pin have to be sufficiently contacted is no longer important in the present invention.

【００２２】図３は図１の実施例において、上記寸法例
示したように、雄ピン１が円柱形状で雌ピン２が円筒形
状の場合を示す斜視図である。FIG. 3 is a perspective view showing a case where the male pin 1 has a cylindrical shape and the female pin 2 has a cylindrical shape as exemplified in the above dimensions in the embodiment of FIG.

【００２３】図４は図１の実施例において、雄ピン１が
長方形断面の長方形の角柱形状であり、対向する二つの
側壁１３にそれぞれ、くびれ３が形成されている。一
方、雌ピン２が長方形断面の長方形の角柱形状である二
つの互いに対向するピン部材から構成されている。この
互いに対向する内側の側壁２３にそれぞれ突起４が形成
され、雄ピン１が雌ピン２の一対のピン部材間に嵌合さ
れ、一対のくびれ３がそれぞれの突起４と嵌合する。図
４の構成は、図３の構成と比較して、雌ピンの変形が容
易であるために、雄ピンを雌ピンの中に小さな力で嵌合
できるという特徴がある。FIG. 4 shows the embodiment of FIG. 1 in which the male pin 1 is in the shape of a rectangular prism having a rectangular cross section, and the constriction 3 is formed on each of two opposing side walls 13. On the other hand, the female pin 2 is composed of two opposing pin members having a rectangular prism shape with a rectangular cross section. The protrusions 4 are formed on the inner side walls 23 facing each other, the male pin 1 is fitted between a pair of pin members of the female pin 2, and the pair of constrictions 3 are fitted with the respective protrusions 4. The configuration of FIG. 4 has a feature that the male pin can be fitted into the female pin with a small force because the female pin is easier to deform than the configuration of FIG.

【００２４】尚、図３および図４においてコンタクトパ
ッド以外の基板要素は図示を省略してあり、また図１と
同一の構成要素は同じ符号で示している。In FIGS. 3 and 4, the substrate elements other than the contact pads are not shown, and the same components as those in FIG. 1 are denoted by the same reference numerals.

【００２５】図５は上記実施例の雄ピンを作製する製造
方法の実施例をプロセス順に示す断面図である。FIG. 5 is a sectional view showing an embodiment of a method of manufacturing the male pin of the above embodiment in the order of processes.

【００２６】まず図５（Ａ）に示すように、シリコン基
板３０全面上に薄い金属膜１２、例えば白金膜を形成す
る。金属膜１２がレジストパターンから露出する箇所か
らメッキを成長させるからこの金属膜はメッキを行う際
のシーズ（種、ｓｅｅｄ）となる。すなわち金属膜１２
は図１のシリコン酸化膜３３上から露出するコンタクト
パッド５の表面上に被着して形成する。この金属膜１２
上に、ネガ型のＸ線レジスト５１、ネガ型の紫外線レジ
スト５２およびネガ型のＸ線レジスト５３の三層レジス
トを塗布法によりを積層形成する。そしてＸ線吸収体パ
ターン５４Ａが設けられたＸ線マスク５４を用いて、シ
ンクロトロンから放射された直線性の優れたＸ線５６を
上記レジスト５１，５２，５３に選択的に照射する。こ
のとき、Ｘ線レジスト５１，５３に加えて紫外線レジス
ト５２も光化学反応が起こるため、Ｘ線吸収体パターン
５４Ａの直下以外のレジストの部分（同図で点線間に実
線を入れて示した）５１Ｘ，５２Ｘ，５３Ｘが感光され
る。First, as shown in FIG. 5A, a thin metal film 12, for example, a platinum film is formed on the entire surface of a silicon substrate 30. Since the metal film 12 grows from the position where the metal film 12 is exposed from the resist pattern, this metal film serves as a seed for plating. That is, the metal film 12
Is formed on the surface of the contact pad 5 exposed from the silicon oxide film 33 in FIG. This metal film 12
A three-layer resist of a negative type X-ray resist 51, a negative type ultraviolet resist 52 and a negative type X-ray resist 53 is formed thereon by a coating method. Then, the X-ray mask 54 provided with the X-ray absorber pattern 54A is used to selectively irradiate the resists 51, 52, and 53 with X-rays 56 having excellent linearity emitted from the synchrotron. At this time, since a photochemical reaction occurs in the ultraviolet resist 52 in addition to the X-ray resists 51 and 53, a portion of the resist other than immediately below the X-ray absorber pattern 54A (shown by a solid line between dotted lines in the drawing) 51X , 52X, 53X are exposed.

【００２７】次に図５（Ｂ）に示すように、先のＸ線吸
収体パターン５４Ａよりも小さな寸法をもつ紫外線吸収
体パターン５５Ａをもつマスク５５を用いて、紫外線５
７をレジスト５１，５２，５３上に選択的に照射する。
このときＸ線レジスト５１，５３は紫外線５７により感
光されないから、Ｘ線吸収体パターン５４Ａの直下と紫
外線吸収体パターン５５Ａの直下との間に位置する紫外
線レジスト５２の部分５２Ｕのみが新らたに感光され
る。ここが雄ピンのくびれとなる。Next, as shown in FIG. 5 (B), the ultraviolet rays 5 are formed by using a mask 55 having an ultraviolet absorber pattern 55A having a smaller size than the X-ray absorber pattern 54A.
7 is selectively irradiated onto the resists 51, 52 and 53.
At this time, since the X-ray resists 51 and 53 are not exposed to the ultraviolet ray 57, only the portion 52U of the ultraviolet resist 52 located immediately below the X-ray absorber pattern 54A and immediately below the ultraviolet absorber pattern 55A is newly obtained. It is exposed. This is the constriction of the male pin.

【００２８】次に図５（Ｃ）に示すように、この試料を
ネガ型の現像液の中に侵すことにより、未反応部を除去
して、コンタクトパッド５（図１）上に未反応部による
開口部５９を形成したレジスト５１，５２，５３のパタ
ーンを得る。Next, as shown in FIG. 5C, the unreacted portion is removed by immersing the sample in a negative developing solution, and the unreacted portion is left on the contact pad 5 (FIG. 1). The patterns of the resists 51, 52 and 53 in which the openings 59 are formed are obtained.

【００２９】次に図５（Ｄ）に示すように、金属膜１２
をシーズとして電気メッキを行い、開口部５９内に雄ピ
ン１の主要材料であるメッキ部１１を構成する金属材料
を埋め込む。このメッキによる材料は、銅もしくはニッ
ケルであるが場合によってはタングステンもしくはモリ
ブデンであることができる。その後、全てのレジストを
剥離することにより雄ピン１を得る。Next, as shown in FIG.
Is used as a seed to perform electroplating, and the opening 59 is filled with a metal material constituting the plating portion 11 which is a main material of the male pin 1. The material from this plating may be copper or nickel, but in some cases tungsten or molybdenum. Thereafter, the male pin 1 is obtained by removing all the resist.

【００３０】最後に、イオンミリング法を用いて、雄ピ
ンの金属膜１２となる部分以外の露出する金属膜１２を
除去する。Finally, the exposed metal film 12 other than the portion to be the metal film 12 of the male pin is removed by using the ion milling method.

【００３１】図６は上記実施例の雌ピンを作製する製造
方法の実施例をプロセス順に示す断面図である。FIG. 6 is a sectional view showing an embodiment of a method of manufacturing the female pin of the above embodiment in the order of processes.

【００３２】まず図６（Ａ）に示すように、パッケージ
基板４０全面上に薄い金属膜２２、例えば白金膜を形成
する。金属膜２２がレジストパターンから露出する箇所
からメッキを成長させるからこの金属膜はメッキを行う
際のシーズ（種、ｓｅｅｄ）となる。すなわち金属膜２
２は図１のシリコン酸化膜４３上から露出するコンタク
トパッド６の表面上に被着して形成する。この金属膜２
２上に、ポジ型のＸ線レジスト６１、ポジ型の紫外線レ
ジスト６２およびポジ型のＸ線レジスト６３の三層レジ
ストを塗布法によりを積層形成する。そしてＸ線吸収体
パターン６４Ａが設けられたＸ線マスク６４を用いて、
シンクロトロンから放射された直線性の優れたＸ線５６
を上記レジスト６１，６２，６３に選択的に照射する。
このとき、Ｘ線レジスト６１，６３に加えて紫外線レジ
スト６２も光化学反応が起こるため、Ｘ線吸収体パター
ン６４Ａの直下以外のレジストの部分（同図で点線間に
実線を入れて示した）６１Ｘ，６２Ｘ，６３Ｘが感光さ
れる。First, as shown in FIG. 6A, a thin metal film 22, for example, a platinum film is formed on the entire surface of the package substrate 40. Since the plating is grown from a position where the metal film 22 is exposed from the resist pattern, the metal film serves as a seed for plating. That is, the metal film 2
2 is formed on the surface of the contact pad 6 exposed from the silicon oxide film 43 of FIG. This metal film 2
A three-layer resist of a positive type X-ray resist 61, a positive type ultraviolet ray resist 62, and a positive type X-ray resist 63 is formed on the layer 2 by a coating method. Then, using the X-ray mask 64 provided with the X-ray absorber pattern 64A,
X-ray with excellent linearity emitted from synchrotron 56
Is selectively applied to the resists 61, 62, and 63.
At this time, in addition to the X-ray resists 61 and 63, a photochemical reaction occurs in the ultraviolet resist 62, so that the resist portion 61X other than immediately below the X-ray absorber pattern 64A (shown by a solid line between the dotted lines in the figure) 61X , 62X, 63X are exposed.

【００３３】次に図６（Ｂ）に示すように、先のＸ線吸
収体パターン６４Ａよりも小さな寸法をもつ紫外線吸収
体パターン６５Ａをもつマスク６５を用いて、紫外線５
７をレジスト６１，６２，６３上に選択的に照射する。
このときＸ線レジスト６１，６３は紫外線５７により感
光されないから、Ｘ線吸収体パターン６４Ａの直下と紫
外線吸収体パターン６５Ａの直下との間に位置する紫外
線レジスト６２の部分６２Ｕのみが新らたに感光され
る。ここが雌ピンの突起となる。Next, as shown in FIG. 6B, the ultraviolet rays 5 are applied by using a mask 65 having an ultraviolet absorber pattern 65A having a smaller size than the X-ray absorber pattern 64A.
7 is selectively irradiated onto the resists 61, 62 and 63.
At this time, since the X-ray resists 61 and 63 are not exposed to the ultraviolet rays 57, only the portion 62U of the ultraviolet resist 62 located immediately below the X-ray absorber pattern 64A and immediately below the ultraviolet absorber pattern 65A is newly obtained. It is exposed. This is the projection of the female pin.

【００３４】次に図６（Ｃ）に示すように、この試料を
ポジ型の現像液の中に侵すことにより、未反応部を除去
して、コンタクトパッド６（図１）上に反応部による開
口部６９を形成したレジスト６１，６２，６３のパター
ンを得る。Next, as shown in FIG. 6 (C), the sample is immersed in a positive developing solution to remove the unreacted portions, and the contact portions 6 are formed on the contact pads 6 (FIG. 1). The pattern of the resists 61, 62, 63 having the openings 69 is obtained.

【００３５】次に図６（Ｄ）に示すように、金属膜２２
をシーズとして電気メッキを行い、開口部６９内に雄ピ
ン２の主要材料であるメッキ部２１を構成する金属材料
を埋め込む。このメッキによる材料は、銅もしくはニッ
ケルであるが場合によってはタングステンもしくはモリ
ブデンであることができる。その後、全てのレジストを
剥離することにより突起４が内側壁に形成された有する
雌ピン２を得る。Next, as shown in FIG.
Is used as a seed to perform electroplating, and the opening 69 is filled with a metal material constituting the plating portion 21 which is a main material of the male pin 2. The material from this plating may be copper or nickel, but in some cases tungsten or molybdenum. Thereafter, by removing all the resist, the female pin 2 having the protrusion 4 formed on the inner wall is obtained.

【００３６】最後に、イオンミリング法を用いて、雌ピ
ンの金属膜２２となる部分以外の露出する金属膜２２を
除去する。Finally, the exposed metal film 22 other than the portion to be the metal film 22 of the female pin is removed by using the ion milling method.

【００３７】尚、電気メッキによる成長を等方的にする
ために、現像により図５（Ｃ）および図６（Ｃ）のレジ
ストパターン形成後、レジストパターン上に膜厚３０ｎ
ｍ程度の薄い金属膜を補助シーズ膜として形成してから
メッキを行うことができる。この新たに追加した金属膜
は図５（Ｄ）および図６（Ｄ）の後のイオンミリングを
少し長時間行うことにより主シーズ膜である金属膜１
２，２２の露出する部分とともに除去されるが、３０ｎ
ｍ程度の薄い金属膜がメッキ部１１，２１のくぼみ３や
突起４の面に付着していても支障はない。In order to make the growth by electroplating isotropic, after forming the resist patterns of FIG. 5C and FIG.
After a metal film as thin as about m is formed as an auxiliary sheath film, plating can be performed. The newly added metal film is formed by performing the ion milling after FIGS. 5 (D) and 6 (D) for a little longer time so that the metal film 1 which is the main seed film is formed.
Removed along with the exposed portions of 2,22, but 30n
Even if a thin metal film having a thickness of about m is attached to the surfaces of the depressions 3 and the projections 4 of the plated portions 11 and 21, there is no problem.

【００３８】図７は本発明の第２の実施例を示す断面図
である。尚、図７においてコンタクトパッド以外の基板
要素は図示を省略してあり、また図１と同一もしくは類
似のの構成要素は同じ符号で示している。本実施例で
は、雄ピン１の外側表面と雌ピン２の内側表面にピンの
主要材料１１，２１よりも融点が低い金属膜７１，７２
がスパッタにより形成されている。雄ピン１を雌ピン２
の中に嵌合させた後、試料を加熱して低融点金属膜７１
と７２を溶融させて結合させる。このとき、雄ピン１と
雌ピン２のメッキによる主要材料１１，２１よりも低い
温度を用いることが重要である。従って、ピン１および
２の横方向の変形が生じないために、高密度の実装を行
うことができる。さらに、ピン１と２が確実に接続され
るために、ピンの機械的結合を強くできること、電気抵
抗を低く下げることができるの長所がある。ピン１およ
び２の主要材料１１，２１は上述のように銅（Ｃｕ）、
ニッケル（Ｎｉ）、タングステン（Ｗ）もしくはモリブ
デン（Ｍｏ）であることが好ましく、低融点金属膜７１
と７２の材料は半田もしくは金（Ａｕ）であることが好
ましい。FIG. 7 is a sectional view showing a second embodiment of the present invention. In FIG. 7, substrate elements other than the contact pads are not shown, and the same or similar components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, metal films 71 and 72 having a lower melting point than the main materials 11 and 21 of the pins are provided on the outer surface of the male pin 1 and the inner surface of the female pin 2.
Are formed by sputtering. Male pin 1 to female pin 2
Then, the sample is heated and the low melting point metal film 71 is heated.
And 72 are melted and combined. At this time, it is important to use a lower temperature than the main materials 11 and 21 formed by plating the male pins 1 and the female pins 2. Therefore, since the pins 1 and 2 do not deform in the horizontal direction, high-density mounting can be performed. Furthermore, since the pins 1 and 2 are securely connected, there are advantages that the mechanical coupling of the pins can be strengthened and the electric resistance can be reduced. The main materials 11 and 21 of the pins 1 and 2 are copper (Cu) as described above,
Nickel (Ni), tungsten (W) or molybdenum (Mo) is preferable, and the low melting point metal film 71 is used.
And 72 are preferably solder or gold (Au).

【００３９】図８は本発明の第３の実施例を示す断面図
である。尚、図８においてコンタクトパッド以外の基板
要素は図示を省略してあり、また図１と同一もしくは類
似の構成要素は同じ符号で示している。本実施例では雄
ピン１の先端に丸み８１を形成し、雌ピン２の先端に開
口が広くなった張出し部８２を形成している。これによ
り、雄ピン１が雌ピン２の中に容易に嵌合できるように
なる。FIG. 8 is a sectional view showing a third embodiment of the present invention. In FIG. 8, substrate elements other than the contact pads are not shown, and the same or similar components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, a roundness 81 is formed at the tip of the male pin 1, and a projecting portion 82 having a wide opening is formed at the tip of the female pin 2. Thereby, the male pin 1 can be easily fitted into the female pin 2.

【００４０】図９は本発明の第４の実施例を示す断面図
である。尚、図１と同一もしくは類似の構成要素は同じ
符号で示している。図１と異なる点は、雌ピン２も雄ピ
ン１と同様に半導体チップ上に形成され、半導体チップ
と半導体チップとを接続する場合である。すなわち本実
施例では、半導体チップを構成するシリコン基板９０の
Ｎ型シリコン基体９１にＰ+ 不純物領域９２が形成さ
れ、この領域９２にアルミからなるコンタクトパッド６
がオーミック接続している。そして基体を全体的に被覆
したシリコン酸化膜９３の開口に露出したコンタクトパ
ッド６に図１と同じ雌ピン２が接続形成している。一
方、雄ピン１は、図１と同様に、半導体チップを構成す
るシリコン基板３０に形成されている。したがって両ピ
ンを相対的に矢印９の方向に近づけて雄ピン１を雌ピン
２内に挿入嵌合することにより半導体チップ３０と半導
体チップ９０とを接続する。FIG. 9 is a sectional view showing a fourth embodiment of the present invention. The same or similar components as those in FIG. 1 are denoted by the same reference numerals. The difference from FIG. 1 is that the female pins 2 are formed on the semiconductor chip similarly to the male pins 1 and connect the semiconductor chips to each other. That is, in this embodiment, a P + impurity region 92 is formed on an N-type silicon base 91 of a silicon substrate 90 constituting a semiconductor chip, and the contact pad 6 made of aluminum is formed in this region 92.
Has ohmic connection. The same female pin 2 as that of FIG. 1 is connected to the contact pad 6 exposed at the opening of the silicon oxide film 93 covering the entire substrate. On the other hand, the male pins 1 are formed on a silicon substrate 30 constituting a semiconductor chip, as in FIG. Therefore, the semiconductor chip 30 and the semiconductor chip 90 are connected by bringing both pins relatively close to each other in the direction of arrow 9 and inserting and fitting the male pin 1 into the female pin 2.

【００４１】以上の図１乃至図９の実施例では雄ピンの
中間部にくびれ構造を設け雌ピンの中間部に突起構造を
設けた例を述べたが、雌ピンの中間部にくびれ構造を設
け雄ピンの中間部に突起構造を設けてもよいことは言う
までもない。In the embodiments of FIGS. 1 to 9 described above, an example in which the constriction structure is provided in the middle portion of the male pin and the projection structure is provided in the middle portion of the female pin, but the constriction structure is provided in the middle portion of the female pin. It goes without saying that a projection structure may be provided in the middle of the provided male pin.

【００４２】[0042]

【発明の効果】雄ピンと雌ピンの嵌合を保持するくびれ
と突起の構造をそれぞれのピンの中間に設けることによ
って、くびれと突起部に働く上下方向の力に対する剛性
を増大させることができる。この結果、上下方向の力に
対してピンの変形が起こりにくくなるため、嵌合を保持
する力が大きくなった。By providing the structure of the constriction and the projection for holding the fitting of the male pin and the female pin between the respective pins, the rigidity against the vertical force acting on the constriction and the projection can be increased. As a result, the pin is less likely to be deformed by the force in the vertical direction, and the force for holding the fitting is increased.

【００４３】また、高密度実装ピンではピンの平面寸法
が小さく抑制され平面の接触面積が制限される。しかし
本発明ではピンの接触面積を、ピンの高さを高くして互
いのピンの側壁を接触させることにより大きくすること
ができる。これにより接続の配線抵抗が小さくなり、ま
た雄ピンと雌ピンの摩擦が増大するために接続がより機
械的に強固になる。In the case of high-density mounting pins, the plane dimensions of the pins are suppressed to be small, and the contact area of the plane is limited. However, in the present invention, the contact area of the pins can be increased by increasing the height of the pins and bringing the side walls of the pins into contact with each other. This reduces the wiring resistance of the connection and increases the friction between the male and female pins, making the connection more mechanically strong.

【００４４】さらに一方のピンの先端面が他方のコンタ
クトパッドに接触する面積に配線抵抗が依存しないか
ら、個々の配線抵抗のばらつきが小さいという利点もあ
る。Furthermore, since the wiring resistance does not depend on the area where the tip end surface of one pin contacts the other contact pad, there is an advantage that the variation in wiring resistance is small.

【００４５】高密度実装を実現させ接触抵抗を小にし強
固の接続となる本発明の上記ピン構造を得るために、高
アスペクト比（高さ／平面寸法）パターンを作製する本
発明の製造方法が好適である。すなわちシンクロトロン
から放射（ＳＲ）されるＸ線は直進するためにアスペク
ト比が１００以上のパターンを作製するのに利用でき
る。現在市販されているＸ線に強い感度をもつレジスト
（電子線レジストと同じもの）は、紫外線に対して非常
に低い感度をもっている。一方、紫外線レジストは、Ｘ
線に対しても大きな感度を有している。これらの性質を
利用して、雌ピンと雄ピンの本体をＸ線を利用したフォ
トリソグラフィ−により形成された高アスペクト比パタ
ーンから作製し、この中間部に突起あるいはくびれの構
造を紫外線レジストを利用したフォトリソグラフィ−か
ら作製する。中間部の突起あるいはくびれの構造を紫外
線レジストの中にパターニングするとき、Ｘ線レジスト
を通して（Ｘ線レジストには影響を与えることなく）行
うことができるために、作製方法が著しく簡略される。In order to obtain the above-mentioned pin structure of the present invention which realizes high-density mounting, reduces contact resistance, and provides a strong connection, the manufacturing method of the present invention for producing a high aspect ratio (height / planar dimension) pattern is as follows. It is suitable. That is, since the X-rays emitted from the synchrotron (SR) go straight, they can be used to form a pattern having an aspect ratio of 100 or more. Currently commercially available resists having a strong sensitivity to X-rays (the same as electron beam resists) have very low sensitivity to ultraviolet rays. On the other hand, UV resist
It also has great sensitivity to lines. Utilizing these properties, the main body of the female pin and the male pin is manufactured from a high aspect ratio pattern formed by photolithography using X-rays, and the structure of the projections or constrictions is formed by using an ultraviolet resist at the intermediate portion. It is manufactured by photolithography. When patterning the structure of the projections or constrictions in the intermediate portion in the ultraviolet resist, the patterning can be performed through the X-ray resist (without affecting the X-ray resist), so that the manufacturing method is significantly simplified.

【００４６】実施例の実装装置の全体を示す図１０にお
いて、シリコン基板３０の高密度にマトリックス状に配
置されたそれぞれのコンタクトパット上の雄ピン１とパ
ッケージ基板４０の高密度にマトリックス状に配置され
たそれぞれのコンタクトパット上の雌ピン２が嵌合した
コネクターピン構造１０により両コンタクトパットが電
気的接続をしている。ピンはＳＲから放射される直線性
の優れたＸ線を利用して作製されるために、著しく大き
なアスペクト比をもつ構造である。例えば、直径が２μ
ｍ、高さが５００μｍの高さをもったものが作製されて
おり、このとき、ピンのピッチｐは５μｍとなる。この
ように本発明では従来例に比べて面密度で１００倍程度
大きな密度をもった高密度実装が可能である。In FIG. 10 showing the entire mounting apparatus of the embodiment, the male pins 1 on each contact pad of the silicon substrate 30 arranged in a matrix in a high density and the package substrate 40 are arranged in a high density of a matrix. The contact pads are electrically connected by the connector pin structure 10 in which the female pins 2 on the respective contact pads are fitted. Since the pins are manufactured using X-rays having excellent linearity radiated from the SR, the pins have a significantly large aspect ratio. For example, if the diameter is 2μ
m and a height of 500 μm are manufactured. At this time, the pin pitch p is 5 μm. As described above, according to the present invention, high-density mounting with a density approximately 100 times larger in area density than the conventional example is possible.

【００４７】また、ピンの高さが５００μｍにすること
が可能であるから、シリコン基板３０とパッケージ基板
４０と間に大きな空間５０を設けることができる。した
がってこの空間に空気や水を流すことによって、大きな
冷却効率を実現した。このため本発明の実装装置はコン
ピュータのＣＰＵ等の発熱が大きなチップの実装に適し
たものである。Since the height of the pins can be set to 500 μm, a large space 50 can be provided between the silicon substrate 30 and the package substrate 40. Therefore, great cooling efficiency was realized by flowing air or water through this space. For this reason, the mounting apparatus of the present invention is suitable for mounting a chip such as a CPU of a computer that generates a large amount of heat.

【００４８】さらに本発明の製造方法では、ピン作製の
一連の工程においてポジ型あるいはネガ型の一方の型の
レジストのみを使用することができる。例えば図５の雄
ピンを作製するためにネガ型のレジスト５１，５２，５
３のみを用い、図６の雌ピンを作製するためにポジ型の
レジスト６１，６２，６３のみを用いる。すなわちピン
作製の一連の工程においてポジ型およびネガ型の両方の
型のレジストを使用していない。このために現像液が共
有できる等フォトリソグラフィ−工程を簡素化すること
ができる。さらにフォトリソグラフィ−が終了した後に
電気メッキを一度行うだけという単純なプロセスである
ために、作製工程が簡略化される。Further, in the manufacturing method of the present invention, only one of the positive type resist and the negative type resist can be used in a series of steps for producing pins. For example, in order to produce the male pin shown in FIG.
3, only positive resists 61, 62, 63 are used to produce the female pin of FIG. That is, both positive and negative resists are not used in a series of steps for producing pins. Therefore, the photolithography process can be simplified, for example, the developer can be shared. Further, since the process is a simple process of performing electroplating only once after the photolithography is completed, the manufacturing process is simplified.

【００４９】以上の効果は顕著なものであり、本発明は
非常に有効なものである。The above effects are remarkable, and the present invention is very effective.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例の実装装置を示す断面図
である。FIG. 1 is a sectional view showing a mounting device according to a first embodiment of the present invention.

【図２】図１の雄ピンと雌ピンとが嵌合した状態を示す
断面図である。FIG. 2 is a sectional view showing a state where the male pin and the female pin of FIG. 1 are fitted.

【図３】図１の実施例のうちの一例の形状を示す斜視図
である。FIG. 3 is a perspective view showing a shape of an example of the embodiment of FIG. 1;

【図４】図１の実施例のうちの他の例の形状を示す斜視
図である。FIG. 4 is a perspective view showing the shape of another example of the embodiment of FIG. 1;

【図５】図１の雄ピンを製造する方法の一実施例を示す
断面図である。FIG. 5 is a sectional view showing one embodiment of a method of manufacturing the male pin of FIG. 1;

【図６】図１の雌ピンを製造する方法の一実施例を示す
断面図である。FIG. 6 is a sectional view showing one embodiment of a method for manufacturing the female pin of FIG. 1;

【図７】本発明の第２の実施例の実装装置を示す断面図
である。FIG. 7 is a sectional view showing a mounting apparatus according to a second embodiment of the present invention.

【図８】本発明の第３の実施例の実装装置を示す断面図
である。FIG. 8 is a sectional view showing a mounting apparatus according to a third embodiment of the present invention.

【図９】本発明の第４の実施例の実装装置を示す断面図
である。FIG. 9 is a sectional view showing a mounting apparatus according to a fourth embodiment of the present invention.

【図１０】本発明の実施例の全体を模式的に示し、本発
明の効果の一部を説明するための図である。FIG. 10 is a diagram schematically illustrating the entire embodiment of the present invention and explaining a part of the effect of the present invention.

【図１１】従来技術の実装装置を示す断面図である。FIG. 11 is a cross-sectional view illustrating a conventional mounting apparatus.

【符号の説明】[Explanation of symbols]

１ 雄ピン ２ 雌ピン ３ 雄ピンのくびれ ４ 雌ピンの突起 ５ シリコン基板のコンタクトパッド ６ セラミック基板のコンタクトパッド ９ 挿入方向 １１ 雄ピンのメッキ部 １２，２２ 金属膜 １３ 雄ピンの側壁 １８ 雄ピンと雌ピン間の間隙 ２１ 雌ピンのメッキ部 ２３ 雌ピンの内側壁 ３０，９０ シリコン基板 ３１，９１ Ｎ型シリコン基体 ３２，９２ Ｐ+ 不純物領域 ３３ シリコン酸化膜 ４０ パッケージ基板 ４１ セラミック基体 ４３ コーティング絶縁膜 ５０ シリコン基板とパッケージ基板との間の間隙 ５１，５３ ネガ型のＸ線レジスト ５１Ｘ、５３Ｘ ネガ型のＸ線レジストがＸ線で感光
した部分 ５２ ネガ型の紫外線レジスト ５２Ｘ ネガ型の紫外線レジストがＸ線で感光した部
分 ５２Ｕ ネガ型の紫外線レジストが紫外線で感光した
部分 ５４ Ｘ線マスク ５４Ａ Ｘ線吸収体パターン ５５ 紫外線マスク ５５Ａ 紫外線吸収体パターン ５６ Ｘ線 ５７ 紫外線 ５９ 開口部 ６１，６３ ポジ型のＸ線レジスト ６１Ｘ、６３Ｘ ポジ型のＸ線レジストがＸ線で感光
した部分 ６２ ポジ型の紫外線レジスト ６２Ｘ ポジ型の紫外線レジストがＸ線で感光した部
分 ６２Ｕ ポジ型の紫外線レジストが紫外線で感光した
部分 ６４ Ｘ線マスク ６４Ａ Ｘ線吸収体パターン ６５ 紫外線マスク ６５Ａ 紫外線吸収体パターン ６９ 開口部 ７１，７２ 融点が低い金属膜 ８１ 雄ピンの先端の丸み ８２ 雌ピンの張出し部 ９１ 雄ピン ９２ 雌ピン ９３ 張出し部 ９４ 凹部 ９５，９６ コンタクトパッドReference Signs List 1 male pin 2 female pin 3 male pin constriction 4 female pin projection 5 silicon substrate contact pad 6 ceramic substrate contact pad 9 insertion direction 11 male pin plating 12,22 metal film 13 male pin side wall 18 male pin and Gap between female pins 21 plated part of female pin 23 inner wall of female pin 30, 90 silicon substrate 31, 91 N-type silicon substrate 32, 92 P + impurity region 33 silicon oxide film 40 package substrate 41 ceramic substrate 43 coating insulating film 50 Gap between silicon substrate and package substrate 51, 53 Negative type X-ray resist 51X, 53X Negative type X-ray resist exposed to X-ray 52 Negative type UV resist 52X Negative type UV resist X 52U negative type UV resist is exposed to ultraviolet rays Part 54 X-ray mask 54A X-ray absorber pattern 55 UV mask 55A UV absorber pattern 56 X-ray 57 UV 59 Opening 61, 63 Positive X-ray resist 61X, 63X Positive X-ray resist is exposed to X-ray 62 Positive UV resist 62X Positive UV resist exposed to X-rays 62U Positive UV resist exposed to UV radiation 64 X-ray mask 64A X-ray absorber pattern 65 UV mask 65A UV absorber Pattern 69 Opening 71,72 Metal film with low melting point 81 Roundness at the tip of male pin 82 Female pin overhang 91 Male pin 92 Female pin 93 Overhang 94 Recess 95,96 Contact pad

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−81264（ＪＰ，Ａ) 実開 平５−23452（ＪＰ，Ｕ) 実開 昭63−102178（ＪＰ，Ｕ) 電子部品ハンドブック、地人書館 （昭43−11−25） Ｐ．91 図２．７. ６ ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-81264 (JP, A) JP-A-5-23452 (JP, U) JP-A-63-102178 (JP, U) Electronic component handbook, ground Jinjinkan (Showa 43-11-25) 91 Figure 2.7.6

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１の基板のコンタクトパッド上に金属
メッキによって作製された雄ピンと第２の基板のコンタ
クトパッド上に金属メッキによって作製された雌ピンと
を嵌合して、前記雄ピンと前記雌ピンを互いの側壁で接
触させることにより電気的接続を行い、かつ前記雄ピン
と前記雌ピンが互いの側壁で接触する面積を、前記雄ピ
ンの先端と前記雌ピンに接続するコンタクトパッドに接
触する面積以上となるように前記雄ピンと前記雌ピンの
高さを高くした高密度実装装置の製造方法であって、Ｘ
線に感光する二層のネガ型レジストの間に紫外線に感光
するネガ型レジストを設けてＸ線と紫外線を順次照射し
た後現像し、メッキにより高さ方向の中間部に前記くび
れ構造を有する一方の雄ピンもしくは雌ピンを作製し、
Ｘ線に感光する二層のポジ型レジストの間に紫外線に感
光するポジ型レジストを設けてＸ線と紫外線を順次照射
した後現像し、メッキにより高さ方向の中間部に前記く
びれ構造と嵌合可能な突起構造を一体構造で設けた他方
の雌ピンもしくは雄ピンを作製することを特徴とする高
密度実装装置の製造方法。 1. A male pin formed by metal plating on a contact pad of a first substrate and a female pin formed by metal plating on a contact pad of a second substrate are fitted to each other, and the male pin and the female An electrical connection is made by contacting the pins at their side walls , and
The area of contact between the female pin and the
Contact the tip of the pin and the contact pad connected to the female pin.
The male pin and the female pin are
A method for manufacturing a high-density mounting apparatus having a height,
UV exposure between two layers of negative resist
X-rays and ultraviolet rays are sequentially irradiated by providing a negative resist
After developing, the above described wedge is applied to the middle part in the height direction by plating.
Make one male pin or female pin with the structure,
Sensitive to UV light between two layers of X-ray sensitive positive resist
Providing a positive resist that emits light and sequentially irradiating X-rays and ultraviolet rays
And then develop it.
The other is provided with a projection structure that can be fitted to the fin structure
Characterized by producing female or male pins
A method for manufacturing a density mounting device. 【請求項２】 前記くびれ構造もしくは前記突起構造が
設けられた前記雄ピンの外側および前記突起構造もしく
は前記くびれ構造が設けられた前記雌ピンの内側に、こ
れらピンを構成する主要材料より融点が低い金属膜を形
成し、前記嵌合後の前記金属膜の溶融により互いに接続
することを特徴とする請求項１記載の高密度実装装置の
製造方法。2. The melting point of the outer periphery of the male pin provided with the constricted structure or the protruding structure and the inner side of the female pin provided with the protruding structure or the constricted structure has a melting point higher than that of the main material constituting these pins. Shaped low metal film
And connected to each other by melting the metal films after the fitting.
High-density mounting apparatus according to claim 1, characterized in that
Manufacturing method . 【請求項３】 前記雄ピンは円柱状の形状であり、前記
雌ピンは円筒状の形状であることを特徴とする請求項１
又は請求項２記載の高密度実装装置の製造方法。3. The female pin according to claim 1, wherein said male pin has a cylindrical shape, and said female pin has a cylindrical shape.
A method for manufacturing a high-density mounting apparatus according to claim 2. 【請求項４】 前記雄ピンは基板の表面と平行方向の断
面が長方形の角柱形状であり、前記雌ピンは基板の表面
と平行方向の断面が長方形の一対の角柱形状であり、前
記雌ピンの一対の角柱形状間に前記雄ピンの角柱形状を
嵌合させて電気的接続を行うことを特徴とする請求項１
又は請求項２記載の高密度実装装置の製造方法。4. The male pin has a rectangular prism shape having a rectangular cross section in a direction parallel to the surface of the substrate, and the female pin has a pair of rectangular prism shapes having a rectangular cross section in a direction parallel to the surface of the substrate. 2. An electrical connection is made by fitting the male pin prism shape between the pair of prism shapes.
A method for manufacturing a high-density mounting apparatus according to claim 2. 【請求項５】 前記第１および第２の基板のうち一方の
基板は半導体チップを構成する半導体基板であり、他方
の基板は前記半導体チップを搭載するパッケージのパッ
ケージ基板であることを特徴とする請求項１から請求項
４のいずれかに記載の高密度実装装置の製造方法。5. The semiconductor device according to claim 1, wherein one of the first and second substrates is a semiconductor substrate forming a semiconductor chip, and the other substrate is a package substrate of a package on which the semiconductor chip is mounted. A method for manufacturing a high-density mounting device according to claim 1. 【請求項６】前記第１および第２の基板のそれぞれは半
導体チップを構成する半導体基板であることを特徴とす
る請求項１から請求項４のいずれかに記載の高密度実装
装置の製造方法。6. The method for manufacturing a high-density mounting apparatus according to claim 1, wherein each of said first and second substrates is a semiconductor substrate constituting a semiconductor chip. .
JP6089280A 1994-04-27 1994-04-27 Manufacturing method of mounting device Expired - Fee Related JP2798605B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6089280A JP2798605B2 (en) 1994-04-27 1994-04-27 Manufacturing method of mounting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6089280A JP2798605B2 (en) 1994-04-27 1994-04-27 Manufacturing method of mounting device

Publications (2)

Publication Number Publication Date
JPH07297197A JPH07297197A (en) 1995-11-10
JP2798605B2 true JP2798605B2 (en) 1998-09-17

Family

ID=13966312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6089280A Expired - Fee Related JP2798605B2 (en) 1994-04-27 1994-04-27 Manufacturing method of mounting device

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Country Link
JP (1) JP2798605B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4949279B2 (en) * 2008-01-21 2012-06-06 新光電気工業株式会社 Wiring board and manufacturing method thereof
JP5599328B2 (en) 2011-01-20 2014-10-01 三菱電機株式会社 Connection mechanism between power semiconductor device and printed wiring board
KR101221180B1 (en) * 2011-09-15 2013-01-21 한국과학기술원 Conductive bumps for connecting chips, manufacturing method for the same, and method for connecting chips using the same
JP7010001B2 (en) * 2018-01-08 2022-01-26 株式会社デンソー Electronic device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481264A (en) * 1987-09-22 1989-03-27 Fujitsu Ltd Semiconductor device
JPH0523452U (en) * 1991-08-30 1993-03-26 第一電子工業株式会社 Electrical connector

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
電子部品ハンドブック、地人書館 （昭４３−１１−２５） Ｐ．９１ 図２．７．６

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