JP2781689B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2781689B2 JP2781689B2 JP4008861A JP886192A JP2781689B2 JP 2781689 B2 JP2781689 B2 JP 2781689B2 JP 4008861 A JP4008861 A JP 4008861A JP 886192 A JP886192 A JP 886192A JP 2781689 B2 JP2781689 B2 JP 2781689B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- mold
- lower mold
- showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Injection Moulding Of Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体素子の樹脂封止方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for sealing a semiconductor element with a resin.
【０００２】[0002]
【従来の技術】従来の半導体素子の樹脂封止方法は、封
入金型の上金型と下金型との間に外部端子と金属細線に
て接続された半導体素子が接着されたリードフレームを
はさみ込み、樹脂を流し込み硬化される方式であった。
これを、図８の（ａ）乃至（ｆ）に示す。2. Description of the Related Art A conventional resin sealing method for a semiconductor element uses a lead frame in which an external terminal and a semiconductor element connected by a thin metal wire are bonded between an upper mold and a lower mold of an encapsulating mold. It was a method of sandwiching and pouring resin and curing.
This is shown in FIGS.
【０００３】図８の（ａ）において、従来では、アイラ
ンド４に固着された半導体素子片６があり、この素子片
６上のパッドと外部リード３０とを金属細線で接続して
おり、上下金型２０が用意される。金型２０内の空洞
は、外部リード３０の中間位置まで設けられ、樹脂Ｂ１
０の注入ゲート９が設けられている。In FIG. 8A, there is conventionally a semiconductor element piece 6 fixed to an island 4, and a pad on this element piece 6 and an external lead 30 are connected by a thin metal wire. A mold 20 is provided. The cavity in the mold 20 is provided up to an intermediate position of the external lead 30, and the resin B1
A zero injection gate 9 is provided.
【０００４】図８の（ｂ）〜（ｆ）は、このゲート９か
ら樹脂Ｂ１０が次第に注入されていく様子を順次示した
透視図である。（ｂ）〜（ｄ）において、素子片６の部
分の注入が遅れ、（ｅ）において、周囲まで樹脂Ｂ１０
で覆われるが、また素子片６の一部にゆきわたらず、
（ｆ）に示すように、ついにホール４０が形成されたま
まとなる。FIGS. 8B to 8F are perspective views sequentially showing a state in which the resin B10 is gradually injected from the gate 9. As shown in FIG. In (b) to (d), the injection of the portion of the element piece 6 is delayed, and in (e), the resin B10
, But does not spread to a part of the element piece 6,
Finally, as shown in (f), the hole 40 remains formed.
【０００５】[0005]
【発明が解決しようとする課題】このように従来の樹脂
封止方法では、パッケージ厚さが薄いもので、リードフ
レームアイランド４下面に樹脂を充分に充填することが
出来ずに、気泡（ホール）４０を発生させてしまうとい
った問題点があった。As described above, according to the conventional resin encapsulation method, the package thickness is small, and the resin cannot be sufficiently filled in the lower surface of the lead frame island 4, resulting in bubbles (holes). There is a problem that 40 is generated.
【０００６】本発明の目的は、前記問題点を解決し、ホ
ールが発生しないようにした半導体装置の製造方法を提
供することにある。It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above-mentioned problem and prevents generation of holes.
【０００７】[0007]
【課題を解決するための手段】本発明の構成は、上，下
金型で形成されるキャビティ内の下金型内に、固形の封
入樹脂を入れ加熱液化し、その後半導体素子を前記下金
型に乗せ、封入樹脂を圧入し、再び前記両封入樹脂を加
熱、硬化することを特徴とする。According to the present invention , a solid mold is provided in a lower mold in a cavity formed by an upper mold and a lower mold.
Inject resin and heat and liquefy, and then replace the semiconductor element with the lower metal
Put on the mold, press-fit the sealing resin, and add both of the sealing resins again.
It is characterized by heat and curing .
【０００８】[0008]
【実施例】図１乃至図７は本発明の一実施例の半導体装
置の製造方法を順に示した断面図である。1 to 7 are sectional views sequentially showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【０００９】まず図１において、本実施例では、封止金
型の下金型１に、固形の非可逆性熱硬化型樹脂Ａ２を入
れる。First, in FIG. 1, in this embodiment, a solid irreversible thermosetting resin A2 is put into a lower mold 1 of a sealing mold.
【００１０】次に図２において、下金型１は加熱されて
おり、キャビティ内に入れられた樹脂Ａ２は液化する。Next, in FIG. 2, the lower mold 1 is heated, and the resin A2 put in the cavity is liquefied.
【００１１】図３において、リードフレーム３のアイラ
ンド４上に、金属細線５で外部リードと電気的に接合さ
れた半導体素子片６を有するリードフレーム３を、下金
型１にのせる。In FIG. 3, a lead frame 3 having a semiconductor element piece 6 electrically connected to external leads by thin metal wires 5 is placed on a lower mold 1 on an island 4 of the lead frame 3.
【００１２】図４に示すように、そして上金型７を閉
じ、図５に示すように、キャビティ８へ、ゲート９より
封止樹脂Ｂ１０を圧入する。図６に示すように、圧入が
終了した時点で封止樹脂Ａ２，樹脂Ｂ１０を加熱、硬化
するのを待ち、図７に示すように、封止されたリードフ
レーム３とゲート９部の樹脂とを取り除く。かくして、
樹脂封止型の半導体装置が得られる。As shown in FIG. 4, the upper mold 7 is closed, and as shown in FIG. 5, a sealing resin B10 is pressed into the cavity 8 from the gate 9. As shown in FIG. 6, when the press-fitting is completed, the sealing resin A2 and the resin B10 are heated and cured, and as shown in FIG. 7, the sealed lead frame 3 and the resin of the gate 9 are removed. Get rid of. Thus,
A resin-sealed semiconductor device is obtained.
【００１３】[0013]
【発明の効果】以上説明したように、本発明の樹脂封止
方法は、あらかじめ気泡の出来やすいリードフレームア
イランド裏面部分のキャビティ内に樹脂を入れておくこ
とにより、気泡の発生を防止することができるという効
果がある。As described above, according to the resin sealing method of the present invention, it is possible to prevent bubbles from being generated by putting resin in the cavity on the back surface of the lead frame island where bubbles are easily formed. There is an effect that can be.
【図１】本発明の一実施例の半導体装置の製造方法の初
期の工程を示す断面図である。FIG. 1 is a cross-sectional view showing an initial step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.
【図２】図１の次工程を示す断面図である。FIG. 2 is a sectional view showing a step subsequent to FIG. 1;
【図３】図２の次工程を示す断面図である。FIG. 3 is a sectional view showing a step subsequent to FIG. 2;
【図４】図３の次工程を示す断面図である。FIG. 4 is a sectional view showing a step subsequent to FIG. 3;
【図５】図４の次工程を示す断面図である。FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
【図６】図５の次工程を示す断面図である。FIG. 6 is a sectional view showing a step subsequent to FIG. 5;
【図７】図６の次工程を示す断面図である。FIG. 7 is a sectional view showing a step subsequent to FIG. 6;
【図８】（ａ）乃至（ｆ）は従来の半導体装置の製造方
法を工程順に示した透視図である。8A to 8F are perspective views showing a conventional method of manufacturing a semiconductor device in the order of steps.
１ 下金型 ２ 樹脂Ａ ３ リードフレーム ４ アイランド ５ 金属細線 ６ 半導体素子片 ７ 上金型 ８ キャビティ ９ ゲート １０ 樹脂Ｂ ２０ 上下金型 ３０ 外部リード ４０ ホール REFERENCE SIGNS LIST 1 Lower mold 2 Resin A 3 Lead frame 4 Island 5 Fine metal wire 6 Semiconductor element piece 7 Upper mold 8 Cavity 9 Gate 10 Resin B 20 Upper and lower mold 30 External lead 40 Hole
Claims (1)
下金型内に、固形の封入樹脂を入れ加熱液化し、その後
半導体素子を前記下金型に乗せ、封入樹脂を圧入し、再
び前記両封入樹脂を加熱、硬化することを特徴とする半
導体装置の製造方法。1. A top, in the cavity formed by the lower mold
Put the solid encapsulation resin in the lower mold and liquefy it by heating.
Place the semiconductor element on the lower mold, press-fit the sealing resin,
And a method of manufacturing the semiconductor device, wherein the resin is heated and cured .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008861A JP2781689B2 (en) | 1992-01-22 | 1992-01-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008861A JP2781689B2 (en) | 1992-01-22 | 1992-01-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05198707A JPH05198707A (en) | 1993-08-06 |
| JP2781689B2 true JP2781689B2 (en) | 1998-07-30 |
Family
ID=11704487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4008861A Expired - Fee Related JP2781689B2 (en) | 1992-01-22 | 1992-01-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2781689B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1318257B1 (en) * | 2000-07-27 | 2003-07-28 | St Microelectronics Srl | LEAD-FRAME FOR SEMICONDUCTOR DEVICES. |
| JP4519398B2 (en) * | 2002-11-26 | 2010-08-04 | Ｔｏｗａ株式会社 | Resin sealing method and semiconductor device manufacturing method |
| JP5308108B2 (en) * | 2008-09-11 | 2013-10-09 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Circuit device manufacturing method |
| JP5308107B2 (en) * | 2008-09-11 | 2013-10-09 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Circuit device manufacturing method |
| US20130037931A1 (en) * | 2011-08-08 | 2013-02-14 | Leo M. Higgins, III | Semiconductor package with a heat spreader and method of making |
| CN106463417A (en) * | 2014-05-14 | 2017-02-22 | 三菱电机株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58138039A (en) * | 1982-02-10 | 1983-08-16 | Nec Home Electronics Ltd | Manufacture of resin sealed type semiconductor device |
| JPH05102216A (en) * | 1991-10-09 | 1993-04-23 | Hitachi Ltd | Semiconductor device |
-
1992
- 1992-01-22 JP JP4008861A patent/JP2781689B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05198707A (en) | 1993-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980414 |
|
| LAPS | Cancellation because of no payment of annual fees |