JP2715579B2 - Manufacturing method of copper wiring ceramic substrate - Google Patents
Manufacturing method of copper wiring ceramic substrateInfo
- Publication number
- JP2715579B2 JP2715579B2 JP19567189A JP19567189A JP2715579B2 JP 2715579 B2 JP2715579 B2 JP 2715579B2 JP 19567189 A JP19567189 A JP 19567189A JP 19567189 A JP19567189 A JP 19567189A JP 2715579 B2 JP2715579 B2 JP 2715579B2
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- Japan
- Prior art keywords
- copper
- plating
- layer
- ceramic substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Physical Vapour Deposition (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Electroplating Methods And Accessories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は銅配線基板、特に最終的に電気めっきにより
他の金属のめっきを施した銅配線セラミック基板の製造
方法に関する。The present invention relates to a method for manufacturing a copper wiring board, and more particularly to a method for manufacturing a copper wiring ceramic board finally plated with another metal by electroplating.
高密度実装が可能なICパッケージとして、PGA（ピン
グリッドアレイ）基板がある。高信頼性を必要とする用
途のPGA基板には、セラミックを基板とし配線層がアル
ミニウムのものが多く用いられていた。しかし最近、電
子回路の高速化に対応するため、アルミニウムの代わり
電気抵抗の小さい銅が用いられるようになった。銅は高
温では勿論常温でも酸化しやすく、そのままではワイヤ
ボンディングに適しないため、銅配線層にはニッケル等
の銅以外の金属の被膜、またはニッケル等を下地として
金等の貴金属の被膜を、電気めっき法により施す。As an IC package capable of high-density mounting, there is a PGA (pin grid array) substrate. As a PGA substrate for applications requiring high reliability, a ceramic substrate and an aluminum wiring layer were often used. However, recently, in order to cope with high-speed electronic circuits, copper having a small electric resistance has been used instead of aluminum. Copper is easily oxidized at high temperature as well as at normal temperature, and is not suitable for wire bonding as it is.Therefore, the copper wiring layer is coated with a coating of a metal other than copper such as nickel or a coating of a noble metal such as gold with nickel or the like as an underlayer. Apply by plating method.
例えば第２図に示すように、セラミック基板１の上に
蒸着法によりクロム蒸着層２、銅蒸着層３を設け、導電
層を形成し、フォトエッチングにより回路パターンを形
成（パターニングと呼ばれる）した後、ニッケルめっき
層５、金めっき層６が順次形成される。For example, as shown in FIG. 2, after a chromium vapor deposition layer 2 and a copper vapor deposition layer 3 are provided on a ceramic substrate 1 by a vapor deposition method, a conductive layer is formed, and a circuit pattern is formed by photoetching (referred to as patterning). , A nickel plating layer 5 and a gold plating layer 6 are sequentially formed.
セラミック基板１の上に蒸着法により形成した銅導電
層３に、フォトエッチングにより回路パターンを形成
（パターニングと呼ばれる）した後、ニッケル等の銅以
外の金属の被膜５を電気めっき法により施す際に、ニッ
ケル等のめっき層５が第３図に示すように局部的に、ホ
イスカー状、または水平方向にひれ状に、異常成長する
ことがしばしばあり（第３図で5aは異常成長部）、甚だ
しい場合には本来電気的に独立でなければならないリー
ド部８同士が短絡したり、短絡寸前の状態になる。具体
例を述べると、平均めっき厚さが１μｍの場合に異常成
長の長さが10μｍ以上、場合により40μｍにも及ぶ（こ
れは、異常成長部分では平均めっき速度の10ないし40倍
にも及ぶ速度で電析が起きていることを意味する）。ニ
ッケル等を下地としてさらに金等の貴金属の被膜６を形
成する場合も、下地のめっきの局部的な異常成長で同様
の障害が生ずる。このようなめっき部の異常成長によっ
て、製造された銅配線基板の信頼性あるいは歩留まりが
甚だしく損なわれる。まためっき速度も制限され、さら
に微細なパターンの配線層の製造が難しい。When a circuit pattern is formed by photo-etching on a copper conductive layer 3 formed on a ceramic substrate 1 by vapor deposition (referred to as patterning), a coating 5 of a metal other than copper such as nickel is applied by electroplating. , Nickel or the like often grows locally, as shown in FIG. 3, in a whisker-like manner or in a horizontal fin-like manner (in FIG. 3, 5a is an abnormally grown portion). In this case, the lead portions 8, which should be electrically independent from each other, are short-circuited or shortly before a short-circuit occurs. Specifically, when the average plating thickness is 1 μm, the length of the abnormal growth is 10 μm or more, and sometimes as much as 40 μm. Means that electrodeposition is occurring). In the case where a coating 6 of a noble metal such as gold is further formed using nickel or the like as a base, a similar obstacle occurs due to local abnormal growth of plating of the base. Due to such abnormal growth of the plated portion, the reliability or the yield of the manufactured copper wiring board is significantly impaired. In addition, the plating rate is limited, and it is difficult to manufacture a wiring layer having a finer pattern.
それ故本発明の目的は、蒸着法により形成した銅電導
層に回路パターン形成後、電気めっき法によるニッケル
等銅以外の金属の被膜を形成する際に生ずるめっき部の
局部的な異常成長を防止した、信頼性あるいは歩留まり
の高い銅配線セラミック基板の製造方法を提供すること
である。Therefore, an object of the present invention is to prevent local abnormal growth of a plated portion which occurs when a film of a metal other than copper such as nickel is formed by electroplating after forming a circuit pattern on a copper conductive layer formed by vapor deposition. It is another object of the present invention to provide a method for manufacturing a copper wiring ceramic substrate having high reliability or high yield.
本発明の他の目的は、めっき速度を高めることがで
き、従って製造に要する時間の短縮が可能であり、また
微細な配線パターンが得られる銅配線セラミック基板の
製造方法を提供することである。Another object of the present invention is to provide a method of manufacturing a copper wiring ceramic substrate which can increase the plating speed, and thus can reduce the time required for manufacturing, and can obtain a fine wiring pattern.
本発明では上記目的を達成するために、銅蒸着層を形
成する際に、蒸着源として99.999％以上の純度の銅に４
ないし30ppmの希土類元素を添加した合金を用いるよう
にした。In the present invention, in order to achieve the above object, when forming a copper vapor deposition layer, copper having a purity of 99.999% or more is used as a vapor deposition source.
An alloy containing 30 ppm or less of a rare earth element was used.
本発明における銅蒸着層には、真空蒸着法のほかイオ
ンプレーティング，クラスタイオンビーム法，スパッタ
リング法等の物理的蒸着法（PVD）により形成された銅
層を包含する。The copper vapor deposition layer in the present invention includes a copper layer formed by a physical vapor deposition method (PVD) such as ion plating, cluster ion beam method, and sputtering method in addition to the vacuum vapor deposition method.
本発明の方法は下記工程から成る。 The method of the present invention comprises the following steps.
（１）セラミック基板に銅層を蒸着する工程 基板として用いるセラミックは、アルミナ、ムライ
ト、マグネシア、窒化アルミニウム、ジルコニア，炭化
珪素等のいずれでもよい。(1) Step of Depositing Copper Layer on Ceramic Substrate The ceramic used as the substrate may be any of alumina, mullite, magnesia, aluminum nitride, zirconia, silicon carbide and the like.
本発明は金属基板、プラスチック基板、ガラスエポキ
シ基板にも適用できるが、セラミック基板は他に比して
表面が粗いので、とくに効果が顕著である。The present invention can be applied to a metal substrate, a plastic substrate, and a glass epoxy substrate. However, since the surface of a ceramic substrate is rougher than other substrates, the effect is particularly remarkable.
本発明は蒸着源として99.999％以上の純度の銅に４な
いし30ppmの希土類元素を添加した合金を用いることを
特徴とする。好ましくは99.9995％以上の純度の銅を用
いる。純度99.999％未満の銅を用いると、ニッケルめっ
き等の際に前記のようなホイスカ状またはひれ状の異常
な成長が起きる。純度99.999％以上であれば、希土類元
素を添加しなくともホイスカ状の成長は皆無に近いが、
ひれ状の成長がなお若干認められる。希土類元素を4ppm
ないし30ppm添加すると、ひれ状の成長も抑制される。3
0ppmを超える希土類元素を添加すると、配線膜の硬度が
増してワイヤボンディング性が悪くなるので、望ましく
ない。The present invention is characterized in that an alloy obtained by adding 4 to 30 ppm of a rare earth element to copper having a purity of 99.999% or more is used as a vapor deposition source. Preferably, copper having a purity of 99.9995% or more is used. When copper having a purity of less than 99.999% is used, whisker-like or fin-like abnormal growth occurs during nickel plating or the like. If the purity is 99.999% or more, whisker-like growth is almost nil even without adding rare earth elements,
Some fin-like growth is still observed. 4ppm rare earth element
Addition of 30 ppm or less also suppresses fin-like growth. Three
If a rare earth element exceeding 0 ppm is added, the hardness of the wiring film increases and the wire bonding property deteriorates, which is not desirable.
希土類元素は13種の元素のいずれでもよいが、中でも
セリウム、ランタン、ネオジムは特に酸素、炭素、水素
との親和力が強く、また溶融後の蒸気圧が小さいため蒸
着膜に混入しにくいので、有利である。The rare earth element may be any of the 13 kinds of elements. Among them, cerium, lanthanum, and neodymium are particularly advantageous because they have a strong affinity for oxygen, carbon, and hydrogen, and have a low vapor pressure after melting, so that they are hardly mixed into the deposited film. It is.
銅を蒸着する前にセラミック基板上に予め下地として
銅以外の金属の層，例えばアルミニウム、チタン、ジル
コニウム、クロム、モリブデン、タングステン、ニッケ
ル等の１種または２種以上を蒸着により形成させてもよ
い。Before depositing copper, a layer of a metal other than copper, for example, one or more of aluminum, titanium, zirconium, chromium, molybdenum, tungsten, nickel, etc. may be formed on the ceramic substrate by vapor deposition in advance. .
蒸着する厚さは普通１μｍから20μｍ程度であり、３
μｍから10μｍとすることが多い。The thickness to be deposited is usually about 1 μm to 20 μm.
It is often from 10 μm to 10 μm.
（２）フォトエッチングによる回路パターン形成 上記工程（１）で得られた銅蒸着層に、通常のフォト
エッチングの方法により回路パターンを形成させる。(2) Circuit pattern formation by photoetching A circuit pattern is formed on the copper vapor deposition layer obtained in the above step (1) by a normal photoetching method.
（３）銅配線層の上に銅以外の金属をめっきする工程 上記工程（２）で得られた銅配線層に、電気めっき法
によりニッケル等の銅以外のめっき、またはニッケル等
を下地とする金めっきを施す。めっきのために用いる金
属はニッケル、コバルト、クロム、モリブデン、タング
ステン等から選ぶことができるが、ニッケル、コバル
ト、クロムのようにめっき時に樹枝状成長を生じ易い金
属の場合本発明の効果が顕著である。(3) Step of plating a metal other than copper on the copper wiring layer The copper wiring layer obtained in the above step (2) is plated with a material other than copper, such as nickel, or nickel, by electroplating. Apply gold plating. The metal used for plating can be selected from nickel, cobalt, chromium, molybdenum, tungsten, etc. is there.
必要に応じ、上記の銅以外の金属のめっきの上に別の
金属、特に金、銀等の貴金属をさらにめっきしてもよ
い。If necessary, another metal, particularly a noble metal such as gold or silver, may be further plated on the plating of a metal other than copper.
めっきの方法、条件等に特に制限はなく、通常の通り
でよい。ニッケル等の銅以外の金属のめっきの厚さは0.
1ないし５μｍ程度、ニッケル等を下地としてめっきし
た上に施す金等のめっきの厚さは0.1ないし２μｍ程度
である。The plating method and conditions are not particularly limited, and may be as usual. The plating thickness of metals other than copper such as nickel is 0.
The thickness of the plating of gold or the like is about 1 to 5 μm after plating with nickel or the like as a base, and is about 0.1 to 2 μm.
本発明において、蒸着に高純度の銅にごく少量の希土
類元素を添加したものを用いるとその後のめっき工程で
のめっき層の異常成長が生じないのは、希土類元素が銅
中の酸素、炭素、水素等を捕捉してこれらの蒸着膜中へ
の混入を防止するため、不純物の少ない銅蒸着層が形成
され、従ってエッチングの際に銅蒸着層の表面の結晶粒
子の欠落が生ぜず、表面の凹凸が少ないため、めっきの
際の電流分布が比較的均一になるためと推定される。In the present invention, when using a high-purity copper to which a very small amount of rare earth element is added for vapor deposition, abnormal growth of the plating layer does not occur in the subsequent plating step, because the rare earth element is oxygen, carbon, In order to prevent hydrogen and the like from being mixed into the deposited film, a copper deposited layer with a small amount of impurities is formed.Therefore, no crystal particles are lost on the surface of the copper deposited layer during etching, and the surface of the copper deposited layer is not generated. It is presumed that the current distribution during plating is relatively uniform because there are few irregularities.
以下、実施例により本発明をさらに詳細に説明する。 Hereinafter, the present invention will be described in more detail with reference to examples.
第１図に示すように、アルミナ基板１の上に蒸着法に
よりクロム蒸着層２、銅蒸着層３から成る導電層を形成
し、フォトエッチングにより回路パターンを形成した
後、電気めっきによりニッケルめっき層５、金めっき層
６を形成した。詳細は下記の通りである。As shown in FIG. 1, a conductive layer composed of a chromium vapor deposition layer 2 and a copper vapor deposition layer 3 is formed on a alumina substrate 1 by vapor deposition, a circuit pattern is formed by photoetching, and a nickel plating layer is formed by electroplating. 5. A gold plating layer 6 was formed. Details are as follows.
厚さ2mmのアルミナ基板上に、チタンを厚さ0.03μｍ
に真空蒸着後、第１表に示すように異なる５種の銅蒸着
材料を、基板温度300℃、真空度２×10-6Torrで、厚さ
５μｍに真空蒸着後、通常のフォトエッチング法により
過硫酸アンモニウムと塩化アンモニウム溶液を用いて金
属層（銅／チタン層）をエッチし、線幅20μｍ、線間20
μｍ、長さ5mmの直線状の配線パターン（リード部）100
0本を互いに平行に形成した。こうして得られたアルミ
ナ基板上に銅配線パターンに、通常の電気めっき法によ
りニッケルを0.5μｍの厚さに下地めっきした後、金を
0.5μｍの厚さに電気めっきした。めっき条件は、ニッ
ケルめっきについては標準ワット浴を用い、温度60℃、
電流密度2.0A/dm2とし、金めっきについてはシアン化金
カリウム浴を用い、温度50℃、電流密度0.5A/dm2とし
た。なお第１図で４は蒸着層を、７はめっき層を示す。Titanium 0.03μm thick on 2mm thick alumina substrate
After vacuum evaporation, as shown in Table 1, five different copper evaporation materials were vacuum-evaporated to a thickness of 5 μm at a substrate temperature of 300 ° C. and a degree of vacuum of 2 × 10 −6 Torr, and then subjected to ordinary photoetching. Etch the metal layer (copper / titanium layer) with ammonium persulfate and ammonium chloride solution, line width 20 μm, line spacing 20
μm, 5mm long linear wiring pattern (lead part) 100
0 were formed in parallel with each other. On the alumina substrate thus obtained, a copper wiring pattern was plated with nickel to a thickness of 0.5 μm by a normal electroplating method, and then gold was plated.
It was electroplated to a thickness of 0.5 μm. The plating conditions were as follows: nickel plating using a standard watt bath, temperature 60 ° C,
The current density was 2.0 A / dm 2, and gold plating was performed using a potassium potassium cyanide bath at a temperature of 50 ° C. and a current density of 0.5 A / dm 2 . In FIG. 1, reference numeral 4 denotes an evaporation layer, and reference numeral 7 denotes a plating layer.
ニッケルめっき終了時および金めっきまで終了した配
線パターンの表面を観察した。その結果を第１表に示
す。第１表中セリウム添加量ゼロの欄は本発明の範囲外
の比較例に相当する。第１表で異常成長発生率は、リー
ド部1000本について異常成長が発生した本数の百分率を
示す。また蒸着膜のビッカース硬度を測定し、金めっき
終了後の配線層のワイヤボンディング適性を評価した。
第１表で蒸着膜硬さは蒸着膜のビッカース硬度を示す。At the end of nickel plating and the surface of the wiring pattern completed up to gold plating were observed. Table 1 shows the results. The column of zero cerium addition in Table 1 corresponds to comparative examples outside the scope of the present invention. In Table 1, the abnormal growth occurrence rate indicates the percentage of the number of abnormal growths occurring in 1000 lead portions. The Vickers hardness of the deposited film was measured, and the suitability for wire bonding of the wiring layer after the completion of the gold plating was evaluated.
In Table 1, the deposited film hardness indicates the Vickers hardness of the deposited film.
第１表から明らかなように、本発明に従い純度99.999
％の銅に7ppmまた30ppmのセリウムを添加して蒸着した
場合には、ホイスカ状の異常成長もひれ状の成長も全く
生じない。これに対し、純度99.999％の銅にセリウムを
添加しないで蒸着した場合には、ホイスカ状の異常成長
はごく僅かであるが、ひれ状成長がいくらか見られ、2p
pmのセリウムを添加して蒸着した場合には、ホイスカ状
の異常成長は皆無となるが、ひれ状成長がなお僅かに見
られた。 As is evident from Table 1, the purity according to the invention is 99.999.
When 7 ppm or 30 ppm of cerium is added to% copper and deposited, neither whisker-like abnormal growth nor fin-like growth occurs. In contrast, when copper was deposited without adding cerium to 99.999% pure copper, abnormal whisker-like growth was very slight, but some fin-like growth was observed.
When vapor deposition was performed with cerium at pm, abnormal whisker-like growth was absent, but fin-like growth was still slightly observed.
他方、55ppmのセリウムを添加した場合には導電層の
硬度が増し、ワイヤボンディング性が若干悪くなった。On the other hand, when 55 ppm of cerium was added, the hardness of the conductive layer was increased, and the wire bonding property was slightly deteriorated.
本発明の方法によると、セラミック基板上に蒸着法に
より形成した銅導電層に、フォトエッチングにより回路
パターンを形成した後、電気めっき法によりニッケル等
の銅以外の金属のめっきを施す際に、めっき層が局部的
にホイスカ状に、または水平方向にひれ状に、異常成長
する現象が生じなくなり、電気的に独立でなければなら
ないリード同士の短絡または短絡寸前の状態になること
が防がれる。本発明の方法は特にセラミック基板上に銅
導電層を蒸着する場合に有効である。According to the method of the present invention, after forming a circuit pattern by photoetching on a copper conductive layer formed on a ceramic substrate by an evaporation method, when plating a metal other than copper such as nickel by electroplating, The phenomenon of abnormal growth of the layer in the form of local whiskers or fins in the horizontal direction does not occur, and a short-circuit or a short-circuit state between leads that must be electrically independent is prevented. The method of the present invention is particularly effective when depositing a copper conductive layer on a ceramic substrate.
本発明の方法によると、セラミック基板上に蒸着した
銅配線層に、前記のようなめっき層の異常成長を生ずる
ことなくニッケル等の銅以外の金属をめっきすることが
可能になるから、導電層に電気抵抗の小さい銅をワイヤ
ボンディングに適するセラミック配線基板を作ることが
でき、電子回路の高速化に対応することができる。本発
明の方法は、例えばPGA（ピングリッドアレイ）の製造
に適用できる。According to the method of the present invention, a copper wiring layer deposited on a ceramic substrate can be plated with a metal other than copper such as nickel without causing abnormal growth of the plating layer as described above. In addition, a ceramic wiring board suitable for wire bonding with copper having a small electric resistance can be manufactured, and it is possible to cope with an increase in the speed of an electronic circuit. The method of the present invention can be applied, for example, to the manufacture of a PGA (pin grid array).
本発明の方法によると、銅導電層に銅以外の金属のめ
っきを施す際に異常成長がないだけでなく、メッキ後の
回路パターンのエッジの凹凸が少なくなり、鮮鋭な回路
パターンが得られる。その結果パターンを微細にするこ
とも可能となる。According to the method of the present invention, not only abnormal growth does not occur when plating a metal other than copper on the copper conductive layer, but also the edge of the circuit pattern after plating is reduced and a sharp circuit pattern is obtained. As a result, the pattern can be made finer.
希土類元素を加えずに単に蒸着する銅の純度を99.999
％より高くすることによっても本発明の方法と類似の効
果が得られるが、原材料の精製のために多大の費用を要
する。本発明の方法によると、銅の純度をさらに純度を
高める必要がないので、原料精製のためのコストを節約
できる。99.999 pure copper that is simply deposited without adding rare earth elements
%, A similar effect to the method of the present invention can be obtained, but at the expense of purification of the raw materials. According to the method of the present invention, it is not necessary to further increase the purity of copper, so that the cost for raw material purification can be saved.
希土類元素の量をさらに増せば銅の純度が99.999％よ
り低くても、めっき層の異常成長を防止できるが、高価
な希土類元素を多量に使用するので、原材料のコストが
増大する。If the amount of the rare earth element is further increased, even if the purity of copper is lower than 99.999%, abnormal growth of the plating layer can be prevented. However, the use of a large amount of the expensive rare earth element increases the cost of raw materials.
本発明の方法によると、銅導電層に銅以外の金属のめ
っきを施す際にめっき速度を上昇しても異常成長が生じ
ないので、めっきに要する時間を短縮でき、生産効率を
高め、製造コストを低下させることができる。According to the method of the present invention, when plating a metal other than copper on the copper conductive layer, abnormal growth does not occur even if the plating rate is increased, so that the time required for plating can be reduced, the production efficiency can be increased, and the production cost can be increased. Can be reduced.
本発明の方法はセラミック基板上に銅を直接蒸着する
場合のみならず、セラミック基板上に蒸着等により設け
た他の金属の下地層を介して銅を蒸着する場合にも、有
用である。The method of the present invention is useful not only for directly depositing copper on a ceramic substrate, but also for depositing copper via another metal base layer provided on a ceramic substrate by deposition or the like.
また本発明の方法は、回路パターンを形成した銅導電
層にニッケル等の銅以内の金属のめっきを施した後、こ
の層を下地としてさらに金、銀等の貴金属をめっきする
場合にも、有用である。The method of the present invention is also useful when plating a metal within copper such as nickel on a copper conductive layer on which a circuit pattern is formed, and further plating a noble metal such as gold or silver using this layer as a base. It is.
第１図は実施例で得られたセラミック基板上の配線層の
拡大断面図、第２図はめっき層の異常成長の部分におけ
るセラミック基板上の配線層の拡大断面図、第３図はセ
ラミック基板上の蒸着銅配線層にニッケル等を電気めっ
きした際に生ずるホイスカ状及びひれ状の異常成長の状
態を示す説明図である。 符号の説明 １……セラミック基板、２……クロム蒸着層 ３……銅蒸着層、４……蒸着層 ５……ニッケルめっき層 5a……ニッケルめっき層の異常成長部 ６……金めっき層、７……めっき層 ８……配線層FIG. 1 is an enlarged cross-sectional view of a wiring layer on a ceramic substrate obtained in an embodiment, FIG. 2 is an enlarged cross-sectional view of a wiring layer on a ceramic substrate in a portion where a plating layer is abnormally grown, and FIG. It is explanatory drawing which shows the state of whisker-like and fin-like abnormal growth which arises when electroplating nickel etc. on the vapor deposition copper wiring layer above. DESCRIPTION OF SYMBOLS 1 ... ceramic substrate 2 ... chromium vapor deposition layer 3 ... copper vapor deposition layer 4 ... vapor deposition layer 5 ... nickel plating layer 5 a ... abnormal growth portion of nickel plating layer 6 ... gold plating layer 7: plating layer 8: wiring layer
Claims (2)
層を形成し、該銅導電層に回路パターン形成後、電気め
っき法により銅以外の金属のめっきまたは該金属を下地
とする貴金属めっきを施す銅配線セラミック基板の製造
方法において、銅蒸着層を形成するための蒸着源として
99.999％以上の純度の銅に４ないし30ppmの希土類元素
を添加して成る合金を用いることを特徴とする銅配線セ
ラミック基板の製造方法。A copper conductive layer is formed on a ceramic substrate by a vapor deposition method, and after forming a circuit pattern on the copper conductive layer, plating of a metal other than copper or precious metal plating based on the metal is performed by an electroplating method. In the method of manufacturing a copper wiring ceramic substrate to be applied, as a deposition source for forming a copper deposition layer
A method for manufacturing a copper wiring ceramic substrate, comprising using an alloy obtained by adding 4 to 30 ppm of a rare earth element to copper having a purity of 99.999% or more.
クロムのうちから選ばれる請求項第１項の銅配線セラミ
ック基板の製造方法。2. The metal other than copper is nickel, cobalt,
2. The method according to claim 1, wherein the copper wiring ceramic substrate is selected from chromium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19567189A JP2715579B2 (en) | 1989-07-28 | 1989-07-28 | Manufacturing method of copper wiring ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19567189A JP2715579B2 (en) | 1989-07-28 | 1989-07-28 | Manufacturing method of copper wiring ceramic substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0360185A JPH0360185A (en) | 1991-03-15 |
| JP2715579B2 true JP2715579B2 (en) | 1998-02-18 |
Family
ID=16345063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19567189A Expired - Fee Related JP2715579B2 (en) | 1989-07-28 | 1989-07-28 | Manufacturing method of copper wiring ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2715579B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140041817A (en) * | 2011-08-12 | 2014-04-04 | 미쓰비시 마테리알 가부시키가이샤 | Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5699853B2 (en) * | 2011-08-12 | 2015-04-15 | 三菱マテリアル株式会社 | Power module substrate, power module substrate with heat sink, power module, and method for manufacturing power module substrate |
| JP5765131B2 (en) * | 2011-08-12 | 2015-08-19 | 三菱マテリアル株式会社 | Power module substrate, power module substrate with heat sink, power module, and method for manufacturing power module substrate |
-
1989
- 1989-07-28 JP JP19567189A patent/JP2715579B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140041817A (en) * | 2011-08-12 | 2014-04-04 | 미쓰비시 마테리알 가부시키가이샤 | Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module |
| KR101586157B1 (en) * | 2011-08-12 | 2016-01-15 | 미쓰비시 마테리알 가부시키가이샤 | Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0360185A (en) | 1991-03-15 |
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