JP2707568B2 - Wiring processing method - Google Patents
Wiring processing methodInfo
- Publication number
- JP2707568B2 JP2707568B2 JP63000714A JP71488A JP2707568B2 JP 2707568 B2 JP2707568 B2 JP 2707568B2 JP 63000714 A JP63000714 A JP 63000714A JP 71488 A JP71488 A JP 71488A JP 2707568 B2 JP2707568 B2 JP 2707568B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- grid
- prohibition
- line width
- net
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はLBIまたはプリント配線基板（PWB）の配線設
計を行うための配線処理方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring processing method for designing wiring of an LBI or a printed wiring board (PWB).
近年のLSI,PWB等の高密度化，動作の高速化に伴い、
これらの配線パターンの線幅の微細化が進んでいる。し
かしながら、上述のような微細化により配線の抵抗が増
大してしまうので、高速動作を保持するために供給電力
を上げる必要が生じてくる。供給電力を上げる場合に
は、冷却等の問題が発生する。このため供給電極を上げ
ない他の方法としては、配線を部分的に線幅を変えて配
線抵抗を操作することが研究されている。With the recent increase in the density and operation speed of LSIs and PWBs,
The line width of these wiring patterns has been miniaturized. However, since the resistance of the wiring increases due to the miniaturization as described above, it becomes necessary to increase the supply power to maintain the high-speed operation. When increasing the power supply, problems such as cooling occur. For this reason, as another method of not raising the supply electrode, research has been made on operating the wiring resistance by partially changing the line width of the wiring.
従来、複数の線幅を有する配線処理の方式として線幅
毎に配線端子を結線するネツトを分類し、配線を行う際
の座標となる配線格子の大きさ等の切換えを行いながら
段階的に配線を行つていた。参考文献としては次のもの
がある。「論理装置のCAD」（情報処理学会誌 昭和56
年３月20日発行）なお、太幅の配線については予め人手
により配線パターンを作成していた。Conventionally, as a wiring processing method having a plurality of line widths, nets for connecting wiring terminals are classified for each line width, and wiring is performed stepwise while switching the size of a wiring grid, which is a coordinate at the time of wiring. Had gone. References include the following: "CAD for logic devices" (Showa 56, IPSJ Journal)
(Published March 20, 2008) Note that wiring patterns for thick wiring were manually created in advance.
しかしながら上述したような従来の方式では、線幅が
異なるときには線幅の異なる配線格子を選択する等の条
件設定を変える必要があるので多大な処理時間を要する
という問題があつた。また、線幅毎に段階的に配線を行
うために、同一線幅のネツトのみの配線順序しか変更操
作ができず、全ネツトを対象とした配線順序の最適化を
図ることも困難であり、さらに人手による配線パターン
の作成に多大な工数を要し、誤配線等の生じる可能性も
高いという問題があつた。However, the conventional method as described above has a problem that when the line width is different, it is necessary to change a condition setting such as selecting a wiring grid having a different line width, so that a large processing time is required. In addition, since wiring is performed step by step for each line width, only the wiring order of nets having the same line width can be changed, and it is difficult to optimize the wiring order for all nets. Further, there is a problem that a great deal of man-hour is required for manually creating the wiring pattern, and there is a high possibility that erroneous wiring or the like occurs.
本発明は、結線対象のネツトを抽出し、そのネツトを
基準線幅で結線した場合を仮配線とすると、その仮配線
の中の任意の格子を中心格子とし、その中心格子の上下
左右に所望のネツト線幅および層間スルーホールの大き
さとなるように必要な周辺格子数を求める線幅抽出手段
と、ネツトの結線を行うための所定の範囲内について他
のネツトの配線または配線禁止領域等の配線不可能領域
が存在する場合に、その配線不可能領域の外周上に結線
しようとするネツトについて中心格子から上下左右に占
有する周辺格子分を見込んで配線およびスルーホールの
禁止を設定する禁止設定手段と、 配線格子上でネツトの配線経路を探索し、基準線幅の
仮配線を求める配線経路探索手段と、その仮配線につい
て周辺格子分拡大し所望の線幅およびスルーホールの大
きさとする配線パターン拡大手段と、配線パターン拡大
後に禁止設定手段により設定された禁止を解除する禁止
解除手段とを設けたものである。According to the present invention, when a net to be connected is extracted and the net is connected with a reference line width as a temporary wiring, an arbitrary grid in the temporary wiring is set as a center grid, and a desired grid is formed at the top, bottom, left and right of the center grid. A line width extracting means for obtaining a required number of peripheral grids so as to have a net line width and a size of an interlayer through hole; and a wiring of another net or a wiring prohibited area within a predetermined range for connecting the net. When a non-wiring area exists, a prohibition setting that sets prohibition of wiring and through holes for nets that are to be connected on the outer periphery of the non-wiring area in consideration of the peripheral grid occupying the upper, lower, left and right from the center grid Means for searching for a net wiring path on the wiring grid and obtaining a temporary wiring of a reference line width; and expanding the temporary wiring by a marginal grid to a desired line width and a desired line width. A wiring pattern enlarging means for setting the size of a hole and a prohibition canceling means for canceling the prohibition set by the prohibition setting means after enlarging the wiring pattern are provided.
本発明は、結線するネツトについて線幅を抽出し、配
線の禁止を設定し、配線経路を探索し、所定の線幅に拡
大し、禁止を解除することにより、複数の線幅を有する
配線について配線を切換えずに所望の配線処理を求める
ことができる。The present invention extracts a line width for a net to be connected, sets a prohibition of wiring, searches for a wiring route, expands to a predetermined line width, and removes the prohibition, thereby removing a wiring having a plurality of line widths. Desired wiring processing can be obtained without switching wiring.
次に本発明の実施例について図を用いて説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の配線処理を示すフローチ
ャートである。まずステツプS1で結線対象のネツトを抽
出し、ステツプS2でそのネツトを基準線幅で結線した場
合を仮配線とすると、その仮配線の中の任意お格子を中
心格子とし、その中心格子の上下左右に所望のネツト線
幅および層間スルーホールの大きさとなるように必要な
周辺格子数を求め（線幅抽出手段）ステップS3でネツト
の結線を行うための所定の範囲内について他のネツトの
配線または配線禁止領域等の配線不可能領域が存在する
場合に、その配線不可能領域の外周上に結線しようとす
るネツトについて中心格子から上下左右に占有する周辺
格子分を見込んで配線およびスルーホールの禁止を設定
し（禁止設定手段）、ステップS4で配線格子上でネツト
の配線経路を探索し、基準線幅の仮配線を求め（配線経
路探索手段）、ステップS5でその仮配線について周辺格
子分拡大し所望の線幅およびスルーホールの大きさとす
し（配線パターン拡大手段）、その後ステツプS6で禁止
設定手段（S3）により設定された禁止を解除し（禁止解
除手段）、最後に他に結線すべきネツトが存在するか否
かを判断し（ステツプS7）、未だ存在する場合にはステ
ツプS1へ戻り、なければ終了する。FIG. 1 is a flowchart showing a wiring process according to one embodiment of the present invention. First, the nets to be connected are extracted in step S1, and the case where the nets are connected with the reference line width in step S2 is assumed to be a temporary wiring. The required number of peripheral grids is determined so as to have the desired net line width and the size of the interlayer through hole on the left and right (line width extracting means). Wiring of other nets within a predetermined range for connecting the nets in step S3 Alternatively, if there is a non-wiring area such as a wiring prohibited area, the nets to be connected on the outer periphery of the non-wiring area should be connected to the wiring and through holes by taking into account the peripheral grid occupied from the center grid vertically and horizontally. Prohibition is set (prohibition setting means), and in step S4, a net wiring route is searched on the wiring grid to obtain a temporary wiring having a reference line width (wiring route searching means). The line is enlarged by the peripheral grid to obtain the desired line width and through hole size (wiring pattern expanding means), and then the prohibition set by the prohibition setting means (S3) is released in step S6 (prohibition releasing means). It is determined whether there are any other nets to be connected at step S7 (step S7). If the nets still exist, the process returns to step S1, and if not, the process ends.
次に第２図（ａ）〜（ｇ）により第１図の配線処理動
作を具体的に説明する。Next, the wiring processing operation of FIG. 1 will be specifically described with reference to FIGS. 2 (a) to 2 (g).
（ａ）図において、T1〜T6は配線を行う１層端子、１
は１層,2層共に配線不可能な領域、２は配線格子であ
る。この場合、１層端子T1とT6を線幅「１」で、１層端
子T2とT4を線幅「３」で、１層端子T3とT4を線幅「１」
で、この順序に配線するものとする。(A) In the figure, T 1 to T 6 are single-layer terminals for wiring, 1
Is a region where both the first and second layers cannot be wired, and 2 is a wiring grid. In this case, one layer terminals T 1 and T 6 in line width "1", the first layer terminal T 2 and T 4 in the line width "3", the line width of the first layer terminals T 3 and T 4 "1"
It is assumed that wiring is performed in this order.
まず、第１図のステツプS1により１層端子T1とT6のネ
ツトが抽出され、ステツプS2によりネツトについて周辺
格子数を求める。この場合は線幅「１」なので中心格子
の上下左右には格子は占有しないので、ステツプS3によ
る禁止の設定はされない。そして、ステツプS4により、
線幅「１」の基準線幅で配線経路が探索され、例えば
（ｂ）図のように１層配線L1、２層配線L2から成る配線
経路３が得られる。ｈは1,2の層間のスルーホールであ
る。この場合は線幅は「１」なので、ステツプS5の処理
は行われず、また、ステツプS3も行わないのでステツプ
S6の禁止解除もされない。First, the net of one layer terminals T 1 and T 6 by step S1 in FIG. 1 is extracted, obtaining the number of surrounding grid for the net by step S2. In this case, since the line width is "1", no grid is occupied above, below, left and right of the center grid, so no prohibition is set by step S3. Then, by step S4,
A wiring path is searched with the reference line width of the line width “1”, and for example, a wiring path 3 including a single-layer wiring L 1 and a two-layer wiring L 2 is obtained as shown in FIG. h is a through hole between the first and second layers. In this case, since the line width is "1", the processing in step S5 is not performed, and step S3 is not performed.
The ban on S6 will not be lifted.
次に、ステツプS7によりステツプS1へ戻り次のネツト
である１層端子T2,T4の抽出が行われる。この端子T2,T4
のネツトでは線幅「３」なので中心格子の周辺格子は１
格子となり（ステツプS2）、ステツプS3により（ｃ）図
のように禁止領域１および配線経路３の外周上に配線禁
止が設定される。K1（○）は１層配線禁止、K2（×）は
２層配線禁止、K3（）は1,2層配線禁止の設定を示
す。この後ステツプS4により（ｄ）図のような仮配線で
ある配線経路４を求め、ステツプS5により（ｅ）図のよ
うに線幅「３」の配線パターンを得るために拡大処理を
行い、配線パターン５を求め、ステツプS6により禁止を
解除し最終的に（ｆ）図のような配線結果を得る。Next, a return following the net to step S1 1 layer terminal T 2, T 4 of the extraction is performed by step S7. These terminals T 2 , T 4
In the case of the net, the line width is “3”, so the peripheral lattice of the central lattice is 1
A grid is formed (step S2), and wiring prohibition is set on the outer periphery of the prohibition area 1 and the wiring path 3 as shown in FIG. K 1 (○) indicates that one layer wiring is prohibited, K 2 (×) indicates that two layer wiring is prohibited, and K 3 () indicates that one or two layer wiring is prohibited. Thereafter, in step S4, a wiring route 4 which is a temporary wiring as shown in FIG. 4D is obtained, and in step S5, an enlarging process is performed to obtain a wiring pattern having a line width "3" as shown in FIG. The pattern 5 is obtained, the prohibition is released in step S6, and finally, a wiring result as shown in FIG.
同様な処理を１層端子T3,T5にも行い配線経路６を求
めると（（ｇ）図）、全ネツトについて配線を完了する
ので配線処理を終える。When the same processing is performed on the first-layer terminals T 3 and T 5 to obtain the wiring path 6 (FIG. 7G), wiring is completed for all nets, and the wiring processing is completed.
このように本実施例では、結線するネツトについて線
幅を抽出し（第１図ステツプS1）、配線の禁止を設定し
（S3）、配線経路を探索し（S4）、所定の線幅に拡大し
（S5）、禁止を解除する（S6）ことにより、複数の線幅
を有する配線について配線を切換えずに所望の配線を行
うことができる。As described above, in this embodiment, the line width is extracted for the nets to be connected (step S1 in FIG. 1), the prohibition of the wiring is set (S3), the wiring route is searched (S4), and the line width is expanded to the predetermined line width. By canceling the prohibition (S5) and canceling the prohibition (S6), desired wiring can be performed without switching wiring for wiring having a plurality of line widths.
以上のように本発明によれば、結線するネツトについ
て線幅を抽出し、配線の禁止を設定し、配線経路を探索
し、所定の線幅に拡大し、禁止を解除することにより、
複数の線幅を有する配線について配線を切換えずに所望
の配線を行うことができるので、配線処理が自動化し、
人手設定時の誤配線がなくなり、配線時間が短縮でき、
線幅の異るネツトの配線順序を最適化して配線率を向上
させることができるという効果がある。このため、LSI
等の今後の高速化に対応して線幅の変更による配線抵抗
の操作がフレキシブルに行える。As described above, according to the present invention, the line width is extracted for the nets to be connected, the prohibition of the wiring is set, the wiring path is searched, the line width is expanded to a predetermined line width, and the prohibition is released.
Since a desired wiring can be performed without switching wiring for wiring having a plurality of line widths, wiring processing is automated,
Erroneous wiring at the time of manual setting is eliminated, and wiring time can be reduced.
There is an effect that the wiring order can be improved by optimizing the wiring order of nets having different line widths. For this reason, LSI
Therefore, the operation of the wiring resistance by changing the line width can be flexibly performed in response to the future increase in speed.
第１図は本発明の一実施例を示す配線処理方式の処理フ
ローチャート、第２図において、（ａ）は具体的な配線
例を示す図、（ｂ）は（ａ）図の端子T1,T6の配線経路
を示す図、（ｃ）は端子T2,T4の配線する際に禁止設定
手段により設定された禁止領域を示す図、（ｄ）は端子
T2,T4についての配線探索手段により求められた仮の配
線経路を示す図、（ｅ）は端子T2,T4について配線パタ
ーン拡大手段により拡大された配線経路を示す図、
（ｆ）は（ｅ）図の禁止領域を削除した配線結果を示す
図、（ｇ）は端子T1〜T6について全て配線処理を行つた
配線結果を示す図である。 S2……線幅抽出手段、S3……禁止設定手段、S4……配線
経路探索手段、S5……配線パターン拡大手段、S6……禁
止解除手段、１……禁止領域、２……配線格子、ｈ……
スルーホール、3,4,5,6……配線経路。FIG. 1 is a processing flowchart of a wiring processing method showing an embodiment of the present invention. In FIG. 2, (a) shows a specific wiring example, and (b) shows terminals T 1 , illustrates the routing of T 6, (c) is a diagram showing a prohibition region set by prohibiting setting means when the wiring terminals T 2, T 4, (d ) the terminal
T 2, T 4 indicates a tentative wiring route determined by the wiring search unit for FIG, (e) is a diagram showing an enlarged wiring route by the wiring pattern enlarged section for terminal T 2, T 4,
(F) is a diagram showing a wiring result obtained by removing the prohibited area in (e), and (g) is a diagram showing a wiring result obtained by performing a wiring process for all of the terminals T 1 to T 6 . S2: Line width extraction means, S3: Prohibition setting means, S4: Wiring route search means, S5: Wiring pattern enlargement means, S6: Prohibition release means, 1 ... Prohibition area, 2 ... Wiring grid, h ……
Through holes, 3, 4, 5, 6 .... Wiring paths.
Claims (1)
を配線用の格子上で行う多層のLSI,PWBの配線処理方式
において、 結線対象のネットを抽出し、そのネツトを基準線幅で結
線した場合を仮配線とすると、その仮配線の中の任意の
格子を中心格子とし、その中心格子の上下左右に所望の
ネツト線幅および層間スルーホールの大きさとなるよう
に必要な周辺格子数を求める線幅抽出手段と、 ネツトの結線を行うための所定の範囲内について他のネ
ツトの配線または配線禁止領域等の配線不可能領域が存
在する場合に、その配線不可能領域の外周上に結線しよ
うとするネツトについて中心格子から上下左右に占有す
る周辺格子分を見込んで配線およびスルーホールの禁止
を設定する禁止設定手段と、 配線格子上でネットの配線経路を探索し、基準線幅の仮
配線を求める配線経路探索手段と、 その仮配線について周辺格子分拡大し所望の線幅および
スルーホールの大きさとする配線パターン拡大手段と、 配線パターン拡大後に禁止設定手段により設定された禁
止を解除する禁止解除手段とを有することを特徴とする
配線処理方式。In a multi-layer LSI and PWB wiring processing system in which predetermined terminals are connected on a wiring grid using nets having different line widths, nets to be connected are extracted and the nets are connected with a reference line width. In this case, if a temporary wiring is used, an arbitrary grid in the temporary wiring is set as a center grid, and the number of peripheral grids necessary to have a desired net line width and a size of an interlayer through hole are formed on the upper, lower, left, and right sides of the center grid. When there is a non-wiring area such as a wiring of another net or a wiring prohibition area within a predetermined range for connecting a net, a wiring is extracted on the outer periphery of the non-wiring area. Prohibition setting means for setting prohibition of wiring and through holes in view of the surrounding grid occupied in the vertical and horizontal directions from the central grid for the net to be tried; and searching for the wiring route of the net on the wiring grid, Wiring path searching means for obtaining a tentative wiring of a quasi-line width, wiring pattern expanding means for expanding the temporary wiring by a peripheral grid to obtain a desired line width and through hole size, and setting by prohibition setting means after expanding the wiring pattern. And a prohibition canceling means for canceling the prohibition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63000714A JP2707568B2 (en) | 1988-01-07 | 1988-01-07 | Wiring processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63000714A JP2707568B2 (en) | 1988-01-07 | 1988-01-07 | Wiring processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01179432A JPH01179432A (en) | 1989-07-17 |
| JP2707568B2 true JP2707568B2 (en) | 1998-01-28 |
Family
ID=11481429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63000714A Expired - Lifetime JP2707568B2 (en) | 1988-01-07 | 1988-01-07 | Wiring processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2707568B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57112049A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Design of wiring pattern |
| JPS6247149A (en) * | 1985-08-26 | 1987-02-28 | Fujitsu Ltd | Manufacture of semiconductor integrated circuit |
| JPS62109173A (en) * | 1985-11-08 | 1987-05-20 | Yokogawa Electric Corp | Designing device for printed board |
-
1988
- 1988-01-07 JP JP63000714A patent/JP2707568B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01179432A (en) | 1989-07-17 |
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