JP2705544B2 - Phase locked loop - Google Patents
Phase locked loopInfo
- Publication number
- JP2705544B2 JP2705544B2 JP5311809A JP31180993A JP2705544B2 JP 2705544 B2 JP2705544 B2 JP 2705544B2 JP 5311809 A JP5311809 A JP 5311809A JP 31180993 A JP31180993 A JP 31180993A JP 2705544 B2 JP2705544 B2 JP 2705544B2
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- voltage
- active filter
- phase
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Networks Using Active Elements (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は位相同期回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop.
【０００２】[0002]
【従来の技術】従来の位相同期回路は、図２に示すよう
に、入力信号と、電圧制御発振器３の出力信号又はその
出力信号を分周器４で分周した信号との位相を比較し、
位相差に応じた電圧ｖを出力する位相比較器１と、位相
比較器１の出力信号を低域通過させる特性を有するアク
ティブフィルタ２と、アクティブフィルタ２の出力電圧
Ｖに応じて出力周波数を制御する電圧制御発振器３とを
有する。位相比較器１は、入力信号ｆｉと電圧制御発振
器３の出力信号ｆｏとの位相差に応じた直流電圧ｖを出
力する。この直流電圧Ｖは、ループフィルタであるアク
ティブフィルタ２を通して、直流電圧Ｖとして電圧制御
発振器３に入力される。電圧制御発振器３は、入力され
た直流電圧Ｖに応答して出力周波数を制御する。このよ
うな動作を繰り返すことにより、電圧制御発振器３の出
力信号ｆｏが入力信号ｆｉと位相同期し、ロックされ
る。2. Description of the Related Art A conventional phase locked loop circuit compares the phase of an input signal with the output signal of a voltage controlled oscillator 3 or a signal obtained by dividing the output signal by a frequency divider 4, as shown in FIG. ,
A phase comparator 1 that outputs a voltage v according to a phase difference; an active filter 2 having a characteristic of passing an output signal of the phase comparator 1 in a low band; and an output frequency controlled according to an output voltage V of the active filter 2 And a voltage-controlled oscillator 3. The phase comparator 1 outputs a DC voltage v corresponding to a phase difference between the input signal fi and the output signal fo of the voltage controlled oscillator 3. This DC voltage V is input to the voltage controlled oscillator 3 as the DC voltage V through the active filter 2 which is a loop filter. The voltage controlled oscillator 3 controls the output frequency in response to the input DC voltage V. By repeating such an operation, the output signal fo of the voltage controlled oscillator 3 is phase-synchronized with the input signal fi and locked.
【０００３】[0003]
【発明が解決しようとする課題】この従来の位相同期回
路では、積分機能をもつ低域通過形のアクティブフィル
タ２を使用している為、同期はずれ時や電源投入時に出
力電圧Ｖがオペアンプへの入力電源電圧「＋Ｖｃｃ」側
又は「−Ｖｃｃ」側の２通りの電圧を取り得ることが可
能である。この為、電圧制御発振器３の出力周波数とア
クティブフィルタ２の時定数との関係により２通りの応
答及び引き込み動作を持ち、どちらかにおいて所望の引
き込み特性を満足できなくなるか、最悪の場合には引き
込むことができなくなる可能性がある。また通常、調整
や定数設定により上述の２通りの応答及び引き込み動作
において所望の特性を満足することは困難である。In this conventional phase locked loop circuit, since the low-pass type active filter 2 having an integrating function is used, the output voltage V is applied to the operational amplifier at the time of loss of synchronization or power-on. It is possible to take two kinds of voltages on the input power supply voltage “+ Vcc” side or “−Vcc” side. For this reason, there are two types of response and pull-in operation depending on the relationship between the output frequency of the voltage controlled oscillator 3 and the time constant of the active filter 2, and either one cannot satisfy the desired pull-in characteristic or in the worst case pull-in. May be unable to do so. In addition, it is usually difficult to satisfy desired characteristics in the above-described two kinds of response and pull-in operations by adjustment and setting of constants.
【０００４】[0004]
【課題を解決するための手段】本発明の位相同期回路
は、同期すべき入力信号と出力信号あるいは該出力信号
を分周した信号との位相を比較してその位相差に応じた
電圧を出力する位相比較器と、前記位相比較器の出力を
低域通過させる特性をもつアクティブフィルタと、前記
アクティブフィルタの出力信号に応じて出力周波数を制
御し前記出力信号として送出する電圧制御発振器とを有
する位相同期回路において、前記位相比較器の出力信号
を受けて同期状態であるか否か検出する同期検出器と、
前記同期検出器の検出結果に応じて前記アクティブフィ
ルタを同期時には低域フィルタ特性に、また非同期時に
は単なる増幅回路特性になるよう切り換え動作するスイ
ッチとを備えることを特徴とする。A phase synchronization circuit according to the present invention compares a phase of an input signal to be synchronized with an output signal or a signal obtained by dividing the output signal, and outputs a voltage corresponding to the phase difference. A phase comparator, an active filter having a characteristic of making the output of the phase comparator low-pass, and a voltage-controlled oscillator for controlling an output frequency according to an output signal of the active filter and transmitting the output signal as the output signal. In a phase synchronization circuit, a synchronization detector that receives an output signal of the phase comparator and detects whether or not a synchronization state exists;
A switch is provided which switches the active filter so as to have a low-pass filter characteristic when synchronized and a simple amplifier circuit characteristic when asynchronous, according to a detection result of the synchronization detector.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００６】図１は本発明の一実施例の回路図である。
入力信号ｆｉと電圧制御発振器３の出力信号を分周器４
で分周した信号との位相を位相比較器１で比較し、その
位相差に応じた電圧ｖを出力する。この出力電圧ｖを、
オペアンプ７と抵抗器８，９，１０ならびにコンデンサ
１１とからなるアクティブフィルタ２を介して、直流電
圧Ｖとして電圧制御発振器３に入力する。アクティブフ
ィルタ２の出力電圧Ｖに応じて電圧制御発振器３におい
て出力周波数を制御し、入力信号ｆｉとの同期信号を出
力信号ｆｏとして得る。FIG. 1 is a circuit diagram of one embodiment of the present invention.
The input signal fi and the output signal of the voltage controlled oscillator 3 are divided by a frequency divider 4
Are compared by the phase comparator 1 and a voltage v corresponding to the phase difference is output. This output voltage v is
The DC voltage V is input to the voltage controlled oscillator 3 via the active filter 2 including the operational amplifier 7, the resistors 8, 9, 10 and the capacitor 11. The output frequency is controlled in the voltage controlled oscillator 3 according to the output voltage V of the active filter 2, and a synchronization signal with the input signal fi is obtained as the output signal fo.
【０００７】同期はずれ時や電源投入時等には、位相比
較器１の出力信号のビート周波数にて非同期の状態であ
ることを同期検出器５で検出し、同期検出器５の出力信
号にてスイッチ６を閉じ、アクティブフィルタ２を形成
しているコンデンサ１１を短絡して、アクティブフィル
タ２の積分機能を一時的に停止させ単なる比例回路にす
る。その後、電圧制御発振器３が入力信号ｆｉに引き込
まれ、位相比較器１が同期時の直流電圧ｖを出力した
時、直流電圧ｖにて同期引き込みを同期検出器５にて検
出し、これに応じてスイッチ６を開き、アクティブフィ
ルタ２の積分回路機能を回復させて、通常の位相同期回
路の構成に戻す。 At the time of loss of synchronization or when power is turned on , the phase comparator 1 is in an asynchronous state at the beat frequency of the output signal.
Is detected by the synchronous detector 5, the switch 6 is closed by the output signal of the synchronous detector 5, the capacitor 11 forming the active filter 2 is short-circuited, and the integration function of the active filter 2 is temporarily stopped. Stop and make it a simple proportional circuit. Thereafter, when the voltage controlled oscillator 3 is pulled into the input signal fi and the phase comparator 1 outputs the DC voltage v at the time of synchronization, the synchronization detector 5 detects the pull-in with the DC voltage v, and responds accordingly. To open the switch 6 to restore the integration circuit function of the active filter 2 to return to the normal phase locked loop configuration.
【０００８】以上の説明から明らかなごとく本実施例で
は、非同期時には常に同一条件からスタートして引き込
み動作に移行するので、従来回路におけるような２通り
の動作の可能性が無くなり、確実な引き込み動作が得ら
れると共に、引き込みに要する時間が長期化するのを防
止できる。As is apparent from the above description, in the present embodiment, at the time of asynchronous operation, the operation always starts under the same condition and shifts to the pull-in operation. The pull-in operation can be obtained, and the time required for the pull-in can be prevented from becoming long.
【０００９】[0009]
【発明の効果】以上説明したように本発明によれば、同
期状態を同期検出器にて検出し、同期検出器の出力信号
によりスイッチを開閉し、アクティブフィルタを同期は
ずれ時や電源投入時等の非同期時には比例回路に、また
同期時には積分回路にそれぞれ接続を切換えることによ
って、非同期時にも常に同一条件で応答及び引き込み動
作させることができ、１通りの引き込み特性しか持ち得
ないようにでき、調整が簡単になる。As described above, according to the present invention, the synchronization state is detected by the synchronization detector, the switch is opened / closed by the output signal of the synchronization detector, and the active filter is synchronized.
By switching the connection to the proportional circuit at the time of non-synchronization at the time of deviation or power- on, and to the integration circuit at the time of synchronization, the response and pull-in operation can always be performed under the same conditions even at the time of non-synchronization. Only characteristics can be provided, and adjustment is simplified.
【００１０】また非同期時のアクティブフィルタの出力
電圧が一意的に規定されるので、応答を速くし、引き込
み時間を短縮できる。Further, since the output voltage of the active filter at the time of asynchronous operation is uniquely defined, the response can be made faster and the pull-in time can be shortened.
【図１】本発明の一実施例の回路図。FIG. 1 is a circuit diagram of one embodiment of the present invention.
【図２】従来の位相同期回路の回路図。FIG. 2 is a circuit diagram of a conventional phase locked loop circuit.
１ 位相比較器 ２ アクティブフィルタ ３ 電圧制御発振器 ４ 分周器 ５ 同期検出器 ６ スイッチ ７ オペアンプ ８，９，１０ 抵抗器 １１ コンデンサ DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Active filter 3 Voltage controlled oscillator 4 Divider 5 Synchronous detector 6 Switch 7 Operational amplifier 8, 9, 10 Resistor 11 Capacitor
Claims (2)
該出力信号を分周した信号との位相を比較してその位相
差に応じた電圧を出力する位相比較器と、前記位相比較
器の出力を低域通過させる特性をもつアクティブフィル
タと、前記アクティブフィルタの出力信号に応じて出力
周波数を制御し前記出力信号として送出する電圧制御発
振器とを有する位相同期回路において、 前記位相比較器の出力信号を受けて同期状態であるか否
か検出する同期検出器と、前記同期検出器の検出結果に
応じて前記アクティブフィルタを同期時には低域フィル
タ特性に、また非同期時には単なる増幅回路特性になる
よう切り換え動作するスイッチとを備えることを特徴と
する位相同期回路。1. A phase comparator for comparing phases of an input signal to be synchronized and an output signal or a signal obtained by dividing the output signal, and outputting a voltage corresponding to the phase difference, and an output of the phase comparator. A phase-locked loop having an active filter having a characteristic of passing a low-pass filter, and a voltage-controlled oscillator for controlling an output frequency in accordance with an output signal of the active filter and transmitting the output signal as the output signal. The active filter is switched to a low-pass filter characteristic when synchronized, and to a mere amplifier circuit characteristic when asynchronous, according to the detection result of the synchronous detector. And a switch that operates.
ルタ特性を形成するためのコンデンサを有し、前記スイ
ッチはそのコンデンサの両端を開閉切り換えする請求項
１記載の位相同期回路。2. The phase-locked loop circuit according to claim 1, wherein said active filter has a capacitor for forming said low-pass filter characteristic, and said switch switches between both ends of said capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5311809A JP2705544B2 (en) | 1993-12-13 | 1993-12-13 | Phase locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5311809A JP2705544B2 (en) | 1993-12-13 | 1993-12-13 | Phase locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07162301A JPH07162301A (en) | 1995-06-23 |
| JP2705544B2 true JP2705544B2 (en) | 1998-01-28 |
Family
ID=18021688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5311809A Expired - Lifetime JP2705544B2 (en) | 1993-12-13 | 1993-12-13 | Phase locked loop |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705544B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972037U (en) * | 1982-11-05 | 1984-05-16 | ソニー株式会社 | PLL |
-
1993
- 1993-12-13 JP JP5311809A patent/JP2705544B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07162301A (en) | 1995-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970909 |