JP2690709B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2690709B2 JP2690709B2 JP7103741A JP10374195A JP2690709B2 JP 2690709 B2 JP2690709 B2 JP 2690709B2 JP 7103741 A JP7103741 A JP 7103741A JP 10374195 A JP10374195 A JP 10374195A JP 2690709 B2 JP2690709 B2 JP 2690709B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer electrode
- lower layer
- insulating film
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
マイクロ波集積回路のデカップリングコンデンサに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a decoupling capacitor for a microwave integrated circuit.
【０００２】[0002]
【従来の技術】マイクロ波集積回路、特に広帯域増幅器
を基板上に配置、使用する場合には、外部電源から誘起
されるリップル等の雑音が周波数特性等に影響を及ぼ
し、帯域特性の低下、及びフラットネス特性の悪化等を
招き、増幅器本来の特性を基板上で再現出来ないことが
ある。2. Description of the Related Art When a microwave integrated circuit, especially a wide band amplifier is arranged and used on a substrate, noise such as ripples induced from an external power source affects frequency characteristics and the like, resulting in deterioration of band characteristics. The flatness characteristic may be deteriorated and the original characteristics of the amplifier may not be reproduced on the substrate.
【０００３】よって、従来は図２に示すように、外部電
源端子に集積回路電源端子を接続するために基板上に形
成された配線と接地端子との間にチップコンデンサ等の
外付けコンデンサ（通常デカップリングコンデンサと呼
ぶ）を接続して配置することにより、外部電源からのリ
ップル等を接地端子に落していた。Therefore, conventionally, as shown in FIG. 2, an external capacitor such as a chip capacitor (usually a chip capacitor) is usually provided between a wiring formed on a substrate for connecting an external power supply terminal to an integrated circuit power supply terminal and a ground terminal. By connecting and arranging a decoupling capacitor), ripples from the external power supply were dropped to the ground terminal.
【０００４】また、配置されるコンデンサは、集積回路
が広帯域で使われるものほど、各周波数帯毎に数種類の
容量値（１００００ｐＦ、１０００ｐＦ、１００ｐＦ、
１０ｐＦ等）のコンデンサを組合わせて配置する必要が
あった。As for the arranged capacitors, the wider the integrated circuit is used, the several kinds of capacitance values (10000 pF, 1000 pF, 100 pF) for each frequency band.
It was necessary to combine and arrange capacitors of 10 pF or the like).
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
では、外付けデカップリングコンデンサを用いているた
め、実装時に部品点数が多くなり、大きな実装スペース
が必要になるという問題があった。In this conventional semiconductor device, since the external decoupling capacitor is used, there is a problem that the number of parts is increased at the time of mounting and a large mounting space is required.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
Ｓｉ基板上に形成した下層電極と、前記下層電極を含む
前記Ｓｉ基板の表面に形成した絶縁膜と、前記絶縁膜に
設けて前記下層電極の一端の表面を露出させるコンタク
トホールと、前記コンタクトホール内に露出した前記下
層電極に電気的に接続した第１の上層電極と、前記第１
の上層電極以外の前記下層電極上に前記絶縁膜を介して
形成し前記下層電極と対向させた第２の上層電極とを有
し、さらにパッシベーション膜でパターニングし、前記
第１の上層電極に接地電極用ボンデイングパッドと、前
記第２の上層電極に前記接地電極用ボンデイングパッド
に隣接して電源電極用のボンデイングパッド形成した構
造を有する。According to the present invention, there is provided a semiconductor device comprising:
A lower layer electrode formed on a Si substrate, an insulating film formed on the surface of the Si substrate including the lower layer electrode, a contact hole provided in the insulating film to expose a surface of one end of the lower layer electrode, and the contact hole A first upper layer electrode electrically connected to the lower layer electrode exposed inside;
Have a second upper electrode said is facing the lower electrode is formed via an insulating film on the lower electrode other than the upper electrode
And patterning with a passivation film,
A bonding pad for the ground electrode is formed on the first upper layer electrode, and
A bonding pad for the ground electrode as a second upper layer electrode
A structure with a bonding pad formed for the power electrode adjacent to
Have structure .
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００８】図１（ａ），（ｂ）は本発明の一実施例を
示す平面図及びＡ−Ａ′線断面図である。FIGS. 1A and 1B are a plan view and a sectional view taken along the line AA 'showing an embodiment of the present invention.
【０００９】図１（ａ），（ｂ）に示すように、マイク
ロ波集積回路チップ内のＳｉ基板１の上に選択的に下層
電極２を形成し、下層電極２を含むＳｉ基板１の上に厚
さ約４００ｎｍの絶縁膜３堆積して下層電極２の上の絶
縁膜３の上部を選択的にエッチングして５０ｎｍの厚さ
まで薄くする。次に、下層電極２の一端の絶縁膜３にコ
ンタクトホール４を形成して下層電極２の表面を露出さ
せ、コンタクトホール４を含む絶縁膜３の表面に金属膜
を堆積してパターニングし、コンタクトホール４内に露
出させた下層電極２に電気的に接続して絶縁膜３上に延
在する第１の上層電極（接地電極）５と、上層電極５以
外の下層電極２の上に形成して絶縁膜３を介して下層電
極２と対向させた第２の上層電極（電源電極）６とを形
成する。次に、上層電極５，６を含む表面を被覆するパ
ッシベーション膜７を形成してパターニングし、上層電
極５，６のそれぞれにボンディングパッド８，９を形成
し、ＭＩＭコンデンサを形成する。As shown in FIGS. 1A and 1B, the lower layer electrode 2 is selectively formed on the Si substrate 1 in the microwave integrated circuit chip, and the Si substrate 1 including the lower layer electrode 2 is formed. Then, the insulating film 3 having a thickness of about 400 nm is deposited, and the upper portion of the insulating film 3 on the lower electrode 2 is selectively etched to reduce the thickness to 50 nm. Next, a contact hole 4 is formed in the insulating film 3 at one end of the lower layer electrode 2 to expose the surface of the lower layer electrode 2, and a metal film is deposited on the surface of the insulating film 3 including the contact hole 4 for patterning. It is formed on the first upper layer electrode (ground electrode) 5 electrically connected to the lower layer electrode 2 exposed in the hole 4 and extending on the insulating film 3, and on the lower layer electrodes 2 other than the upper layer electrode 5. As a result, a second upper layer electrode (power supply electrode) 6 facing the lower layer electrode 2 via the insulating film 3 is formed. Next, a passivation film 7 covering the surface including the upper layer electrodes 5 and 6 is formed and patterned, and bonding pads 8 and 9 are formed on the upper layer electrodes 5 and 6, respectively, to form an MIM capacitor.
【００１０】この場合、ＭＩＭコンデンサの容量値Ｃ
は、 Ｃ＝εO ・εS ・Ｓ／ｄ （但し、εO は真空の誘電率、εS は誘電体膜の比誘電
率、ＳはＭＩＭコンデンサ面積、ｄは誘電体膜の厚さ）
で与えられる。In this case, the capacitance value C of the MIM capacitor
Is C = ε O · ε S · S / d (where ε O is the dielectric constant of the vacuum, ε S is the relative dielectric constant of the dielectric film, S is the MIM capacitor area, and d is the thickness of the dielectric film).
Given by
【００１１】ここで、Ｓ＝１００μｍ×１００μｍ、ε
S ＝７であれば１２ｐＦ位の容量値を確保できる。Here, S = 100 μm × 100 μm, ε
If S = 7, a capacitance value of about 12 pF can be secured.
【００１２】このようなＭＩＭコンデンサを内蔵するこ
とにより、高周波領域用のチップコンデンサを削除で
き、チップサイズや実装面積の増加無しに、電源からの
リップル等の影響をなくし、高周波特性の改良が可能と
なる。By incorporating such an MIM capacitor, the chip capacitor for the high frequency region can be eliminated, the influence of ripples from the power source can be eliminated and the high frequency characteristics can be improved without increasing the chip size or mounting area. Becomes
【００１３】本実施例で、接地電極用のボンディングパ
ッド８と電源電極用のボンディングパッド９を隣接して
レイアウトされていることが重要となる。それは、ボン
ディングパッド８とボンディングパッド９を離してレイ
アウトし一層配線で接続する場合、ボンディングパッド
の外周部を引き回すことが必要となる為、ペレットサイ
ズの増加につながるからである。In this embodiment, it is important that the bonding pad 8 for the ground electrode and the bonding pad 9 for the power supply electrode are laid out adjacent to each other. This is because when the bonding pad 8 and the bonding pad 9 are laid out separately and are connected by a single-layer wiring, it is necessary to draw the outer peripheral portion of the bonding pad, which leads to an increase in the pellet size.
【００１４】集積回路内で使用されるコンデンサには、
ＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃ
ｏｎｄｕｃｔｏｒ）構造のものもあるが、内蔵するコン
デンサの容量値は使用周波数、応用回路によって様々な
定数を選択する必要があり、ＭＩＳ構造ではこれらに対
応しきれない場合があるのに対してＭＩＭ構造であれば
メタライズ工程のみで所望の容量値を実現できる利点が
ある。The capacitors used in integrated circuits include:
MIS (Metal-Insulator-Semiic)
There are some types of on-conductor structure, but it is necessary to select various constants for the capacitance value of the built-in capacitor, depending on the operating frequency and application circuit, and the MIS structure may not be able to handle these, whereas the MIM structure. In that case, there is an advantage that a desired capacitance value can be realized only by the metallizing process.
【００１５】[0015]
【発明の効果】以上説明したように、本発明はマイクロ
波集積回路、特に広帯域増加器におけるデカップリング
コンデンサをＭＩＭ構造のコンデンサ（１０ｐＦ程度）
で形成する事により、実装面積及びチップサイズを増や
すこと無しに、帯域特性の向上（２ＧＨｚを越える領域
で１０％〜２０％の向上）及びフラットネスの向上（平
坦性±１ｄＢから±０．２ｄＢに改善）が実現できると
いう効果を有する。As described above, according to the present invention, the decoupling capacitor in the microwave integrated circuit, especially in the wide band amplifier is the MIM structure capacitor (about 10 pF).
In this case, the band characteristic is improved (10% to 20% in the region over 2 GHz) and the flatness is improved (flatness ± 1 dB to ± 0.2 dB) without increasing the mounting area and the chip size. It has the effect that the improvement can be realized.
【図１】本発明の一実施例を示す平面図及びＡ−Ａ′線
断面図。FIG. 1 is a plan view and a sectional view taken along the line AA ′ showing an embodiment of the present invention.
【図２】従来の半導体装置の一例を説明するためのブロ
ック図。FIG. 2 is a block diagram illustrating an example of a conventional semiconductor device.
１ Ｓｉ基板 ２ 下層電極 ３ 絶縁膜 ４ コンタクトホール ５，６ 上層電極 ７ パッシベーション膜 ８，９ ボンディングパッド 1 Si substrate 2 Lower layer electrode 3 Insulating film 4 Contact hole 5,6 Upper layer electrode 7 Passivation film 8, 9 Bonding pad
Claims (1)
下層電極を含む前記Ｓｉ基板の表面に形成した絶縁膜
と、前記絶縁膜に設けて前記下層電極の一端の表面を露
出させるコンタクトホールと、前記コンタクトホール内
に露出した前記下層電極に電気的に接続した第１の上層
電極と、前記第１の上層電極以外の前記下層電極上に前
記絶縁膜を介して形成し前記下層電極と対向させた第２
の上層電極とを有し、さらにパッシベーション膜でパタ
ーニングし、前記第１の上層電極に接地電極用ボンデイ
ングパッドと、前記第２の上層電極に前記接地電極用ボ
ンデイングパッドに隣接して電源電極用のボンデイング
パッドを形成した構造を有することを特徴とする半導体
装置。1. A lower layer electrode formed on a Si substrate, an insulating film formed on the surface of the Si substrate including the lower layer electrode, and a contact hole provided in the insulating film to expose a surface of one end of the lower layer electrode. A first upper layer electrode electrically connected to the lower layer electrode exposed in the contact hole, and the lower layer electrode formed on the lower layer electrodes other than the first upper layer electrode via the insulating film. Second facing
It has a top electrode and a passivation film.
And grounding electrode bond to the first upper layer electrode.
And a grounding pad on the second upper electrode.
Bonding for power electrodes adjacent to the bonding pad
A semiconductor device having a structure in which a pad is formed .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7103741A JP2690709B2 (en) | 1995-04-27 | 1995-04-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7103741A JP2690709B2 (en) | 1995-04-27 | 1995-04-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08298307A JPH08298307A (en) | 1996-11-12 |
| JP2690709B2 true JP2690709B2 (en) | 1997-12-17 |
Family
ID=14362044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7103741A Expired - Lifetime JP2690709B2 (en) | 1995-04-27 | 1995-04-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2690709B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10035584A1 (en) * | 2000-07-21 | 2002-01-31 | Philips Corp Intellectual Pty | mobile device |
| KR20020082549A (en) * | 2001-04-24 | 2002-10-31 | 주식회사 하이닉스반도체 | Method of manufacturing high capacitance mim capacitor |
| US7224040B2 (en) | 2003-11-28 | 2007-05-29 | Gennum Corporation | Multi-level thin film capacitor on a ceramic substrate |
| JP5818624B2 (en) * | 2011-10-07 | 2015-11-18 | 株式会社東芝 | High frequency amplifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03293759A (en) * | 1990-04-12 | 1991-12-25 | Fuji Electric Co Ltd | Capacitor to be incorporated into mos integrated circuit device |
-
1995
- 1995-04-27 JP JP7103741A patent/JP2690709B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08298307A (en) | 1996-11-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970729 |