JP2676756B2 - Receiver front end - Google Patents
Receiver front endInfo
- Publication number
- JP2676756B2 JP2676756B2 JP2434588A JP2434588A JP2676756B2 JP 2676756 B2 JP2676756 B2 JP 2676756B2 JP 2434588 A JP2434588 A JP 2434588A JP 2434588 A JP2434588 A JP 2434588A JP 2676756 B2 JP2676756 B2 JP 2676756B2
- Authority
- JP
- Japan
- Prior art keywords
- tuning circuit
- capacitance
- circuit
- oscillation
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 産業上の利用分野 本発明は受信機のプリントコイルを用いたフロント・
エンドに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a front end using a printed coil of a receiver.
It's about the end.
従来の技術 近年、受信機のフロント・エンドの同調回路に印刷配
線によるプリントコイルを採用してきている。2. Description of the Related Art In recent years, a print coil using printed wiring has been adopted in a tuning circuit at the front end of a receiver.
以下図面を参照しながら、上述した従来の受信機のフ
ロント・エンドの一例について説明する。An example of the front end of the above-described conventional receiver will be described below with reference to the drawings.
第２図は従来の受信機のフロント・エンドのブロック
図を示すものである。第２図において、１はアンテナ入
力、２はプリントコイルL1と可変容量ダイオードCD1と
付加容量（トリマコンデンサ）C1で構成された受信周波
数同調回路、３はプリントコイルL2と可変容量ダイオー
ドCD2と付加容量C2で構成された発振周波数同調回路、
４は受信周波数１とそれにより上側の発振周波数２
の混合回路で５の中間周波数３を出力する。したがっ
て２ ＝１＋３ の関係がある。FIG. 2 shows a block diagram of the front end of a conventional receiver. In FIG. 2, 1 is an antenna input, 2 is a receiving frequency tuning circuit composed of a print coil L1, a variable capacitance diode C D1 and an additional capacitance (trimmer capacitor) C 1 , 3 is a print coil L2 and a variable capacitance diode C D2 And an oscillation frequency tuning circuit composed of an additional capacitance C 2 .
4 is the reception frequency 1 and, as a result, the upper oscillation frequency 2
The intermediate frequency 3 of 5 is output by the mixing circuit of. Therefore, there is a relationship of 2 = 1 + 3 .
可変容量タイオードに与える同調電圧VTによって得ら
れる容量特性を第３図ａに示す。同調回路の周波数は より同調電圧対周波数は第３図ｂに示すように変化す
る。そして受信周波数帯域をカバーするために同調電圧
をVTmin〜VTmaxまで可変する。このとき最適に同調する
為には受振周波数１と発振周波数２の差はつねに一
定の中間周波数３でなければならない。その為に可変
容量ダイオードCD1とCD2はランク分けをして特性のそろ
った部品を使う。そしてコイルと付加容量を調整してト
ラッキングを合わすことになる。ここで、コイルには印
刷配線のプリントコイルを使い、印刷配線基板のエッチ
ングによってＬ値がばらついてもプリントコイルL1とL2
のＬ値が同じ比率に変わるのでトラッキングに悪影響は
ないから、設計的にトラッキングが合うように銅箔のパ
ターンで、Ｌ値をあらかじめ設定している。そうすると
付加容量C1とC2でトラッキングを調整することになる
が、発振周波数２をPLL周波数シンセサイザ回路６に
よって制御するとトラッキング調整の為の調整箇所は受
信周波数同調回路２の付加容量C1（≒7pF程度のトリマ
コンデンサ）のみとなる。受信周波数同調回路の段数が
増えるとそれに応じてトリマコンデンサを増設して調整
する。The capacitance characteristic obtained by the tuning voltage V T applied to the variable capacitance diode is shown in FIG. 3a. The frequency of the tuning circuit is As a result, the tuning voltage versus frequency changes as shown in Figure 3b. Then, the tuning voltage is varied from V Tmin to V Tmax to cover the reception frequency band. At this time, the difference between the receiving frequency 1 and the oscillating frequency 2 must always be a constant intermediate frequency 3 for optimum tuning. Therefore, the variable-capacitance diodes C D1 and C D2 are divided into ranks and parts with uniform characteristics are used. Then, the coil and the additional capacitance are adjusted to match the tracking. Here, a print coil of printed wiring is used as the coil, and even if the L value varies due to etching of the printed wiring board, the printed coils L1 and L2
Since there is no adverse effect on the tracking because the L value of is changed to the same ratio, the L value is set in advance by a copper foil pattern so that the tracking is designed by design. Then, the tracking is adjusted by the additional capacitances C 1 and C 2 , but if the oscillation frequency 2 is controlled by the PLL frequency synthesizer circuit 6, the adjustment point for tracking adjustment is the additional capacitance C 1 (≈ It is only a 7pF trimmer capacitor). If the number of stages of the reception frequency tuning circuit increases, a trimmer capacitor will be added and adjusted accordingly.
発明が解決しようとする課題 しかしながら上記のような構成では、調整部品と調整
工程を必要とするので製造工程の合理化がむつかしいと
いう問題点を有していた。SUMMARY OF THE INVENTION However, the above-described configuration has a problem that it is difficult to rationalize the manufacturing process because the adjusting component and the adjusting process are required.
本発明は上記問題点に鑑み、製造工程でトラッキング
調整をなくした受信機のフロント・エンドを提供するも
のである。In view of the above problems, the present invention provides a front end of a receiver that eliminates tracking adjustment in the manufacturing process.
課題を解決するための手段 上記問題点を解決するために本発明の受信機のフロン
ト・エンドは、受信周波数同調回路の付加容量をなく
し、印刷配線によるプリントコイルと可変容量タイオー
ドからなる同調回路を発振周波数同調回路と受信周波数
同等回路の全段に備えるとともに、発振周波数同調回路
の発振回路半導体素子との結合容量と発振周波数同調回
路に設けた付加容量をトラッキング補正用の固定のコン
デンサとしたものである。Means for Solving the Problems In order to solve the above problems, the receiver front end of the present invention eliminates the additional capacitance of the reception frequency tuning circuit, and includes a tuning circuit consisting of a printed coil by printed wiring and a variable capacitance diode. The oscillation frequency tuning circuit and the receiving frequency equivalent circuit are provided in all stages, and the coupling capacitance between the oscillation frequency tuning circuit and the oscillation circuit semiconductor element and the additional capacitance provided in the oscillation frequency tuning circuit are used as fixed capacitors for tracking correction. Is.
作用 本発明は上記した構成によってしばらくつく要因を減
らして調整部分をなくすことにより製造工程の合理化が
できることとなる。Operation The present invention can streamline the manufacturing process by reducing the factor that takes a while to eliminate the adjustment part by the above-mentioned configuration.
実 施 例 以下本発明の一実施例の受信機のフロント・エンドに
ついて、図面を参照しながら説明する。第１図は本発明
の一実施例における受信機のフロント・エンドのブロッ
ク図を示すものである。第１図において第２図と同じ番
号を付した部分は説明を省略する。12はプリントコイル
L11とバックツーバック型可変容量ダイオードCD11で構
成された受信周波数同調回路、13はプリントコイルL12
とバックツーバック型可変容量ダイオードCD12と発振ト
ランジスタのベース側をみた等価容量Ｃ′と結合容量Ｃ
と付加容量C2′の合成容量C12で構成された発振周波数
同調回路である。局部発振周波数２は受信周波数１
の中間周波数３（10.7MHz）だけ上とし、受信周波数
１は87.5MHz〜108MHzのいわゆるFMの米国バンドと
し、従来例と同様にPLL周波数シンセサイザ回路６によ
って制御している。バックツーバック型可変容量ダイオ
ードCD11とCD12はランク分けをしてその特性の等しいも
のを選びCD11＝CD12＝CDと置き、バンド下限の容量値と
してＣＤmin＝33pFを選んでトラッキングがとれる
と、 の各式からL11＝0.1μH,CＤmax＝21.7pF,L12＝0.073
μH,C12＝2.8pFが求められる。実際には浮遊容量や回路
間の結合のために値が若干異なり、部品を実装して、結
合容量Ｃの値を発振回路が安定に発振するように6pF,付
加容量C2′の値として0.5pFに選び、プリントコイルL1
1,L12のＬ値と可変容量ダイオードに加える同調電圧VT
をトラッキングをとりながら設定する。Embodiment A receiver front end according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a front end of a receiver according to an embodiment of the present invention. The description of the parts in FIG. 1 given the same numbers as in FIG. 2 is omitted. 12 is a printed coil
Reception frequency tuning circuit composed of L11 and back-to-back variable capacitance diode C D11 , 13 is printed coil L12
And the back-to-back type variable capacitance diode C D12 , the equivalent capacitance C'as seen from the base side of the oscillation transistor, and the coupling capacitance C
And an oscillation frequency tuning circuit composed of a combined capacitance C12 of an additional capacitance C2 '. Local oscillation frequency 2 is reception frequency 1
Only the intermediate frequency of 3 (10.7MHz) above
1 is a so-called FM American band of 87.5 MHz to 108 MHz, and is controlled by the PLL frequency synthesizer circuit 6 as in the conventional example. The back-to-back type variable capacitance diodes C D11 and C D12 are ranked and selected to have the same characteristics and placed as C D11 = C D12 = C D, and C Dmin = 33 pF is selected as the capacitance value at the lower limit of the band for tracking. When you get From each formula of L11 = 0.1μH, C Dmax = 21.7pF, L12 = 0.073
μH, C12 = 2.8pF is required. Actually, the value is slightly different due to stray capacitance and coupling between circuits. By mounting components, the coupling capacitance C value is 6pF and the additional capacitance C2 'is 0.5pF so that the oscillation circuit oscillates stably. Select and print coil L1
L value of 1, L12 and tuning voltage V T applied to the variable capacitance diode
Set while tracking.
以上のようにして同調回路を設計すると、トラッキン
グのずれる要素としては、プリントコイルL11とL12はそ
の値がエッチングや環境条件等によってばらついても
（実際にはわずかであるが）プリントコイルL11とL12を
同じ印刷配線基板で構成しているかぎり同じ比率で変化
するのでトラッキングに悪影響はないから、合成容量C1
2のばらつきがあげられる。しかしながら結合容量Ｃと
して±0.25pFのような偏差の少ない部品を使っておけば
合成容量C12の値が小さいので同調容量全体のばらつき
は少ない。したがってトラッキングに与える影響が小さ
いから結合容量Ｃは固定のコンデンサで良い。When the tuning circuit is designed as described above, the factors that cause tracking deviation are that the print coils L11 and L12 have a slight variation in their values due to etching, environmental conditions, etc. As long as they are composed of the same printed wiring board, they will change at the same ratio, so tracking will not be adversely affected.
There is a variation of 2. However, if a component having a small deviation such as ± 0.25 pF is used as the coupling capacitance C, the value of the combined capacitance C12 is small, so that the variation of the entire tuning capacitance is small. Therefore, since the influence on tracking is small, the coupling capacitance C may be a fixed capacitor.
また従来例のように一素子型可変容量ダイオードでは
直列に結合容量Coを必要とするが本実施例のようにバッ
クツーバック型可変容量ダイオードを使うと結合容量Co
が不要であるので、部品の少ない分だけばらつく要素も
減る。Further, as in the conventional example, the one-element type variable capacitance diode requires the coupling capacitance Co in series, but when the back-to-back type variable capacitance diode is used as in this embodiment, the coupling capacitance Co
Since there is no need for components, there are fewer elements that vary due to fewer parts.
また、本実施例では回路間の結合のトラッキングに与
える影響を少なくするためにプリントコイルにタップを
設けて回路間の接続を行なっている。Further, in the present embodiment, in order to reduce the influence on the tracking of the coupling between the circuits, the printed coils are provided with taps to connect the circuits.
以上のように本実施例によれば、プリントコイルと可
変容量ダイオードからなる同調回路を発振周波数同調回
路と受信周波数同調回路の全段に備えるとともに発振周
波数同調回路の発振回路半導体素子との結合容量Ｃと発
振周波数同調回路に設けた付加容量C2′をトラッキング
補正用のコンデンサとしているので、結合容量Ｃは固定
のコンデンサで良いから調整の必要な部品をなくすこと
ができる。As described above, according to this embodiment, the tuning circuit including the print coil and the variable capacitance diode is provided in all stages of the oscillation frequency tuning circuit and the receiving frequency tuning circuit, and the coupling capacitance between the oscillation frequency tuning circuit and the oscillation circuit semiconductor element is provided. Since C and the additional capacitance C2 'provided in the oscillation frequency tuning circuit are used as the capacitors for tracking correction, the coupling capacitance C may be a fixed capacitor, so that parts requiring adjustment can be eliminated.
なお請求の範囲で発振周波数が上側と限定したのは、
受信周波数が上側の場合にはminからmaxの同調容量
の容量変化比は受信周波数同調回路の方が小さくなけれ
ばならないので受信周波数同調回路にトラッキング補正
用の付加容量（5pF程）が必要となり、ばらつく要因が
増えるからである。もっとも、受信感度がばらついても
良ければ発振周波数はPLL周波数シンセサイザ回路で制
御しているのでこの付加容量は固定のコンデンサで良
い。In the claims, the upper limit of the oscillation frequency is
When the reception frequency is on the upper side, the capacitance change ratio of the tuning capacitance from min to max must be smaller in the reception frequency tuning circuit, so the reception frequency tuning circuit requires additional capacitance (about 5 pF) for tracking correction, This is because there are more factors that cause variations. However, if the reception sensitivity may vary, the oscillation frequency is controlled by the PLL frequency synthesizer circuit, so this additional capacitance may be a fixed capacitor.
発明の効果 以上のように本発明は、プリントコイルと可変容量ダ
イオードからなる同調回路を発振周波数同調回路と受信
周波数同調回路の全段に備えるとともに、発振周波数同
調回路の発振回路半導体素子との結合容量と発振周波数
同調回路に設けた付加容量をトラッキング補正用のコン
デンサとしているので調整部品をなくすことができ、構
成部品のコストを低減できるほか、調整工程を必要とせ
ず製造工程の合理化ができる等工業的利用価値のきわめ
て高いものである。As described above, according to the present invention, the tuning circuit including the print coil and the variable capacitance diode is provided in all stages of the oscillation frequency tuning circuit and the reception frequency tuning circuit, and the oscillation frequency tuning circuit is coupled to the oscillation circuit semiconductor element. Since the capacitance and the additional capacitance provided in the oscillation frequency tuning circuit are used for tracking correction capacitors, adjustment parts can be eliminated, the cost of components can be reduced, and the manufacturing process can be rationalized without the need for adjustment processes. It has extremely high industrial utility value.
第１図は本発明の一実施例の受信機のフロント・エンド
のブロック図、第２図は従来の受信機のフロント・エン
ドのブロック図、第３図ａは可変容量ダイオードの特性
図、第３図ｂは同調電圧対周波数特性図である。 12……受信周波数同調回路、13……発振周波数同調回
路、L11,L12……プリントコイル、CD11,CD12……可変容
量ダイオード、Ｃ……結合容量。1 is a block diagram of a front end of a receiver according to an embodiment of the present invention, FIG. 2 is a block diagram of a front end of a conventional receiver, and FIG. 3a is a characteristic diagram of a variable capacitance diode. FIG. 3b is a tuning voltage vs. frequency characteristic diagram. 12 …… Reception frequency tuning circuit, 13 …… Oscillation frequency tuning circuit, L11, L12 …… Print coil, C D11 , C D12 …… Variable capacitance diode, C …… Coupling capacitance.
Claims (1)
て、印刷配線によるプリントコイルと可変容量ダイオー
ドからなる同調回路を発信周波数同調回路と受信周波数
同調回路の全段に備えるとともに、上記発振周波数同調
回路の発振回路半導体素子との結合容量と発振周波数同
調回路に設けた付加容量をトラッキング補正用の固定の
コンデンサとしたことを特徴とする受信機のフロントエ
ンド。1. A tuning circuit having an oscillation frequency above the reception frequency and comprising a printed coil formed by printed wiring and a variable capacitance diode is provided in all stages of the transmission frequency tuning circuit and the reception frequency tuning circuit, and the oscillation frequency tuning is performed. A receiver front end, characterized in that a coupling capacitor with an oscillation circuit semiconductor element of the circuit and an additional capacitor provided in an oscillation frequency tuning circuit are fixed capacitors for tracking correction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2434588A JP2676756B2 (en) | 1988-02-03 | 1988-02-03 | Receiver front end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2434588A JP2676756B2 (en) | 1988-02-03 | 1988-02-03 | Receiver front end |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01198821A JPH01198821A (en) | 1989-08-10 |
| JP2676756B2 true JP2676756B2 (en) | 1997-11-17 |
Family
ID=12135601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2434588A Expired - Lifetime JP2676756B2 (en) | 1988-02-03 | 1988-02-03 | Receiver front end |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2676756B2 (en) |
-
1988
- 1988-02-03 JP JP2434588A patent/JP2676756B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01198821A (en) | 1989-08-10 |
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