JP2650455B2 - Semiconductor pressure sensor - Google Patents
Semiconductor pressure sensorInfo
- Publication number
- JP2650455B2 JP2650455B2 JP2024649A JP2464990A JP2650455B2 JP 2650455 B2 JP2650455 B2 JP 2650455B2 JP 2024649 A JP2024649 A JP 2024649A JP 2464990 A JP2464990 A JP 2464990A JP 2650455 B2 JP2650455 B2 JP 2650455B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- diaphragm
- passivation film
- stress
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Pressure Sensors (AREA)
- Measuring Fluid Pressure (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体圧力センサに関し、詳しくは、集積
回路部（一個の回路素子で構成されてもよい）と一体集
積された半導体圧力センサに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor pressure sensor, and more particularly, to a semiconductor pressure sensor integrated with an integrated circuit unit (may be constituted by one circuit element). .
［従来の技術］ 本出願人の出願にかかわる特開昭62−266875号公報
は、例えば第４図に示すように、単結晶シリコン基板1a
の一主面をエッチングして形成されたダイヤフラム部7a
と、ダイヤフラム部7aの周辺において単結晶シリコン基
板1aの他主面に不純物をドープして形成された集積回路
部8aと、ダイヤフラム部7aを除いて集積回路部8aの表面
に形成されたパッシベーション膜6aとを備える半導体圧
力センサを開示している。[Prior Art] Japanese Patent Application Laid-Open No. Sho 62-266875 relating to the application of the present applicant discloses, for example, a single-crystal silicon substrate 1a as shown in FIG.
Diaphragm part 7a formed by etching one main surface of
And an integrated circuit portion 8a formed by doping the other main surface of the single-crystal silicon substrate 1a with impurities around the diaphragm portion 7a, and a passivation film formed on the surface of the integrated circuit portion 8a except for the diaphragm portion 7a. 6a.
［発明が解決しようとする課題］ 上述したように、集積回路部8aをもつ半導体圧力セン
サでは集積回路部8aの保護のためにパッシベーション膜
6aを設ける必要がある。ただ、パッシベーション膜6aを
ダイヤフラム部7a上に被着すると、パッシベーション膜
形成時に発生するパッシベーション膜6aの歪みや、パッ
シベーション膜6aとシリコン基板1a（正確にはその上の
フィールド酸化膜）との熱膨張率の差に起因する界面歪
などのために、圧力センサの出力特性、特に温度特性が
劣化し、出力感度も低下する。[Problems to be Solved by the Invention] As described above, in a semiconductor pressure sensor having an integrated circuit portion 8a, a passivation film is provided for protecting the integrated circuit portion 8a.
6a needs to be provided. However, if the passivation film 6a is deposited on the diaphragm portion 7a, the distortion of the passivation film 6a generated when the passivation film is formed and the thermal expansion between the passivation film 6a and the silicon substrate 1a (more precisely, the field oxide film thereon). The output characteristics, particularly the temperature characteristics, of the pressure sensor are degraded due to interface distortion or the like caused by the difference in the rate, and the output sensitivity is also lowered.
従って上記公報に開示されるようにダイヤフラム部7a
表面のパッシベーション膜6aを除去することが好まし
が、この場合、ダイヤフラム部7a近傍に位置するパッシ
ベーション膜6aの端縁部60aにおいて、第３図に実線で
示すように応力集中が生じ、温度変化により生じる熱応
力の集中により、出力特性、特に温度特性が劣化する。Therefore, as disclosed in the above publication, the diaphragm portion 7a
It is preferable to remove the passivation film 6a on the surface, but in this case, stress concentration occurs at the edge 60a of the passivation film 6a located near the diaphragm 7a as shown by a solid line in FIG. The output characteristics, especially the temperature characteristics, are degraded due to the concentration of the thermal stress caused by the heat.
本発明は上記問題の改善を図って、ダイヤフラム部近
傍における応力集中の低減により出力特性変動の低減が
可能な半導体圧力センサを提供することを、その解決す
べき課題としている。An object of the present invention is to provide a semiconductor pressure sensor capable of reducing output characteristic fluctuations by reducing stress concentration in the vicinity of a diaphragm portion in order to improve the above problem.
［課題を解決するための手段］ 本発明の半導体圧力センサは、単結晶シリコン基板の
一主面をエッチングして形成されるとともにピエゾ拡散
ゲージが形成されたダイヤフラム部と、該ダイヤフラム
部の周辺において前記単結晶シリコン基板の他主面に形
成された集積回路部と、BPSG膜と窒化シリコン膜と窒化
シリコン膜及び酸化シリコン膜からなる２層膜とのうち
のいずれかからなり、前記ダイヤフラム部以外の少なく
とも前記集積回路部の表面に覆って形成された集積回路
部保護用のパッシベーション膜と、前記パッシベーショ
ン膜よりも変形容易な性質を有するとともに、前記ダイ
ヤフラム部側の前記パッシベーション膜の端縁部と前記
単結晶シリコン基板との間に位置して前記ダイヤフラム
部の周縁部に沿いつつ帯状に配設される応力吸収緩和膜
とを備えることを特徴としている。[Means for Solving the Problems] A semiconductor pressure sensor according to the present invention includes a diaphragm portion formed by etching one main surface of a single crystal silicon substrate and having a piezo diffusion gauge formed thereon, and a periphery of the diaphragm portion. An integrated circuit portion formed on the other main surface of the single crystal silicon substrate; and a BPSG film, a silicon nitride film, or a two-layer film made of a silicon nitride film and a silicon oxide film, other than the diaphragm portion. A passivation film for protecting the integrated circuit portion formed over at least the surface of the integrated circuit portion, and having properties more easily deformable than the passivation film, and an edge portion of the passivation film on the diaphragm portion side. A stress which is arranged between the single crystal silicon substrate and a strip along the periphery of the diaphragm portion; It is characterized in that it comprises a yield relaxation film.
応力吸収緩和膜としては、例えば、アルミニウム、
金、などの軟質金属膜を採用することができ、膜厚は0.
5μｍ以上とすることが好ましい。このような軟質金属
膜は、上記応力集中より塑性変形（弾性変形も伴う）し
て応力を緩和する。また、ポリイミドなどの樹脂膜を採
用することができる。このような樹脂膜は大きな弾性率
をもつので応力吸収能に富む。その他、応力吸収緩和膜
は単一膜でなく複層膜としてもよい。As the stress absorption relaxation film, for example, aluminum,
A soft metal film such as gold can be used, and the film thickness is 0.
The thickness is preferably 5 μm or more. Such a soft metal film is plastically deformed (also accompanied by elastic deformation) due to the above-mentioned stress concentration, thereby relaxing the stress. Further, a resin film such as polyimide can be employed. Since such a resin film has a large elastic modulus, it is rich in stress absorbing ability. In addition, the stress absorption relaxation film may be a multilayer film instead of a single film.
［作用］ ダイヤフラム部の境界部分に位置するパッシベーショ
ン膜の端縁部において、ダイヤフラム部の歪みによる応
力は、応力吸収緩和膜の変形により吸収され、その結
果、ダイヤフラム部の境界部分における応力集中は防止
される。[Operation] At the edge of the passivation film located at the boundary of the diaphragm, the stress due to the distortion of the diaphragm is absorbed by the deformation of the stress absorption relaxation film, and as a result, the concentration of stress at the boundary of the diaphragm is prevented. Is done.
［発明の効果］ 上記したように、本発明の半導体圧力センサでは、集
積回路部が一体集積された半導体圧力センサにおいてパ
ッシベーション膜の端縁部がダイヤフラム部の境界部分
で変形容易な応力吸収緩和膜上に設けられているので、
このパッシベーション膜の端縁部に応力が集中するのを
防止して、この応力集中による出力特性劣化を防止する
ことができる。[Effects of the Invention] As described above, in the semiconductor pressure sensor of the present invention, in the semiconductor pressure sensor in which the integrated circuit portion is integrally integrated, the edge portion of the passivation film is easily deformed at the boundary portion of the diaphragm portion. Since it is provided above,
It is possible to prevent stress from concentrating on the edge of the passivation film and prevent deterioration of output characteristics due to the stress concentration.
更に説明すると、本発明によれば、パッシベーション
膜を重ねることによるダイヤフラム部の感度特性の劣化
を回避しつつ集積回路部を汚染から保護することができ
るとともに、パッシベーション膜の端部近傍において最
大となる応力集中を応力吸収緩和膜の変形により緩和さ
せ、これにより、上記応力に起因する出力特性の変動を
抑止することができる。More specifically, according to the present invention, it is possible to protect the integrated circuit portion from contamination while avoiding the deterioration of the sensitivity characteristic of the diaphragm portion due to the superposition of the passivation film, and it is maximized near the end of the passivation film. The stress concentration is alleviated by the deformation of the stress absorption and relaxation film, whereby the fluctuation of the output characteristic due to the stress can be suppressed.
［実施例］ 本発明の半導体圧力センサの一実施例をについて、そ
の平面図を第１図に、そのＡ−Ａ′線矢視断面図を第２
図に示す。Embodiment FIG. 1 is a plan view of an embodiment of a semiconductor pressure sensor according to the present invention, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
Shown in the figure.
この半導体圧力センサは、所定の結晶軸を有するシリ
コン基板１、シリコン基板１の一主面に形成された薄肉
のダイヤフラム部７、ダイヤフラム部７に設けられたピ
エゾ拡散ゲージ２、シリコン基板１の他主面に形成され
たアンプ回路（集積回路部）８、ダイヤフラム部７を除
きアンプ回路８の表面に形成されたパッシベーション膜
６、ダイヤフラム部７の境界部分においてシリコン基板
１のフィールド酸化膜４上に配設された応力吸収緩和膜
９を備えている。This semiconductor pressure sensor includes a silicon substrate 1 having a predetermined crystal axis, a thin diaphragm portion 7 formed on one main surface of the silicon substrate 1, a piezo diffusion gauge 2 provided on the diaphragm portion 7, a silicon substrate 1, and the like. An amplifier circuit (integrated circuit portion) 8 formed on the main surface, a passivation film 6 formed on the surface of the amplifier circuit 8 except for the diaphragm portion 7, and a boundary portion between the diaphragm portion 7 and the field oxide film 4 of the silicon substrate 1. A stress absorption / relaxation film 9 is provided.
そして、パッシベーション膜６の端縁部は、応力吸収
緩和膜９の表面上に被着されている。The edge of the passivation film 6 is attached on the surface of the stress absorption relaxation film 9.
ダイヤフラム部７は、水酸化カリウム（KOH）等の異
方性エッチング液を用いる異方性エッチングにより形成
される。The diaphragm portion 7 is formed by anisotropic etching using an anisotropic etching solution such as potassium hydroxide (KOH).
ピエゾ拡散ゲージ２は、シリコン基板１の表面部にイ
オン注入技術等によりダイヤフラム部７の中央部に一
対、図中左右周辺部に各一個形成されており、各ピエゾ
拡散ゲージ２は拡散リード３によりブリッジ結線されて
いる。A pair of piezo diffusion gauges 2 are formed on the surface of the silicon substrate 1 at the center of the diaphragm 7 by ion implantation technology or the like, and one piezo diffusion gauge 2 is formed on each of the left and right peripheral portions in the figure. Bridge connection.
アンプ回路（集積回路部）８は、バイポーラIC又はＣ
−MOSIC等からなり、ピエゾ拡散ゲージ２からなるブリ
ッジの信号電圧を増幅して外部に出力する。The amplifier circuit (integrated circuit section) 8 is a bipolar IC or C
-Amplifies the signal voltage of a bridge composed of MOSIC or the like and composed of the piezo diffusion gauge 2 and outputs the amplified signal voltage to the outside.
フィールド酸化膜４は、CVD法により形成された二酸
化シリコン膜からなり、１μｍの厚さをもつ。Field oxide film 4 is made of a silicon dioxide film formed by a CVD method, and has a thickness of 1 μm.
応力吸収緩和膜９は、ダイヤフラム部の周辺部分にお
いてAl配線層５と同一の真空蒸着工程によりフィールド
酸化膜４表面に形成されている。応力吸収緩和膜９はA
l、又はSi添加Alからなり、0.5〜２μｍの厚さと25〜10
0μｍの幅とをもち、正方形のダイヤフラム部７の周縁
部に帯状に形成されている。The stress absorption relaxation film 9 is formed on the surface of the field oxide film 4 by the same vacuum deposition process as that of the Al wiring layer 5 in the peripheral portion of the diaphragm. The stress absorption relaxation film 9 is A
l or Si-added Al with a thickness of 0.5-2 μm and 25-10
It has a width of 0 μm and is formed in a band shape on the periphery of the square diaphragm portion 7.
パッシベーション膜６は、BPSG、SiNなどからなり、
0.5〜２μｍの厚さをもつ。パッシベーション膜６の内
側の端縁部60は応力吸収緩和膜９の表面上に形成されて
いる。The passivation film 6 is made of BPSG, SiN, etc.
It has a thickness of 0.5-2 μm. The inner edge portion 60 of the passivation film 6 is formed on the surface of the stress absorption relaxation film 9.
この実施例の半導体圧力センサは、例えば上述の先行
技術に開示されるような周知の製造プロセス製造できる
ので、製造工程の詳細説明は省略する。Since the semiconductor pressure sensor of this embodiment can be manufactured by a well-known manufacturing process as disclosed in, for example, the above-described prior art, detailed description of the manufacturing process is omitted.
この半導体圧力センサにおいて、アルミ製の応力吸収
緩和膜９は軟質で塑性変形しやすく、パッシベーション
膜６の端縁部60で生じる応力集中を緩和させる。In this semiconductor pressure sensor, the stress absorption and relaxation film 9 made of aluminum is soft and easily plastically deformed, and reduces the stress concentration generated at the edge 60 of the passivation film 6.
パッシベーション膜６の端縁部60近傍の熱応力分布を
FEMにより解析した結果を第３図に示す。なお、ダイヤ
フラム７の一辺は約1.4mm、パッシベーション膜６が被
着され集積回路部が設けられるシリコン基板１の周辺部
の幅を0.75mmとした。パッシベーション膜６は、0.4μ
ｍ厚のリンを含むSiO2膜とその上に0.6μｍ厚のSiN膜と
の２層膜とした。The thermal stress distribution near the edge 60 of the passivation film 6
FIG. 3 shows the results of analysis by FEM. The width of one side of the diaphragm 7 was about 1.4 mm, and the width of the peripheral portion of the silicon substrate 1 on which the passivation film 6 was provided and the integrated circuit portion was provided was 0.75 mm. The passivation film 6 has a thickness of 0.4 μm.
A two-layer film of a m-thick SiO 2 film containing phosphorus and a 0.6 μm-thick SiN film thereon was formed.
図中、（ａ）はダイヤフラム部７にもパッシベーショ
ン膜６を設けた場合、（ｂ）はダイヤフラム部７のパッ
シベーション膜６を除去した場合、（ｃ）は応力吸収緩
和膜９を設けた場合である。In the figure, (a) shows the case where the passivation film 6 is also provided on the diaphragm part 7, (b) shows the case where the passivation film 6 of the diaphragm part 7 is removed, and (c) shows the case where the stress absorption relaxation film 9 is provided. is there.
すなわち、アンプ回路部８のみにパッシベーション膜
６を配置した場合、ダイヤフラム部７上ではほとんど熱
応力を発生しないが、ダイヤフラム部７の周辺で応力集
中が生じかつ端縁部60において応力の変曲点が生じるこ
とがわかる。一部のピエゾ拡散ゲージ２は、ダイヤフラ
ム部７の周辺部に配置されるので、この応力集中の影響
を受けて特性が変化する。That is, when the passivation film 6 is disposed only in the amplifier circuit portion 8, almost no thermal stress is generated on the diaphragm portion 7, but stress concentration occurs around the diaphragm portion 7 and the inflection point of the stress is generated at the edge portion 60. It can be seen that this occurs. Since some of the piezo diffusion gauges 2 are arranged around the diaphragm 7, the characteristics change under the influence of the stress concentration.
第１図は本発明の一実施例を示す平面図、第２図はその
Ａ−Ａ′線矢視断面図、第３図はこの実施例及び従来例
におけるパッシベーション膜による応力分布を示す応力
分布図、第４図は従来の半導体圧力センサの一部断面図
である。 １……単結晶シリコン基板、２……ピエゾ拡散ゲージ、
４……フィールド酸化膜、５……アルミ配線層、６……
パッシベーション膜、７……ダイヤフラム部、８……ア
ンプ回路（集積回路部）、９……応力吸収緩和膜1 is a plan view showing one embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA 'of FIG. 1, and FIG. 3 is a stress distribution showing a stress distribution by a passivation film in this embodiment and a conventional example. FIG. 4 is a partial sectional view of a conventional semiconductor pressure sensor. 1 ... single crystal silicon substrate, 2 ... piezo diffusion gauge,
4 ... field oxide film, 5 ... aluminum wiring layer, 6 ...
Passivation film, 7 ... diaphragm part, 8 ... amplifier circuit (integrated circuit part), 9 ... stress absorption relaxation film
Claims (1)
して形成されるとともにピエゾ拡散ゲージが形成された
ダイヤフラム部と、該ダイヤフラム部の周辺において前
記単結晶シリコン基板の他主面に形成された集積回路部
とBPSG膜と窒化シリコン膜と、窒化シリコン膜及び酸化
シリコン膜からなる２層膜とのうちのいずれかからな
り、前記ダイヤフラム部以外の少なくとも前記集積回路
部の表面を覆って形成された集積回路部保護用のパッシ
ベーション膜と、前記パッシベーション膜よりも変形容
易な性質を有するとともに、前記ダイヤフラム部側の前
記パッシベーション膜の端縁部と前記単結晶シリコン基
板との間に位置して前記ダイヤフラム部の周縁部に沿い
つつ帯状に配設される応力吸収緩和膜とを備えることを
特徴とする半導体圧力センサ。1. A diaphragm portion formed by etching one main surface of a single crystal silicon substrate and having a piezo diffusion gauge formed thereon, and a diaphragm formed on the other main surface of the single crystal silicon substrate around the diaphragm portion. BPSG film, silicon nitride film, or a two-layer film composed of a silicon nitride film and a silicon oxide film, and is formed so as to cover at least the surface of the integrated circuit portion other than the diaphragm portion. And a passivation film for protecting the integrated circuit portion, which has properties that are easier to deform than the passivation film, and is located between the edge portion of the passivation film on the diaphragm side and the single crystal silicon substrate. And a stress absorption-reducing film disposed along the periphery of the diaphragm portion in a strip shape. Sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024649A JP2650455B2 (en) | 1990-02-02 | 1990-02-02 | Semiconductor pressure sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024649A JP2650455B2 (en) | 1990-02-02 | 1990-02-02 | Semiconductor pressure sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03229470A JPH03229470A (en) | 1991-10-11 |
| JP2650455B2 true JP2650455B2 (en) | 1997-09-03 |
Family
ID=12143991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024649A Expired - Lifetime JP2650455B2 (en) | 1990-02-02 | 1990-02-02 | Semiconductor pressure sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2650455B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408112A (en) * | 1991-06-03 | 1995-04-18 | Nippondenso Co., Ltd. | Semiconductor strain sensor having improved resistance to bonding strain effects |
| JPH0685287A (en) * | 1992-09-03 | 1994-03-25 | Mitsubishi Electric Corp | Semiconductor pressure sensor and its manufacture |
| JP3873454B2 (en) * | 1998-05-29 | 2007-01-24 | 株式会社デンソー | Semiconductor pressure sensor |
| JP3567094B2 (en) | 1999-02-09 | 2004-09-15 | 株式会社日立製作所 | Circuit built-in type sensor and pressure detecting device using the same |
| JP2007024589A (en) * | 2005-07-13 | 2007-02-01 | Hitachi Ltd | Gas flow rate measuring arrangement |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5533024A (en) * | 1978-08-28 | 1980-03-08 | Mitsubishi Electric Corp | Semiconductor device for converting pressure |
| JPS62144368A (en) * | 1985-12-19 | 1987-06-27 | Nec Corp | Protective film for semiconductor type pressure sensor |
| JPS62266875A (en) * | 1986-05-14 | 1987-11-19 | Nippon Denso Co Ltd | Semiconductor pressure sensor |
-
1990
- 1990-02-02 JP JP2024649A patent/JP2650455B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03229470A (en) | 1991-10-11 |
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