JP2646711B2 - Method for manufacturing multilayer printed wiring board - Google Patents

Method for manufacturing multilayer printed wiring board

Info

Publication number
JP2646711B2
JP2646711B2 JP63277834A JP27783488A JP2646711B2 JP 2646711 B2 JP2646711 B2 JP 2646711B2 JP 63277834 A JP63277834 A JP 63277834A JP 27783488 A JP27783488 A JP 27783488A JP 2646711 B2 JP2646711 B2 JP 2646711B2
Authority
JP
Japan
Prior art keywords
inner layer
printed wiring
forming
wiring board
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63277834A
Other languages
Japanese (ja)
Other versions
JPH02122699A (en
Inventor
雅敏 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP63277834A priority Critical patent/JP2646711B2/en
Publication of JPH02122699A publication Critical patent/JPH02122699A/en
Application granted granted Critical
Publication of JP2646711B2 publication Critical patent/JP2646711B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の製造方法に関し、特に電源
・地気層となる内層板の製造方法を含む多層印刷配線板
の製造方法に関する。
The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly, to a method for manufacturing a multilayer printed wiring board including a method for manufacturing an inner layer board serving as a power supply / ground layer.

〔従来の技術〕[Conventional technology]

近年、超大型コンピュータ分野においては、演算速度
向上と省スペース化の目的による実装密度の向上が著し
く、その心臓部ともいえる中央演算処理装装をわずか1
枚の印刷配線板に収めたものが登場している。かかる用
途に用いられる印刷配線板では、高速化のために、EC
L、CML等の消費電力が大きく、論理振幅の小さい論理素
子があり、電源・地気層に用いられる導体層の厚みが総
計で1mm以上になることも珍しくない。この場合、通常
用いられる銅張積層板で銅箔をエッチングして電源・地
気層のパターンを形成しようとすると、パターン形成精
度が悪化し、微細加エが困難になり高密度化できなくな
るという欠点があり、これを解消する手段として、特願
昭62−299168号のような両面銅張積層板にドリル加工に
より共通クリアランス部を作成することにより、パター
ン精度の向上をはかり、電力供給の安定化と、高密度化
を達成した例がある。
In recent years, in the field of ultra-large computers, there has been a remarkable increase in the mounting density for the purpose of improving the operation speed and saving space.
Some printed circuit boards have appeared. In printed wiring boards used for such purposes, EC
There is a logic element such as L and CML that consumes a large amount of power and has a small logic amplitude, and it is not unusual for the total thickness of the conductor layers used for the power supply and the geosphere to be 1 mm or more. In this case, when the copper foil is etched with a commonly used copper-clad laminate to form a power supply / ground layer pattern, the pattern formation accuracy is deteriorated, and it becomes difficult to perform fine processing, and the density cannot be increased. There are drawbacks, and as a means to solve this, by creating a common clearance part by drilling on a double-sided copper-clad laminate as disclosed in Japanese Patent Application No. 62-299168, the pattern accuracy is improved and the power supply is stabilized. There is an example of achieving higher density and higher density.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、上述した銅張積層板にドリル加工によ
り共通クリアランス部を形成する方法では、前記共通ク
リアランス部分が樹脂分のみで埋め込まれており、多層
化成形後の状態では、樹脂に残留応力が生じ、さらに、
樹脂の機械的強度が銅箔やガラスクロスに比べて弱いた
め、貫通孔切削応力が樹脂に集中するため、ここにクラ
ックを発生し、液体処理工程の際の残渣がクラックに残
留し、絶縁不良の原因となっていた。
However, in the above-described method of forming a common clearance portion by drilling in a copper-clad laminate, the common clearance portion is embedded only with a resin component, and in a state after multi-layer molding, residual stress occurs in the resin, further,
Since the mechanical strength of the resin is weaker than that of copper foil or glass cloth, the through-hole cutting stress concentrates on the resin, which causes cracks, and residues during the liquid treatment process remain in the cracks, resulting in poor insulation. Was the cause.

本発明の目的は、絶縁不良のない多層印刷配線板の製
造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board free from insulation failure.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は、両面銅張積層板の所定の位置にドリル加工
により共通クリアランス部を形成する工程と、前記両面
銅張積層板上の共通クリアランス部を除いた所定の位置
にエッチングによる非共通クリアランス部を形成し電源
・地気層となる内層板を形成する工程と、該内層板の両
面にプリプレグを介して配設し加熱積層する工程とを有
する多層印刷配線板の製造方法において、前記内層板を
形成後、外層導体を配設する前に前記内層板の表面にフ
ィラー入り絶縁樹脂を塗布し加熱加圧して絶縁層を成形
する工程を含んで構成されている。
The present invention provides a step of forming a common clearance portion at a predetermined position of a double-sided copper-clad laminate by drilling, and a step of forming a non-common clearance portion by etching at a predetermined position on the double-sided copper-clad laminate excluding the common clearance portion. Forming an inner layer plate to be a power supply / ground layer, and a step of arranging and heating and laminating both sides of the inner layer plate via prepregs, wherein the inner layer plate is formed. After the formation, before the outer layer conductor is provided, a step of applying a filler-containing insulating resin to the surface of the inner layer plate and applying heat and pressure to form an insulating layer.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。第1図(a)〜(d)は、本発明の第1実施例の製
造方法を説明する工程順に示した断面図である。まず、
第1図(a)に示すように、所要の厚みの銅箔1(例え
ば200μm)を用いた両面銅張積層板2を用意し、ドリ
ルによって貫通穴を加工する事により、共通クリアラン
ス部3を形成する。次に、第1図(b)に示すように、
ホトエッチング法によって非共通クリアランス部4を形
成して、電源・地気層となる内層板5を得る。次に、第
1図(c)に示すように、このようにして得られた内層
板5の表面にフイラー入り絶縁樹脂6をスクリーン印刷
により両面から塗布し、共通クリアランス部3及び非共
通クリアランス部4をフィラー入り絶縁樹脂6で充てん
し、真空プレス(オートクレーブ)により加熱加圧し
て、フィラー入り絶縁樹脂6からなる絶縁層の形成され
た内層板7を得る。このフイラー入り絶縁樹脂6は、エ
ポキシ樹脂の中にフィラーとして平均粒径1μmの水酸
化アルミニウムを40%添加したものである。次に、第1
図(d)に示すように、内層板7の両面にプリプレグ8
を介して外層導体層9を加熱積層した後、穴あけ、スル
ホールメッキ、エッチングする事により、多層印刷配線
板10を得た。
Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (d) are cross-sectional views showing a manufacturing method according to a first embodiment of the present invention in the order of steps for explaining the manufacturing method. First,
As shown in FIG. 1 (a), a double-sided copper-clad laminate 2 using a copper foil 1 (for example, 200 μm) of a required thickness is prepared, and a through-hole is machined by a drill to form a common clearance portion 3. Form. Next, as shown in FIG.
The non-common clearance portion 4 is formed by a photo-etching method to obtain an inner plate 5 serving as a power supply / ground layer. Next, as shown in FIG. 1 (c), an insulating resin 6 containing a filler is applied from both sides by screen printing to the surface of the inner layer plate 5 thus obtained, and the common clearance portion 3 and the non-common clearance portion are applied. 4 is filled with an insulating resin 6 containing a filler, and heated and pressed by a vacuum press (autoclave) to obtain an inner layer plate 7 having an insulating layer made of the insulating resin 6 containing a filler. This filler-containing insulating resin 6 is obtained by adding 40% of aluminum hydroxide having an average particle diameter of 1 μm as a filler to an epoxy resin. Next, the first
As shown in FIG.
After heating and laminating the outer conductor layer 9 through the above, a multilayer printed wiring board 10 was obtained by drilling, through-hole plating and etching.

第2の実施例は、第1の実施例の第1図(c)におい
て、内層板5の表面に塗布するフィラー入り絶縁樹脂6
として、変性ポリイミド樹脂にシリカを10%添加したも
のを用い、第1の実施例と同様にフィラー入り絶縁樹脂
6を印刷後、真空プレス(オートクレーブ)により、加
熱加圧してフィラー入り絶縁樹脂6からなる絶縁層の形
成された内層板7を形成し、内層板7の両面にプリプレ
グ8を介して外層導体層9を加熱した後、穴あけ、スル
ホールメッキ、エッチングする事により、多層印刷配線
板10を得た。
The second embodiment is different from the first embodiment in FIG. 1 (c) in that the filler-containing insulating resin 6 applied to the surface of the inner layer plate 5 is used.
As described in the first embodiment, a resin obtained by adding 10% of silica to a modified polyimide resin is used to print the filler-containing insulating resin 6, and then heated and pressed by a vacuum press (autoclave) to remove the filler-containing insulating resin 6 from the filler-containing insulating resin 6. After forming an inner layer plate 7 having an insulating layer formed thereon, heating the outer layer conductor layer 9 via prepregs 8 on both sides of the inner layer plate 7, drilling, through-hole plating, and etching to form the multilayer printed wiring board 10. Obtained.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、内層板の表面に無機材
料フィラーを添加した絶縁樹脂を塗布し、共通クリアラ
ンス及び非共通クリアランス部を充てんし、加熱加圧し
て成形後外層導体を加熱積層したため、貫通穴形成時に
発生するクリアランス内のクラック発生が防止でき、絶
縁不良のない多層印刷配線板が得られる効果がある。
As described above, the present invention applies an insulating resin added with an inorganic material filler to the surface of the inner layer plate, fills the common clearance and the non-common clearance portion, and heat-presses the outer layer conductor after forming, so that the outer layer conductor is heated and laminated. It is possible to prevent the occurrence of cracks in the clearance generated at the time of forming the through holes, and to obtain a multilayer printed wiring board free from insulation failure.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(d)は本発明の第1の実施例の製造方
法を説明するエ程順に示した断面図である。 1……銅箔、2……両面銅張積層板、3……共通クリア
ランス部、4……非共通クリアランス部、5,7……内層
板、6……フィラー入り絶縁樹脂、8……プリプレグ、
9……外層導体層、10……多層印刷配線板。
1 (a) to 1 (d) are cross-sectional views showing a manufacturing method according to a first embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1 ... Copper foil, 2 ... Double-sided copper-clad laminate, 3 ... Common clearance part, 4 ... Non-common clearance part, 5, 7 ... Inner plate, 6 ... Filler insulating resin, 8 ... Prepreg ,
9 ... Outer conductor layer, 10 ... Multilayer printed wiring board.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】両面銅張積層板の所定の位置にドリル加工
により共通クリアランス部を形成する工程と、前記両面
銅張積層板上の共通クリアランス部を除いた所定の位置
にエッチングにより非共通クリアランス部を形成し電源
・地気層となる内層板を形成する工程と、該内層板の両
面にプリプレグを介して外層導体を配設し加熱積層する
工程とを有する多層印刷配線板の製造方法において、前
記内層板を形成後、前記外層導体を配設する前に前記内
層板の表面にフィラー入り絶縁樹脂を塗布し加熱加圧し
て絶縁層を成形する工程を含む事を特徴とする多層印刷
配線板の製造方法。
1. A step of forming a common clearance portion at a predetermined position on a double-sided copper-clad laminate by drilling, and a non-common clearance by etching at a predetermined position on the double-sided copper-clad laminate excluding the common clearance portion. Forming a part and forming an inner layer plate to be a power supply / ground layer, and a step of arranging an outer layer conductor on both sides of the inner layer plate via a prepreg and heating and laminating the multilayer printed wiring board. Forming the inner layer plate, and before disposing the outer layer conductor, applying a filler-containing insulating resin to the surface of the inner layer plate, and applying heat and pressure to form an insulating layer. Plate manufacturing method.
JP63277834A 1988-11-01 1988-11-01 Method for manufacturing multilayer printed wiring board Expired - Lifetime JP2646711B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63277834A JP2646711B2 (en) 1988-11-01 1988-11-01 Method for manufacturing multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63277834A JP2646711B2 (en) 1988-11-01 1988-11-01 Method for manufacturing multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH02122699A JPH02122699A (en) 1990-05-10
JP2646711B2 true JP2646711B2 (en) 1997-08-27

Family

ID=17588916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63277834A Expired - Lifetime JP2646711B2 (en) 1988-11-01 1988-11-01 Method for manufacturing multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2646711B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49127164A (en) * 1973-04-09 1974-12-05
JPS55121696A (en) * 1979-03-13 1980-09-18 Tokyo Shibaura Electric Co Method of fabricating multilayer printed circuit board
JPS61154096A (en) * 1984-12-26 1986-07-12 住友ベークライト株式会社 Manufacture of multilayer printed wiring board
JPS61296799A (en) * 1985-06-25 1986-12-27 日本電気株式会社 Multilayer printed wiring board

Also Published As

Publication number Publication date
JPH02122699A (en) 1990-05-10

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