JP2621722B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2621722B2
JP2621722B2 JP3340928A JP34092891A JP2621722B2 JP 2621722 B2 JP2621722 B2 JP 2621722B2 JP 3340928 A JP3340928 A JP 3340928A JP 34092891 A JP34092891 A JP 34092891A JP 2621722 B2 JP2621722 B2 JP 2621722B2
Authority
JP
Japan
Prior art keywords
insulating
case
gas
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3340928A
Other languages
Japanese (ja)
Other versions
JPH05175382A (en
Inventor
義夫 高木
和嘉 中山
富美子 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3340928A priority Critical patent/JP2621722B2/en
Publication of JPH05175382A publication Critical patent/JPH05175382A/en
Application granted granted Critical
Publication of JP2621722B2 publication Critical patent/JP2621722B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve insulating characteristics and cooling performance by filling highly insulating gas and helium gas. CONSTITUTION:A silicon chip 27 and an insulating case 30 which covers aluminum wire 28 and 29 are adhered on an insulating board 22. The insulating case 30 is filled with highly insulating gas and helium gas. The highly insulating gas ensures insulation between the aluminum wire 28 and 29 and on a pattern and eliminates silicon gel. Thus, electrodes 32 and 33 are linearly formed, the production cost is reduced and the aluminum wire 28 and 29 are prevented from easily making contact and the degree of freedom in designing and assembling the device is increased.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
電子機器などに使用される電力用半導体モジュールのシ
リコンゲルの膨張、収縮に伴なう応力を受けないように
した半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a silicon gel of a power semiconductor module used in an electronic device or the like is not subjected to a stress accompanying expansion and contraction of silicon gel. .

【０００２】[0002]

【従来の技術】近年、電子機器の発展は著しく、また、
その信頼性向上が要求されている。従来の半導体装置を
図２によって説明する。2. Description of the Related Art In recent years, the development of electronic devices has been remarkable.
There is a demand for improved reliability. A conventional semiconductor device will be described with reference to FIG.

【０００３】図２は従来の半導体装置としてのトランジ
スタモジュールの断面図であり、放熱板１上に、絶縁基
板（セラミック基板または窒化アルミ基板）２を搭載さ
せる。絶縁基板２は表側にベース電極３，コレクタ電極
４，エミッタ電極５が、裏側には放熱用電極６が付いた
厚銅箔基板を一例として示した。FIG. 2 is a sectional view of a transistor module as a conventional semiconductor device. An insulating substrate (ceramic substrate or aluminum nitride substrate ) 2 is mounted on a heat sink 1. As an example of the insulating substrate 2, a thick copper foil substrate having a base electrode 3, a collector electrode 4, and an emitter electrode 5 on the front side and a heat radiation electrode 6 on the back side is shown.

【０００４】絶縁基板２のコレクタ電極４上にシリコン
チップ７を搭載させ、放熱板１，絶縁基板２，シリコン
チップ７を同時にはんだ付けする。（はんだは図示せ
ず）。その後、アルミニウムワイヤ８，９のボンディン
グを行ない、Ｓベンド状に形成されたベース電極（外部
電極端子）１０およびエミッタ電極（外部電極端子）１
１を絶縁基板２上のベース電極３とエミッタ電極５上に
はんだ付け（はんだは図示せず）して取り出す。その
後、ケース１２を放熱板１の接着剤（図示せず）を使用
して接着する。[0004] A silicon chip 7 is mounted on the collector electrode 4 of the insulating substrate 2, and the heat sink 1, the insulating substrate 2 and the silicon chip 7 are simultaneously soldered. (Solder not shown). Thereafter, aluminum wires 8 and 9 are bonded to form a base electrode (external electrode terminal) 10 and an emitter electrode (external electrode terminal) 1 formed in an S-bend shape.
1 is soldered onto the base electrode 3 and the emitter electrode 5 on the insulating substrate 2 (the solder is not shown) and is taken out. Thereafter, the case 12 is bonded using an adhesive (not shown) for the heat sink 1.

【０００５】ベース電極１０およびエミッタ電極１１
は、ケースまたは蓋（図示せず）にアウトサートまたは
インサートして固定してもよい。蓋に前記各電極１０，
１１をインサートまたはアウトサートしている場合は、
治具（図示せず）で蓋の外周を固定して各電極１０，１
１をはんだ付けする。その後、ケース１２を放熱板１に
接着剤（図示せず）を使用して接着する。[0005] Base electrode 10 and emitter electrode 11
May be outsert or inserted into a case or lid (not shown) and secured. Each electrode 10,
If you insert or outsert 11,
Fix the outer periphery of the lid with a jig (not shown) and
Solder 1 Thereafter, the case 12 is bonded to the heat sink 1 using an adhesive (not shown).

【０００６】ケース１２に前記各電極１０，１１をイン
サートまたはアウトサートしている場合は、各電極１
０，１１のはんだ付けをすると同時にケース１２も接着
剤（図示せず）を使用して接着する。その後、シリコン
ゲル１３をＳベンド形状のベース電極１０，エミッタ電
極１１のＳベンド上部まで注入しキュアを行なう。引き
続きエポキシ樹脂１４を注入しキュアを行なう。When the electrodes 10 and 11 are inserted or outsert into the case 12, each electrode 1
At the same time as the soldering of 0 and 11, the case 12 is also bonded using an adhesive (not shown). Thereafter, the silicon gel 13 is injected to the upper part of the S-bend of the S-bend base electrode 10 and the emitter electrode 11, and curing is performed. Subsequently, epoxy resin 14 is injected and cured.

【０００７】[0007]

【発明が解決しようとする課題】しかるに、上述したよ
うに構成された従来の半導体装置では、シリコンゲル１
３の熱膨張係数はエポキシ樹脂１４の熱膨張係数よりも
１桁大きく、エポキシ樹脂１４に固定されたベース電極
１０およびエミッタ電極１１のはんだ付け部がシリコン
ゲル１３の熱膨張に伴い引っ張られて外れる可能性があ
る。However, in the conventional semiconductor device configured as described above, the silicon gel 1
The coefficient of thermal expansion of 3 is one order of magnitude greater than the coefficient of thermal expansion of the epoxy resin 14, and the soldered portions of the base electrode 10 and the emitter electrode 11 fixed to the epoxy resin 14 are pulled off due to the thermal expansion of the silicon gel 13. there is a possibility.

【０００８】また、モジュールの実使用およびヒートサ
イクル等により、各電極１０，１１のはんだ付け面に引
張り，圧縮の力が加わりはんだの疲労等につながりはん
だ付け面が剥がれる等の問題が生じる。In addition, due to the actual use of the module and the heat cycle, a tensile or compressive force is applied to the soldering surfaces of the electrodes 10 and 11, which leads to solder fatigue and the like, causing problems such as peeling of the soldering surfaces.

【０００９】これらの問題点を解決するために一般的に
Ｓ字形の電極を用いるが、電極が高価になりアルミワイ
ヤ等の接触および設計的にはスペースの制約，組立上種
々の問題点が生じ易くなる。In order to solve these problems, an S-shaped electrode is generally used. However, the electrode becomes expensive, and there are restrictions in terms of contact with aluminum wires and the like in terms of space, design, and various problems in assembly. It will be easier.

【００１０】本発明は、上述した問題点を解消するため
になされたもので、シリコンゲルの熱膨張の影響を受け
難くすると共に、電極の形状をシンプルにし、かつ安価
となる他、組立上、電極とワイヤとの接触等の組立およ
び設計上の制約をなくし、さらに、チップ周辺の絶縁特
性や放熱性を向上させ、高信頼性が得られる半導体装置
を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention makes it less susceptible to the thermal expansion of the silicon gel, simplifies the shape of the electrode, and reduces the cost. It is an object of the present invention to obtain a semiconductor device that eliminates restrictions on assembly and design such as contact between an electrode and a wire, improves insulation properties and heat dissipation around a chip, and obtains high reliability.

【００１１】[0011]

【課題を解決するための手段】本発明に係る半導体装置
は、絶縁基板上に、シリコンチップおよびワイヤボンデ
ィング部分を覆う絶縁材製気密封止用ケースを接着し、
このケース内に、高絶縁性ガスおよびヘリウムガスを封
入したものである。また、本発明に係る半導体装置は、
電極パターン上のボンディングワイヤとの接合部と、外
部接続用電極との接合部との間に、絶縁ケースの開口端
面を接合したものである。 According to a semiconductor device of the present invention, an airtight sealing case made of an insulating material covering a silicon chip and a wire bonding portion is adhered on an insulating substrate.
In this case, a highly insulating gas and a helium gas are sealed. Further, the semiconductor device according to the present invention includes:
The joint with the bonding wire on the electrode pattern
Opening end of the insulating case between the junction with the connection electrode
The surfaces are joined.

【００１２】[0012]

【作用】高絶縁性ガスによりボンディングワイヤ間やパ
ターン上での絶縁性を確保できシリコンゲルが不要とな
る。また、ケース内のボンディングワイヤやパターンが
ヘリウムガスに触れるためにそれらの熱が放熱され易く
なる。また、絶縁ケースの開口端面は平面上に接合され
る。 The insulating property between the bonding wires and the pattern can be ensured by the high insulating gas, and the silicon gel is not required. Further, since the bonding wires and patterns in the case come into contact with the helium gas, the heat thereof is easily dissipated. The open end face of the insulating case is joined on a flat surface.
You.

【００１３】[0013]

【実施例】以下、本発明の一実施例を図１によって詳細
に説明する。図１は本発明に係る半導体装置としてのト
ランジスタモジュールの断面図である。図１において、
２１は放熱板で、この放熱板２１上に絶縁基板（セラミ
ック基板または窒化アルミ基板）２２が搭載されてい
る。絶縁基板２２は、表側にベース電極２３，コレクタ
電極２４，エミッタ電極２５が形成され、裏側に放熱用
電極２６が形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIG. FIG. 1 is a sectional view of a transistor module as a semiconductor device according to the present invention. In FIG.
Reference numeral 21 denotes a heat sink on which an insulating substrate (ceramic substrate or aluminum nitride substrate ) 22 is mounted. The insulating substrate 22 has a base electrode 23, a collector electrode 24, and an emitter electrode 25 formed on the front side, and a heat radiation electrode 26 formed on the back side.

【００１４】絶縁基板２２上のコレクタ電極２４上には
シリコンチップ２７が搭載され、放熱板２１，絶縁基板
２２，シリコンチップ２７が同時にはんだ付けされてい
る（はんだは図示せず）。A silicon chip 27 is mounted on the collector electrode 24 on the insulating substrate 22, and the heat sink 21, the insulating substrate 22, and the silicon chip 27 are simultaneously soldered (solder is not shown).

【００１５】２８はベース用のアルミニウムワイヤ、２
９はエミッタ用のアルミニウムワイヤである。Reference numeral 28 denotes an aluminum wire for the base, 2
9 is an aluminum wire for the emitter.

【００１６】３０はシリコンチップ２７およびワイヤボ
ンディング部分を覆うための絶縁ケースで、この絶縁ケ
ース３０はセラミックまたは窒化アルミなどの絶縁材か
らなり、箱蓋状に形成されている。そして、この絶縁ケ
ース３０は絶縁基板２２上に接着剤（図示せず）によっ
て熱接着されている。なお、絶縁基板２２とこの絶縁ケ
ース３０の接着部は気密を保つように接着されている。Reference numeral 30 denotes an insulating case for covering the silicon chip 27 and the wire bonding portion. The insulating case 30 is made of an insulating material such as ceramic or aluminum nitride, and is formed in a box lid shape. The insulating case 30 is thermally bonded on the insulating substrate 22 by an adhesive (not shown). The bonding portion between the insulating substrate 22 and the insulating case 30 is bonded so as to maintain airtightness.

【００１７】３１は前記絶縁ケース３０の上部ガス導入
口を塞ぐためのキャップで、このキャップ３１は、絶縁
ケース３０内に高絶縁性ガスとヘリウムガスを導入した
後に上部ガス導入口に嵌入されて絶縁ケース３０に固着
されている。Reference numeral 31 denotes a cap for closing the upper gas inlet of the insulating case 30. The cap 31 is inserted into the upper gas inlet after introducing a highly insulating gas and helium gas into the insulating case 30. It is fixed to the insulating case 30.

【００１８】前記高絶縁性ガスとしては、本実施例では
６フッ化硫黄ガスを用いた。なお、６フッ化硫黄ガスと
ヘリウムガスとの混合割合としては、ヘリウムガスを６
０％〜９０％とすると、双方のガスの特性をより確実に
活用できる。混合ガスを図中符号Ａで示す。In the present embodiment, a sulfur hexafluoride gas was used as the highly insulating gas. The mixing ratio of the sulfur hexafluoride gas and the helium gas is 6
If it is 0% to 90%, the characteristics of both gases can be utilized more reliably. The mixed gas is indicated by reference symbol A in the figure.

【００１９】３２は前記ベース電極２３にはんだ付けさ
れたベース電極、３３は前記エミッタ電極２５にはんだ
付けされたエミッタ電極で、これらの電極３２，３３は
直線的に形成されている。Reference numeral 32 denotes a base electrode soldered to the base electrode 23, and reference numeral 33 denotes an emitter electrode soldered to the emitter electrode 25. These electrodes 32 and 33 are formed linearly.

【００２０】３４は半導体装置の外囲器を構成するケー
スで、このケース３４は放熱板２１に接着されており、
その内部には、エポキシ樹脂３５が注入されキュアされ
ている。Reference numeral 34 denotes a case constituting an envelope of the semiconductor device. The case 34 is adhered to the heat sink 21.
An epoxy resin 35 is injected into the inside and cured.

【００２１】このように構成された半導体装置を組立て
るには、先ず、絶縁ケース３０を絶縁基板２２に接着し
た後に絶縁ケース３０内に高絶縁性ガスとヘリウムガス
を封入し、その後、ケース３４を放熱板２１に接着剤に
よって接着する。In order to assemble the semiconductor device configured as described above, first, the insulating case 30 is bonded to the insulating substrate 22 and then a high insulating gas and a helium gas are sealed in the insulating case 30. It is adhered to the heat sink 21 with an adhesive.

【００２２】次に、エポキシ樹脂３５をケース３４内に
注入し、キュアさせる。このようにして樹脂封止された
半導体装置が得られる。Next, an epoxy resin 35 is injected into the case 34 and cured. Thus, a resin-sealed semiconductor device is obtained.

【００２３】したがって、高絶縁性ガスによりアルミニ
ウムワイヤ２８，２９間やパターン上での絶縁性を確保
できるから、本発明に係る半導体装置では熱膨張係数の
大きなシリコンゲルが不要となる。また、絶縁ケース３
０内のアルミニウムワイヤ２８，２９やパターンがヘリ
ウムガスに触れるためにそれらの熱が放熱され易くな
る。Accordingly, the insulating property between the aluminum wires 28 and 29 and the pattern can be ensured by the high insulating gas, so that the semiconductor device according to the present invention does not require a silicon gel having a large thermal expansion coefficient. Insulating case 3
Since the aluminum wires 28 and 29 and the pattern in 0 come into contact with helium gas, their heat is easily radiated.

【００２４】なお、本実施例では絶縁ケース３０をセラ
ミックあるいは窒化アルミによって形成した例について
説明したが、絶縁ケース３０の材質は、ファインセラミ
ックスまたはエンジニアリングプラスチック等でもよ
い。Although the present embodiment has been described with respect to an example in which the insulating case 30 is made of ceramic or aluminum nitride, the material of the insulating case 30 may be fine ceramics or engineering plastic.

【００２５】また、本実施例では絶縁ケース３０をエポ
キシ樹脂３５で覆った例を示したが、エポキシ樹脂３５
は必ずしも必要とするものではなく、外囲器となるケー
ス３４が絶縁ケースを兼ねるように形成し、そのケース
３４内に高絶縁性ガスとヘリウムガスの混合ガスを封入
したものであっても同等の効果が得られる。In this embodiment, the insulating case 30 is covered with the epoxy resin 35.
Is not always necessary, and even if the case 34 serving as an envelope is formed so as to also serve as an insulating case and a mixed gas of a highly insulating gas and helium gas is sealed in the case 34, The effect of is obtained.

【００２６】さらに、封入ガスの圧力としては、外部か
らの水分やガスの浸入を完全に防止できるように、大気
圧より高くすることもできる。なお、高絶縁性ガスとし
ては、空気とすることもできる。Further, the pressure of the sealed gas can be set higher than the atmospheric pressure so that intrusion of moisture or gas from the outside can be completely prevented. Note that air may be used as the highly insulating gas.

【００２７】[0027]

【発明の効果】以上説明したように本発明に係る半導体
装置は、絶縁基板上に、シリコンチップおよびワイヤボ
ンディング部分を覆う絶縁材製気密封止用ケースを接着
し、このケース内に、高絶縁性ガスおよびヘリウムガス
を封入したため、高絶縁性ガスによりボンディングワイ
ヤ間やパターン上での絶縁性を確保できシリコンゲルが
不要となる。As described above, in the semiconductor device according to the present invention, an airtight sealing case made of an insulating material covering a silicon chip and a wire bonding portion is bonded on an insulating substrate, and a high insulating case is provided in the case. Since the insulating gas and the helium gas are sealed, the insulating property between the bonding wires and on the pattern can be secured by the high insulating gas, and the silicon gel is not required.

【００２８】したがって、外部電極を直線的に形成して
その製造コストを低く抑えることができると共に、ボン
ディングワイヤが接触し難くなって設計上，組立上の自
由度が増えるようになる。また、高絶縁性ガスでシリコ
ンチップやワイヤボンディング部分が封止されるため
に、絶縁特性が著しく向上するという効果も得られる。Therefore, the external electrodes can be formed linearly to reduce the manufacturing cost, and it is difficult for the bonding wires to come into contact, so that the degree of freedom in design and assembly is increased. Further, since the silicon chip and the wire bonding portion are sealed with the high insulating gas, the effect of significantly improving the insulating characteristics can be obtained.

【００２９】さらに、ケース内のボンディングワイヤや
パターンがヘリウムガスに触れるためにそれらの熱が放
熱され易くなるので、上述した絶縁特性向上効果に加え
て冷却効果をも向上できるから、信頼性が向上すると共
に、半導体装置の大容量化を図ることができる。Further, since the bonding wires and patterns in the case come into contact with the helium gas, the heat thereof is easily radiated, so that the cooling effect can be improved in addition to the above-mentioned effect of improving the insulating properties, so that the reliability is improved. In addition, the capacity of the semiconductor device can be increased.

【００３０】また、本発明に係る半導体装置は、電極パ
ターン上のボンディングワイヤとの接合部と、外部接続
用電極との接合部との間に、絶縁ケースの開口端面を接
合したため、絶縁ケースの開口端面は平面上に接合され
る構成となり、このため絶縁ケースによる密閉が容易
で、かつ構成が簡単にもかかわらず密閉の信頼性を容易
に向上させることができる。 Further , the semiconductor device according to the present invention has an electrode pad.
Connection with bonding wire on turn and external connection
Connect the open end surface of the insulating case to the joint with the
Because of this, the open end face of the insulating case is
Configuration, which makes it easy to seal with an insulating case.
Easy and reliable sealing despite simple configuration
Can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体装置としてのトランジスタ
モジュールの断面図である。FIG. 1 is a sectional view of a transistor module as a semiconductor device according to the present invention.

【図２】従来の半導体装置としてのトランジスタモジュ
ールの断面図である。FIG. 2 is a cross-sectional view of a transistor module as a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

２１ 放熱板 ２２ 絶縁基板 ２４ シリコンチップ ２８ アルミニウムワイヤ ２９ アルミニウムワイヤ ３０ 絶縁ケース ３２ ベース電極 ３３ エミッタ電極 Reference Signs List 21 radiator plate 22 insulating substrate 24 silicon chip 28 aluminum wire 29 aluminum wire 30 insulating case 32 base electrode 33 emitter electrode

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 放熱板上に絶縁基板が接着され、前記絶
縁基板上にシリコンチップと、このシリコンチップにボ
ンディングワイヤを介して接続された外部接続用電極と
が搭載された半導体装置において、前記絶縁基板上に、
シリコンチップおよびワイヤボンディング部分を覆う絶
縁材製気密封止用ケースを接着し、このケース内に、高
絶縁性ガスおよびヘリウムガスを封入したことを特徴と
する半導体装置。1. A semiconductor device having an insulating substrate adhered on a heat sink, a silicon chip mounted on the insulating substrate, and an external connection electrode connected to the silicon chip via a bonding wire, On an insulating substrate,
A semiconductor device characterized by bonding an airtight sealing case made of an insulating material covering a silicon chip and a wire bonding portion, and enclosing a highly insulating gas and a helium gas in the case. 【請求項２】 請求項１記載の半導体装置において、電
極パターン上のボンディングワイヤとの接合部と、外部
接続用電極との接合部との間に、絶縁ケースの開口端面
を接合したことを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein
The joint with the bonding wire on the pole pattern and the outside
Open the end face of the insulation case between the joint with the connection electrode.
A semiconductor device characterized by bonding.
JP3340928A 1991-12-24 1991-12-24 Semiconductor device Expired - Lifetime JP2621722B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3340928A JP2621722B2 (en) 1991-12-24 1991-12-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3340928A JP2621722B2 (en) 1991-12-24 1991-12-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05175382A JPH05175382A (en) 1993-07-13
JP2621722B2 true JP2621722B2 (en) 1997-06-18

Family

ID=18341590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3340928A Expired - Lifetime JP2621722B2 (en) 1991-12-24 1991-12-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2621722B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036014A (en) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd Circuit device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014033119A (en) * 2012-08-06 2014-02-20 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036014A (en) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd Circuit device

Also Published As

Publication number Publication date
JPH05175382A (en) 1993-07-13

Similar Documents

Publication Publication Date Title
US7355547B2 (en) Vehicle-mounted millimeter wave radar device, millimeter wave radar module, and manufacturing method thereof
US6177725B1 (en) Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
JPH0878574A (en) Semiconductor device and manufacturing method thereof
US3999285A (en) Semiconductor device package
US7868430B2 (en) Semiconductor device
JPH03233334A (en) Semiconductor pressure sensor
JP2621722B2 (en) Semiconductor device
JPH0661372A (en) Hybrid ic
JPH06188335A (en) Resin sealed semiconductor device
JP6887476B2 (en) Semiconductor power module
JPH05267503A (en) Semiconductor device
JPS5837694B2 (en) semiconductor equipment
JPH02203555A (en) Semiconductor device
JP2674273B2 (en) Electronic ignition device for internal combustion engine
JP2710207B2 (en) Semiconductor device and manufacturing method thereof
JPH0513618A (en) Semiconductor device
JP2874431B2 (en) Resin-sealed semiconductor device
JP2549633Y2 (en) Power module
JPH0370163A (en) Semiconductor device
JPH113972A (en) Semiconductor device
JPS6226847A (en) Hermetic seal semiconductor device
JPH05160317A (en) Structure for assembling semiconductor device
JPH0831986A (en) Semiconductor device having heatsink
JPS61240664A (en) Semiconductor device
JPH0786497A (en) Intelligent power module