JP2586162B2 - Switching element parallel connection method - Google Patents
Switching element parallel connection methodInfo
- Publication number
- JP2586162B2 JP2586162B2 JP2021467A JP2146790A JP2586162B2 JP 2586162 B2 JP2586162 B2 JP 2586162B2 JP 2021467 A JP2021467 A JP 2021467A JP 2146790 A JP2146790 A JP 2146790A JP 2586162 B2 JP2586162 B2 JP 2586162B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- current
- parallel connection
- switching elements
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Protection Of Static Devices (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電力変換装置等において並列接続状態で使
用される電力用スイッチング素子の電流分担率の平衡を
図る並列接続方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel connection method for balancing a current sharing ratio of power switching elements used in a parallel connection state in a power converter or the like.
〔従来の技術〕 並列接続されたスイッチング素子それぞれの電流分担
率の平衡を図るための従来の並列接続方法としては第３
図の配線構成図に示す如きものが知られている。第４図
は第３図に対応する回路図である。[Prior Art] As a conventional parallel connection method for balancing the current sharing ratio of each switching element connected in parallel, there is a third method.
As shown in the wiring configuration diagram of FIG. FIG. 4 is a circuit diagram corresponding to FIG.
第３図は複数の電力用スイッチング素子として２個の
パワートランジスタを用いた例であり、該両トランジス
タの外部主回路及び制御回路配線におけるインピーダン
スの均等化を図るために配線の対称化等による配線の経
路と長さとに関する均等化を図ったものである。FIG. 3 shows an example in which two power transistors are used as a plurality of power switching elements. In order to equalize the impedance of the external main circuit and the control circuit wiring of both transistors, the wiring is made symmetrical or the like. Of the path and the length of the path.
第３図において、１と２とはパワートランジスタ、Ｂ
とＣとＥとはそれぞれ該両トランジスタのベース端子と
コレクタ端子とエミッタ端子とであり、3aと3bとは前記
トランジスタ１と２それぞれのエミッタ電流の通電用バ
ー（導帯）であり、3cは前記両エミッタ電流の合成電流
通電用のバーである。前記両バー3aと3bとにおける前記
両エミッタ電流の合流点までの長さL1とL2とはL1＝L2の
如く等しくされ、また前記両トランジスタ１と２とに対
する共通の制御信号用ベース入力配線も図示の如く対称
化されている。In FIG. 3, 1 and 2 are power transistors, B
, C and E are a base terminal, a collector terminal and an emitter terminal of the two transistors, respectively, 3a and 3b are conducting bars for conducting an emitter current of the transistors 1 and 2, respectively, and 3c is a conducting band. This is a bar for conducting a combined current of the two emitter currents. The two bars 3a the in and the 3b of the length L 1 and L 2 of the confluence of the two emitter currents are equal as L 1 = L 2, also for a common control signal to the two transistors 1 and 2 and The base input wiring is also symmetrical as shown.
第４図は第３図に対応する２個のパワートランジスタ
並列接続時の回路図である。FIG. 4 is a circuit diagram corresponding to FIG. 3 when two power transistors are connected in parallel.
しかしながら上記の如き従来方法においては並列接続
される電力用スイッチング素子の個数増大に従い、特に
該各素子の主回路配線に関しそれぞれの長さと経路の均
等化を図ることは配線所要スペースの増大による装置の
大形化と配線作業の複雑化による装置の価格上昇とを招
かざるを得なかった。これに鑑み本発明は、回路配線不
均衡による配線インダクタンス差に基因するスイッチン
グノイズの前記各素子制御信号入力回路への影響を除去
し前記各素子の電流分担率の平衡を簡易且つ安価に図り
得るスイッチング素子の並列接続方法の提供を目的とす
るものである。However, in the conventional method as described above, according to the increase in the number of power switching elements connected in parallel, in particular, to equalize the lengths and paths of the main circuit wiring of each element, it is necessary to increase the space required for the wiring. This has inevitably led to an increase in the price of the device due to the increase in size and the complexity of the wiring work. In view of this, the present invention can eliminate the influence of the switching noise caused by the wiring inductance difference due to the circuit wiring imbalance on the respective element control signal input circuits, and can easily and inexpensively balance the current sharing rates of the respective elements. It is an object of the present invention to provide a method for connecting switching elements in parallel.
上記目的を達成するために、本発明のスイッチング素
子の並列接続方法は、電力変換装置等に使用される電力
用スイッチング素子の並列接続に関し、並列接続される
前記スイッチング素子それぞれに対して電線貫通形の磁
路形成素子を設け、前記スイッチング素子それぞれにお
いてその制御信号入力配線中の対をなす電線を該各電線
中の電流通電方向が互に逆となるようにして共通に前記
磁路形成素子に貫通させるものである。In order to achieve the above object, a method for connecting switching elements in parallel according to the present invention relates to a parallel connection of power switching elements used in a power converter or the like. And a pair of electric wires in the control signal input wiring of each of the switching elements is commonly connected to the magnetic path forming element so that the current flowing directions in the electric wires are opposite to each other. It is made to penetrate.
電力用スイッチング素子として用いるパワートランジ
スタ或いはサイリスタ等の並列接続制御においては、該
各素子の電流分担率の平衡化のために該各素子自体のタ
ーンオン電圧及びターンオン時間等の諸特性の均一化と
共に前記各素子に対する制御用入力信号の量的時間的特
性の均一化を図る必要がある。In the parallel connection control of a power transistor or a thyristor used as a power switching element, in order to balance the current sharing ratio of each element, the characteristics such as the turn-on voltage and the turn-on time of each element are equalized, and It is necessary to equalize the quantitative and temporal characteristics of the control input signal for each element.
特に前記の制御用入力信号の均一化に関しては、共通
制御信号発信源から前記各素子の制御入力端子迄の制御
信号入力配線の長さと経路の均一化と共に、該制御配線
に比し極めて大なる電流を通電する前記各素子主回路配
線の不揃いによる主回路配線インダクタンス差が主回路
電流の変化に従って発生する逆起電力に基因し前記制御
信号入力配線と主回路配線とにより共通に接続されて形
成された前記各素子出力端子間の閉回路を流れる環流電
流が前記各素子への制御入力信号に対し不均一に与える
波形歪の除去が重要となる。In particular, regarding the uniformity of the control input signal, the length and the path of the control signal input wiring from the common control signal source to the control input terminal of each element are made uniform, and the control input signal is extremely large compared to the control wiring. The main circuit wiring inductance difference due to the irregularity of the main circuit wiring of each of the elements through which a current flows is formed by being connected in common by the control signal input wiring and the main circuit wiring based on the back electromotive force generated according to the change of the main circuit current. It is important to remove the waveform distortion that the circulating current flowing through the closed circuit between the output terminals of the elements non-uniformly gives to the control input signal to the elements.
本発明は、前記環流電流の阻止を目的とし、前記各素
子のそれぞれのなす前記閉回路毎に、その通電方向にお
いて対をなす制御信号入力配線を貫通させた磁路形成素
子（コア）を設けることにより前記各閉回路に等価的な
リアクタンス素子を挿入するものであり、前記各素子の
電流分担率の平衡化に関する前記主回路配線均一化の制
約を除くことを可能とするものである。The present invention provides a magnetic path forming element (core) having a pair of control signal input wirings penetrating in the direction of conduction for each of the closed circuits formed by each of the elements, for the purpose of preventing the circulating current. In this way, an equivalent reactance element is inserted into each of the closed circuits, and it is possible to remove the restriction on the uniforming of the main circuit wiring regarding the balancing of the current sharing ratio of each element.
以下この発明の実施例を図面により説明する。第１図
はこの発明の実施例を示す配線構成図であり、第２図は
第１図に対応する回路図である。Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a wiring diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram corresponding to FIG.
第１図は前記第３図において、パワートランジスタ１
と２それぞれの制御信号入力配線と主回路配線とに関し
前記トランジスタ１を主として行ったものであり、前記
両トランジスタのエミッタ端子接続用バー3aと3bとをバ
ー３にて一本化すると共に前記両トランジスタのエミッ
タ電流の合成分の外部引出しを前記トランジスタ１のエ
ミッタ端子からバー3cにより行うと共に、前記制御信号
入力配線に関し前記両トランジスタのベース端子Ｂとエ
ミッタ端子Ｅとをそれぞれ相互に結びその通電電流方向
が反対である一対の配線を貫通するようになした小形の
磁路形成素子（コア）４を設けたものである。図示の如
く前記トランジスタ２のエミッタ回路配線長は前記トラ
ンジスタ１のそれに比し前記バー３の長さだけ大であ
る。FIG. 1 shows a power transistor 1 shown in FIG.
And 2 mainly use the transistor 1 for the control signal input wiring and the main circuit wiring. The bars 3a and 3b for connecting the emitter terminals of the two transistors are unified by the bar 3 and the two transistors are connected together. The combined output of the emitter current of the transistor is externally drawn from the emitter terminal of the transistor 1 by the bar 3c, and the base terminal B and the emitter terminal E of the two transistors are connected to each other with respect to the control signal input wiring, and A small-sized magnetic path forming element (core) 4 penetrating a pair of wirings having opposite directions is provided. As shown, the length of the emitter circuit wiring of the transistor 2 is larger than that of the transistor 1 by the length of the bar 3.
第２図の回路図において、インダクタンスＬは前記両
トランジスタ１と２とのエミッタ回路配線長の差、従っ
て前記バー３部の有する配線インダクタンスであり前記
トランジスタ２のエミッタ電流の変化に応じて逆起電力
を発生し、前記両トランジスタのエミッタ間に形成され
た閉回路に電流Icを環流させる。該電流Icは前記トラン
ジスタ２のON−OFF動作毎にその通電方向を反転させ
る。また４は電線貫通形の磁路形成素子（コア）であ
り、前記トランジスタ２のベース電流通電用の一対の電
線を貫通させている。なお該一対の電線中の往復電流は
大きさ等しく方向反対のため前記コア４の挿入による配
線インダクタンスの増大はない。また前記環流Icによる
磁束は前記コア４中を通りここにリアクタンス降下を発
生させ前記電流Icの環流を阻止するように動作し、該電
流Icにより発生するスイッチングノイズによる前記制御
入力信号の歪発生は抑制される。すなわち、前記の如き
両トランジスタ１と２との主回路配線の不揃いにもかか
わらず前記コア４の動作により前記両トランジスタ１と
２との電流分担率の不平衡は抑制されることになる。In the circuit diagram of FIG. 2, the inductance L is the difference between the emitter circuit wiring lengths of the two transistors 1 and 2, that is, the wiring inductance of the bar 3, and is counteracted according to the change in the emitter current of the transistor 2. generating a power, to circulate a current I c in closed circuit formed between the emitters of the two transistors. It said current I c reverses the current direction for each ON-OFF operation of the transistor 2. Reference numeral 4 denotes an electric wire penetrating magnetic path forming element (core), which penetrates a pair of electric wires for supplying a base current of the transistor 2. Since the round-trip currents in the pair of wires are equal in magnitude and opposite in direction, the insertion of the core 4 does not increase the wiring inductance. The magnetic flux generated by the ring current I c operates to prevent the reflux of the current I c to generate reactance drop here through the middle of the core 4, of the control input signal due to switching noise generated by said current I c The generation of distortion is suppressed. In other words, the operation of the core 4 suppresses the imbalance in the current sharing ratio between the transistors 1 and 2 irrespective of the irregularities in the main circuit wiring between the transistors 1 and 2 as described above.
本発明によれば、並列接続される電力用スイッチング
素子の制御信号入力配線を貫通させた小形の電線貫通形
磁路形成素子（コア）を前記各素子毎に設けることによ
り該各素子のスイチングノイズによる制御入力信号の波
形歪が抑制され該各素子の電流分担率の平衡化が簡易且
つ安価に図り得ると共に、前記各素子に対する主回路配
線経路に関する制約が除かれ該各素子を用いる装置の小
形化と低廉化とが可能となる。According to the present invention, switching of each element is provided by providing a small electric wire penetrating type magnetic path forming element (core) in which the control signal input wiring of the power switching element connected in parallel is penetrated. The waveform distortion of the control input signal due to noise is suppressed, the current sharing ratio of each element can be balanced easily and inexpensively, and the restriction on the main circuit wiring path for each element is removed, so that the device using each element can be used. It is possible to reduce the size and cost.
第１図はこの発明の実施例を示す配線構成図、第２図は
第１図に対応する回路図、第３図は従来技術の実施例を
示す配線構成図、第４図は第３図に対応する回路図であ
る。 1,2……パワートランジスタ、3,3a,3b,3c……バー（通
電用導帯）、４……コア（電線貫通形磁路形成素子）、
Ｂ……ベース端子、Ｃ……コレクタ端子、Ｅ……エミッ
タ端子。1 is a wiring diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram corresponding to FIG. 1, FIG. 3 is a wiring diagram showing an embodiment of the prior art, and FIG. 4 is FIG. 3 is a circuit diagram corresponding to FIG. 1,2 ... Power transistor, 3,3a, 3b, 3c ... Bar (conductive band), 4 ... Core (wire-through type magnetic path forming element),
B: Base terminal, C: Collector terminal, E: Emitter terminal.
Claims (1)
チング素子の並列接続に関し、並列接続される前記スイ
ッチング素子それぞれに対して電線貫通形の磁路形成素
子を設け、前記スイッチング素子それぞれにおいてその
制御信号入力配線中の対をなす電線を該各電線中の電流
通電方向が互に逆となるようにして共通に前記磁路形成
素子に貫通させることを特徴とするスイッチング素子の
並列接続方法。1. A parallel connection of power switching elements used in a power converter or the like, wherein a wire-passing type magnetic path forming element is provided for each of the switching elements connected in parallel, A method of connecting switching elements in parallel, wherein a pair of electric wires in a control signal input wiring is commonly passed through the magnetic path forming element such that current flowing directions in the respective electric wires are opposite to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021467A JP2586162B2 (en) | 1990-01-31 | 1990-01-31 | Switching element parallel connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021467A JP2586162B2 (en) | 1990-01-31 | 1990-01-31 | Switching element parallel connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03227110A JPH03227110A (en) | 1991-10-08 |
| JP2586162B2 true JP2586162B2 (en) | 1997-02-26 |
Family
ID=12055791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021467A Expired - Lifetime JP2586162B2 (en) | 1990-01-31 | 1990-01-31 | Switching element parallel connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2586162B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2551089Y2 (en) * | 1992-04-10 | 1997-10-22 | 東洋電機製造株式会社 | Parallel connection circuit of switching elements with improved current balance |
-
1990
- 1990-01-31 JP JP2021467A patent/JP2586162B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03227110A (en) | 1991-10-08 |
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