JP2557906B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2557906B2
JP2557906B2 JP62246058A JP24605887A JP2557906B2 JP 2557906 B2 JP2557906 B2 JP 2557906B2 JP 62246058 A JP62246058 A JP 62246058A JP 24605887 A JP24605887 A JP 24605887A JP 2557906 B2 JP2557906 B2 JP 2557906B2
Authority
JP
Japan
Prior art keywords
layer
etching
hno
electrode
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62246058A
Other languages
Japanese (ja)
Other versions
JPS6489436A (en
Inventor
喜一 臼木
恒夫 厚見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62246058A priority Critical patent/JP2557906B2/en
Publication of JPS6489436A publication Critical patent/JPS6489436A/en
Application granted granted Critical
Publication of JP2557906B2 publication Critical patent/JP2557906B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体装置の製造方法に関するもので、特に
半導体装置の電極のエッチング工程において使用される
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and is particularly used in an etching process of electrodes of a semiconductor device.

(従来の技術) 従来、この種の電極としてはAl電極が用いられ、その
エッチング法としては、ウエットエッチング法,ドライ
エッチング法(代表的にはリアクティブ・イオン・エッ
チング略してRIE)が一般に用いられている。
(Prior Art) Conventionally, an Al electrode has been used as this kind of electrode, and as its etching method, a wet etching method or a dry etching method (typically, reactive ion etching for short, RIE) is generally used. Has been.

(発明が解決しようとする問題点) 従来、Al電極のエッチング方法としては、ウエットエ
ッチングまたはRIE等のドライエッチングが一般に用い
られているが、これらは半導体装置の加工寸法,電極膜
厚,レジスト及び下地膜との選択性,生産性,素子の価
格等で選択される。加工寸法が微細パターンでない場合
は、CH3COOH,HNO3,H3PO4系のエッチング液が用いられ
る。
(Problems to be Solved by the Invention) Conventionally, wet etching or dry etching such as RIE has been generally used as a method for etching an Al electrode. It is selected according to the selectivity with the underlying film, the productivity, the price of the device, and so on. If the processing size is not a fine pattern, a CH 3 COOH, HNO 3 , or H 3 PO 4 based etching solution is used.

ところで従来は、半導体装置の電極としてはAl単層で
あったが、AlとMo,V,Cuのうち1つ以上の金属を組み合
わせた電極を用いる必要が生じた。しかしこのような電
極を上記エッチング液を用いてエッチングする場合、エ
ッチング液中のHNO3濃度の具合により、Mo,V,Cuのエッ
チング残り、及びAlとMo,V,Cuのエッチングレート差が
生じてヒサシ形状となり、製品特性、信頼性に悪影響を
与える問題が生じた。
By the way, conventionally, an Al single layer was used as an electrode of a semiconductor device, but it became necessary to use an electrode in which Al and one or more metals of Mo, V, and Cu were combined. However, when such an electrode is etched using the above etching solution, depending on the HNO 3 concentration in the etching solution, the etching residue of Mo, V, Cu, and the etching rate difference between Al and Mo, V, Cu occur. As a result, there was a problem that the product shape and reliability were adversely affected.

そこで本発明の目的とするところは、上記のような電
極が所定寸法でかつ良好な形状を得ることができ、以っ
て素子特性、信頼性を向上させようとするものである。
Therefore, an object of the present invention is to improve the device characteristics and reliability by making it possible for the above electrode to have a predetermined size and a good shape.

[発明の構成] (問題点を解決するための手段と作用) 本発明は、半導体基板上にAlとCu,Mo,Vのうち少なく
とも一つ以上の金属とを組み合わせた電極を有する半導
体装置を製造するに当たり、H3PO4,HNO3,CH3COOHを用い
たエッチング液で上記電極をエッチングする際、上記エ
ッチング液中のHNO3濃度が1wt%(重量%)以上のエッ
チング液を用いることを特徴とする半導体装置の製造方
法である。即ちHNO3濃度を上記のように選定することで
(但し上限は、後述するように10wt%)良好なエッチン
グ形状が得られた。
[Structure of the Invention] (Means and Actions for Solving Problems) The present invention provides a semiconductor device having an electrode formed by combining Al and at least one metal selected from Cu, Mo, and V on a semiconductor substrate. In manufacturing, when etching the electrode with an etching solution using H 3 PO 4 , HNO 3 , and CH 3 COOH, use an etching solution having a HNO 3 concentration of 1 wt% (wt%) or more in the etching solution. And a method for manufacturing a semiconductor device. That is, a good etching shape was obtained by selecting the HNO 3 concentration as described above (however, the upper limit is 10 wt% as described later).

(実施例) 以下図面を参照して本発明の実施例を説明する。第1
図は同実施例で、電極材料をAl,V,Alの三層構造とし、H
NO3濃度が1wt%以上の液を用いたエッチング後の形状を
示す。第2図,第3図では電極材料をAl,V,Alの三層構
造とし、HNO3濃度が1wt%より低い液を用いたエッチン
グ後の形状を示す。これら図において、1は半導体基
板、2は半導体基面保護膜(絶縁膜)、3は電極で、3a
はAl層(第1層)、3bはV層(第2層)、3cはAl層(第
3層)、4は選択的に開口されたレジスト膜である。
Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows the same embodiment, the electrode material has a three-layer structure of Al, V, Al, H
The shape after etching using a liquid having a NO 3 concentration of 1 wt% or more is shown. 2 and 3 show the shape after etching using a liquid having a three-layer structure of Al, V and Al as the electrode material and having a HNO 3 concentration lower than 1 wt%. In these figures, 1 is a semiconductor substrate, 2 is a semiconductor base surface protective film (insulating film), 3 is an electrode, and 3a
Is an Al layer (first layer), 3b is a V layer (second layer), 3c is an Al layer (third layer), and 4 is a resist film which is selectively opened.

前述したように半導体装置の電極加工方法としては、
ウエットエッチング法,ドライエッチング法(代表例RI
E)等が一般に用いられているが、これらは半導体装置
の加工寸法、電極膜厚、レジスト及び下地膜との選択
性、生産性、素子の価格等で選択される。
As described above, as the electrode processing method of the semiconductor device,
Wet etching method, dry etching method (typical example RI
E) and the like are generally used, but these are selected depending on the processing size of the semiconductor device, the electrode film thickness, the selectivity with respect to the resist and the base film, the productivity, the price of the element, and the like.

ところでAlとMo,Cu,Vのうち少なくとも一つ以上の金
属とを組み合わせた電極を、H3PO4,HNO3,CH3COOH系のエ
ッチング液でエッチングする場合、Alとのエッチングレ
ート差が生じてMo,Cu,Vの組み合わせ金属が全面残りし
たり、ひさし形状となって、工程で問題となると共に素
子特性,素子信頼性上大きな問題となる。
By the way, when an electrode combining Al and Mo, Cu, at least one or more metal among V is etched with H 3 PO 4 , HNO 3 , and CH 3 COOH-based etching solution, the etching rate difference from Al is As a result, the combined metal of Mo, Cu, and V remains on the entire surface, or becomes an eaves shape, which becomes a problem in the process and a serious problem in device characteristics and device reliability.

第1図ないし第3図で示したように、電極構造はAl−
V−Al構造で、第1層Al膜3aの厚みは1000Å,その上に
第2層V膜3bを3000Å,その上に第3層Al膜3cを3μm
形成した構造である。
As shown in FIGS. 1 to 3, the electrode structure is Al-
In the V-Al structure, the thickness of the first layer Al film 3a is 1000Å, the second layer V film 3b is 3000Å on it, and the third layer Al film 3c is 3 μm on it.
It is the formed structure.

第3層目のAl膜3c上に、PEP(フォト・エッチング・
プロセス)法で選択的に開口された半導体素子は、CH3C
OOH−H3PO4−HNO3系のエッチング液中に浸される。第3
層Al膜3cがエッチングされ、第2層V膜3bが露出したと
き、第2層V膜と第3層Al膜で電位を生じる。
On the third layer Al film 3c, PEP (photo etching
The semiconductor element selectively opened by the (process) method is CH 3 C
Immersed in an etching solution of OOH-H 3 PO 4 -HNO 3 system. Third
When the layer Al film 3c is etched and the second layer V film 3b is exposed, a potential is generated between the second layer V film and the third layer Al film.

この時のエッチング液中のHNO3濃度が1wt%未満の場
合、2種類のエッチング機構となる。
If the HNO 3 concentration in the etching solution at this time is less than 1 wt%, there are two types of etching mechanisms.

即ちHNO3濃度が0.5〜1wt%未満の場合、第2図に示す
ようにAl層のエッチングが促進され、AlとVのエッチン
グレート差が生じ、V膜3bがひさし形状となる。
That is, when the HNO 3 concentration is less than 0.5 to 1 wt%, the etching of the Al layer is promoted as shown in FIG.

またHNO3濃度が0.5wt%以下の場合、第3図に示すよ
うに第3層Al膜3cのエッチングのみ促進され、V膜3b以
下が全面残りとなる。
Further, when the HNO 3 concentration is 0.5 wt% or less, only the etching of the third layer Al film 3c is promoted as shown in FIG. 3, and the V film 3b or less remains entirely.

そこで本発明によるHNO3濃度が1wt%以上の液を用い
ることで、上記不具合な現象を防止でき、第1図に示す
ように良好なエッチング形状が得られる。
Therefore, by using the liquid having the HNO 3 concentration of 1 wt% or more according to the present invention, it is possible to prevent the above-mentioned inconvenient phenomenon and obtain a good etching shape as shown in FIG.

なおHNO3濃度は、10wt%を越えるとレジスト剥れが生
じるので、1〜10wt%の範囲とする。
The HNO 3 concentration is in the range of 1 to 10 wt% because resist peeling occurs when it exceeds 10 wt%.

[発明の効果] 以上説明した如く本発明によれば、AlとMo,Cu,Vのう
ち少なくとも1つ以上の金属とを組み合わせた電極で、
H3PO4,HNO3,CH3COOH系のエッチング液を用いてエッチン
グする場合、HNO3濃度を1wt%以上としたもので、Alと
のエッチングレートがそろい、良好な電極エッチング形
状が得られるものである。
[Effects of the Invention] As described above, according to the present invention, an electrode in which Al and at least one metal of Mo, Cu, and V are combined,
When etching with H 3 PO 4, HNO 3, CH 3 COOH type etching solution, obtained by the HNO 3 concentration 1 wt% or more, aligned etching rate with Al, resulting good electrode etching shape It is a thing.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を説明するための電極付近の
断面図、第2図,第3図はエッチング液中のHNO3濃度が
本発明の範囲以外の場合を説明するための電極付近の断
面図である。 1……半導体基板、2……表面保護膜、3……電極、3a
……Al(第1層)、3b……V(第2層)、3c……Al(第
3層)、4……レジスト膜。
FIG. 1 is a sectional view of the vicinity of an electrode for explaining one embodiment of the present invention, and FIGS. 2 and 3 are electrodes for explaining the case where the HNO 3 concentration in the etching solution is outside the range of the present invention. FIG. 1 ... Semiconductor substrate, 2 ... Surface protective film, 3 ... Electrode, 3a
... Al (first layer), 3b ... V (second layer), 3c ... Al (third layer), 4 ... resist film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に、Alから構成される第1層
を形成する工程と、 前記第1層上に、Vから構成される第2層を形成する工
程と、 前記第2層上に、Alから構成される第3層を形成する工
程と、 前記第3層上にマスク材を形成する工程と、 前記マスク材に選択的に開口を形成する工程と、 前記開口されたマスク材をマスクにして、H3PO4,HNO3,C
H3COOHから構成されるエッチング液であって、前記HNO3
の濃度が1wt%以上10wt%以下のものを用いて、連続的
に前記第1乃至第3層をエッチングする工程と を具備することを特徴とする半導体装置の製造方法。
1. A step of forming a first layer made of Al on a semiconductor substrate, a step of forming a second layer made of V on the first layer, and a step of forming the second layer on the second layer. A step of forming a third layer made of Al, a step of forming a mask material on the third layer, a step of selectively forming openings in the mask material, and the opened mask material. As a mask, H 3 PO 4 , HNO 3 , C
An etching solution composed of H 3 COOH, wherein the HNO 3
And a step of continuously etching the first to third layers with a concentration of 1 wt% or more and 10 wt% or less.
JP62246058A 1987-09-30 1987-09-30 Method for manufacturing semiconductor device Expired - Fee Related JP2557906B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246058A JP2557906B2 (en) 1987-09-30 1987-09-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246058A JP2557906B2 (en) 1987-09-30 1987-09-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6489436A JPS6489436A (en) 1989-04-03
JP2557906B2 true JP2557906B2 (en) 1996-11-27

Family

ID=17142840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246058A Expired - Fee Related JP2557906B2 (en) 1987-09-30 1987-09-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2557906B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5334484A (en) * 1976-09-10 1978-03-31 Toshiba Corp Forming method for multi layer wiring
JPS54100676A (en) * 1978-01-26 1979-08-08 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6489436A (en) 1989-04-03

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