JP2536050B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2536050B2 JP2536050B2 JP63107027A JP10702788A JP2536050B2 JP 2536050 B2 JP2536050 B2 JP 2536050B2 JP 63107027 A JP63107027 A JP 63107027A JP 10702788 A JP10702788 A JP 10702788A JP 2536050 B2 JP2536050 B2 JP 2536050B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance layer
- electrode
- contact hole
- insulating film
- surface including
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に多層配線
構造を有する半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.
半導体素子の微細化が進み、それに伴なって配線の多
層化が進んでいる。この配線の多層化は従来のアルミニ
ウム配線等の金属配線のみならず多結晶シリコン配線
や、高融点金属配線，高融点金属硅化物配線等の多層化
も同時に進んでいる。またメモリセル等を有する半導体
装置を縮小するため素子の多層構造化も提案されてい
る。The miniaturization of semiconductor elements is advancing, and accordingly, the multilayering of wiring is advancing. In addition to conventional metal wiring such as aluminum wiring, multi-layer wiring such as polycrystalline silicon wiring, refractory metal wiring, refractory metal silicide wiring, etc. is being advanced at the same time. Further, in order to reduce the size of a semiconductor device having a memory cell or the like, a multilayer structure of elements has been proposed.
従来の半導体装置の第１の例は、第３図に示すよう
に、多結晶シリコン層の負荷抵抗を用いたスタティック
型MOSランダムアクセルメモリセルを有する半導体装置
において、前記メモリセルの寸法を小さくするための高
抵抗の負荷抵抗として抵抗層9,14を直列接続した２層構
造にする方法が提案されている。As a first example of a conventional semiconductor device, as shown in FIG. 3, in a semiconductor device having a static MOS random access memory cell using a load resistance of a polycrystalline silicon layer, the size of the memory cell is reduced. As a high resistance load resistance for the above, a method of forming a two-layer structure in which resistance layers 9 and 14 are connected in series has been proposed.
また、従来の半導体装置の第２の例は、第４図に示す
ように、下層のMOSトランジスタの上に積層して多結晶
シリコン層による上層のMOSトランジスタを形成し、メ
モリセルの寸法を縮小する方法も提案されている。In addition, as a second example of the conventional semiconductor device, as shown in FIG. 4, by stacking on the lower MOS transistor, the upper MOS transistor of the polycrystalline silicon layer is formed to reduce the size of the memory cell. The method of doing is also proposed.
このように、配線や素子の多層化が進むと、層間絶縁
膜の層数や厚さが増加し、半導体基板中に設けた素子領
域とのコンタクトホールを層間絶縁膜に設けたときに、
コンタクトホールの口径Ｄと高さＨとの比H/D（以後ア
スペクト比と記す）が大きくなり、コンタクトホールの
配線のカバレージが悪くなり、空洞19を生じて電極18a
が断線することがある。Thus, as the number of layers and thickness of the interlayer insulating film increases as the number of layers of wiring and elements increases, when a contact hole with the element region provided in the semiconductor substrate is provided in the interlayer insulating film,
The ratio H / D (hereinafter referred to as the aspect ratio) between the diameter D and the height H of the contact hole is increased, the coverage of the contact hole wiring is deteriorated, and the cavity 19 is formed to form the electrode 18a.
May be disconnected.
上述したように、従来の半導体装置は、配線や素子の
多層化が進むと、層間絶縁膜が厚くなり、半導体基板に
設けた素子領域のコンタクトホールのアスペクト比が大
きくなり、コンタクトホールのアスペクト比が１以上に
なる場合がある。通常アスペクト比が１以上になるとコ
ンタクトホールでの配線切れや配線のカバレージの悪化
を招き1.5以上ではコンタクトをとることが困難とな
り、製品歩留，信頼性等で問題となる。従来、コンタク
トホールでの段切れを防ぐため、コンタクトホール上端
に傾斜を設けるテーパー処理を施す方法が提案されてい
るが、この方法ではコンタクトホールの上端が広がるた
め素子の微細化には適さない。また、コンタクトホール
に多結晶シリコン層や金属を堆積した後エッチバック法
を用いて、コンタクトホール内にこれらの堆積層を埋め
込む方法も提案されているが工程が複雑で深さの異なる
複数のコンタクトホールを良好に埋め込むことが難しい
等の欠点がある。As described above, in the conventional semiconductor device, as the number of wirings and elements is increased, the interlayer insulating film becomes thicker, the aspect ratio of the contact hole in the element region provided on the semiconductor substrate increases, and the aspect ratio of the contact hole increases. May be 1 or more. Usually, when the aspect ratio is 1 or more, the wiring breaks in the contact hole and the coverage of the wiring is deteriorated, and when the aspect ratio is 1.5 or more, it becomes difficult to make a contact, which causes a problem in product yield and reliability. Conventionally, in order to prevent disconnection in the contact hole, a method of tapering the upper end of the contact hole has been proposed, but this method is not suitable for miniaturization of the element because the upper end of the contact hole widens. A method has also been proposed in which a polycrystalline silicon layer or metal is deposited in the contact hole and then the etch-back method is used to bury these deposited layers in the contact hole. However, the process is complicated and multiple contacts with different depths are used. There are drawbacks such as difficulty in burying holes well.
本発明の目的は、多層配線を有する半導体装置の層間
絶縁膜に設けるコンタクトホールの断線を防止して信頼
性を向上させた半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having improved reliability by preventing disconnection of a contact hole provided in an interlayer insulating film of a semiconductor device having a multilayer wiring.
本発明の半導体装置の製造方法の構成は、半導体基板
の一主面に設けた複数の素子領域を含む表面に第１の絶
縁膜を形成しこれら素子領域上の前記第１の絶縁膜に第
１のコンタクトホールをそれぞれ形成する工程と、前記
第１のコンタクトホールを含む表面に堆積した第１の多
結晶シリコン膜をパターニングして１つの前記第１のコ
ンタクトホールの前記素子領域に接続する第１の電極お
よび他の前記第１のコンタクトホールの前記素子領域に
一端を接続してこの素子領域上の前記第１の絶縁膜上に
延在する第１の抵抗層をそれぞれ同時に形成する工程
と、前記第１の電極および第１の抵抗層を含む表面に第
２の絶縁膜を形成した後前記第１の電極上および前記第
１の抵抗層の他方の端部上の前記第２の絶縁膜に第２の
コンタクトホールをそれぞれ形成する工程と、前記第２
のコンタクトホールを含む表面に堆積した第２の多結晶
シリコン膜をパターニングして前記第１の電極に１つの
前記第２のコンタクトホールを介して接続し且つこの第
１の電極の直上に設けたブロック状の第２の電極および
前記第１の抵抗層の他端に他の前記第２のコンタクトホ
ールを介して一端を接続して前記第１の抵抗層上の前記
第２の絶縁膜上に延在させ他端を前記第１の抵抗層の一
端上に接するようにした第２の抵抗層を同時に形成する
工程と、前記第２の電極および前記第２の抵抗層を含む
表面に設けてパターニングしたホストレジスト膜をマス
クとして不純物をそれぞれイオン注入し前記第２の電極
を通して前記第１の電極に不純物を導入すると同時に前
記第２の抵抗層の他方の端部および前記第の抵抗層の一
端に不純物をそれぞれ導入する工程と、前記ホトレジス
ト膜を除去した後アニールにより前記第１の電極および
前記第１の抵抗層からそれぞれの素子領域に前記不純物
を拡散して前記各素子領域の拡散領域より浅い高濃度の
拡散領域をそれぞれ形成する工程と、前記第２の電極お
よび前記第２の抵抗層を含む表面に第３の絶縁膜を形成
した後この第３の絶縁膜に第３のコンタクトホールをそ
れぞれ形成しこれら第３のコンタクトホールに前記第２
の電極および前記第２の抵抗層とそれぞれ接続する金属
電極をそれぞれ形成する工程とを含むことを特徴とす
る。According to the structure of the method for manufacturing a semiconductor device of the present invention, a first insulating film is formed on a surface including a plurality of element regions provided on one main surface of a semiconductor substrate, and the first insulating film is formed on the element regions with a first insulating film. Forming a first contact hole, patterning the first polycrystalline silicon film deposited on the surface including the first contact hole, and connecting to the element region of one of the first contact holes. A step of connecting one end of the first electrode and the other first contact hole to the element region and simultaneously forming a first resistance layer extending on the first insulating film on the element region; After forming a second insulating film on the surface including the first electrode and the first resistance layer, the second insulation on the first electrode and the other end of the first resistance layer Make a second contact hole in the film. A step of respectively forming the second
The second polycrystalline silicon film deposited on the surface including the contact hole is patterned to be connected to the first electrode through one of the second contact holes and provided directly on the first electrode. One end is connected to the other end of the block-shaped second electrode and the first resistance layer through the other second contact hole, and is formed on the second insulating film on the first resistance layer. A step of simultaneously forming a second resistance layer extending and having the other end in contact with one end of the first resistance layer; and a step of forming a second resistance layer on the surface including the second electrode and the second resistance layer. Impurities are ion-implanted using the patterned host resist film as a mask to introduce the impurities into the first electrode through the second electrode, and at the same time, the other end portion of the second resistance layer and one end of the first resistance layer. To impurities it And a step of introducing the impurities, and after the photoresist film is removed, annealing is performed to diffuse the impurities from the first electrode and the first resistance layer into the respective element regions to form a high concentration shallower than a diffusion region of each of the element regions. And forming a third insulating film on the surface including the second electrode and the second resistance layer, and then forming a third contact hole on the third insulating film. The second contact is formed in these third contact holes.
And a metal electrode connected to the second resistance layer, respectively.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例の製造方法
を説明するための工程順に示した半導体チップの断面図
である。1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、ｐ型半導体基板１
の上に選択酸化法により膜厚0.7〜0.8μｍのフィールド
酸化膜２を設けて素子形成領域を区画し、熱酸化法によ
り前記素子形成領域の表面に酸化シリコン膜３を設け
る。次に、酸化シリコン膜３の一部を選択的にエッチン
グして開口部を設け、前記開口部を含む表面にCVD法に
より多結晶シリコン層を0.4〜0.5μｍの厚さに堆積し、
これを選択的にエッチングしてゲート電極4aおよび前記
開口部の前記素子領域に接続するゲート電極4bを形成す
る。次に、フィールド酸化膜２及びゲート電極4a,4bを
マスクとして不純物をイオン注入した深さ0.3〜0.4μｍ
のｎ型拡散領域５を形成する。次に、CVD法により全面
に膜厚0.1〜0.2μｍの酸化シリコン膜６を堆積し、これ
を選択的にエッチングして第１のコンタクトホール７を
形成する。First, as shown in FIG. 1A, a p-type semiconductor substrate 1
A field oxide film 2 having a thickness of 0.7 to 0.8 .mu.m is provided on the above to partition the element forming region, and a silicon oxide film 3 is provided on the surface of the element forming region by the thermal oxidation method. Next, a portion of the silicon oxide film 3 is selectively etched to form an opening, and a polycrystalline silicon layer is deposited to a thickness of 0.4 to 0.5 μm on the surface including the opening by a CVD method,
This is selectively etched to form a gate electrode 4a and a gate electrode 4b connected to the element region of the opening. Next, using the field oxide film 2 and the gate electrodes 4a and 4b as a mask, impurities are ion-implanted to a depth of 0.3 to 0.4 μm.
The n-type diffusion region 5 is formed. Next, a silicon oxide film 6 having a film thickness of 0.1 to 0.2 μm is deposited on the entire surface by a CVD method, and this is selectively etched to form a first contact hole 7.
次に、第１図（ｂ）に示すように、コンタクトホール
７を含む表面にCVD法により多結晶シリコン層を0.05〜
0.2μｍの厚さに堆積し、これを選択的にエッチングし
てコンタクトホール７のｎ型拡散領域５と接続する第１
の電極８と、コンタクトホール７のｎ型拡散領域５及び
ゲート電極4bに共通に接続する第１の抵抗層９を形成す
る。次に、CVD法により全面に酸化シリコン膜10を堆積
し、これを選択的にエッチングして電極８の上のコンタ
クトホール11と抵抗層９の上のコンタクトホール12をそ
れぞれ形成する。Next, as shown in FIG. 1 (b), a polycrystalline silicon layer of 0.05 to 0.05 is formed on the surface including the contact holes 7 by the CVD method.
The first layer is deposited to a thickness of 0.2 μm and selectively etched to connect to the n-type diffusion region 5 of the contact hole 7.
The first resistance layer 9 commonly connected to the electrode 8, the n-type diffusion region 5 of the contact hole 7 and the gate electrode 4b is formed. Next, a silicon oxide film 10 is deposited on the entire surface by the CVD method, and this is selectively etched to form a contact hole 11 on the electrode 8 and a contact hole 12 on the resistance layer 9.
次に、第１図（ｃ）に示すように、コンタクトホール
11,12を含む表面に多結晶シリコン層を0.05〜0.2μｍの
厚さに堆積し、これを選択的にエッチングしてコンタク
トホール11の電極８に接続する第２の電極13及びコンタ
クトホール12の抵抗層９と接続する第２の抵抗層14を形
成する。次に、全面にホストレジスト膜15を設けてパタ
ーニングし、ホトレジスト膜15をマスクとしてリン又は
ヒ素をイオン注入し、抵抗層９のｎ型領域9a及び抵抗層
14のｎ型領域14aをそれぞれ形成すると共に、電極8,13
にもｎ型不純物を導入する。次に、ホトレジスト膜15を
除去し、900〜1000℃のアニールよりｎ型領域9a及び電
極８からｎ型拡散領域５に不純物を拡散してｎ型拡散領
域５より浅いn+型拡散領域16を形成する。Next, as shown in FIG. 1 (c), contact holes
A polycrystalline silicon layer is deposited to a thickness of 0.05 to 0.2 μm on the surface including 11, 12 and is selectively etched to connect the second electrode 13 and the contact hole 12 to the electrode 8 of the contact hole 11. A second resistance layer 14 connected to the resistance layer 9 is formed. Next, a host resist film 15 is provided on the entire surface and patterned, and phosphorus or arsenic is ion-implanted using the photoresist film 15 as a mask to form the n-type region 9a of the resistance layer 9 and the resistance layer.
14 n-type regions 14a are formed, and electrodes 8 and 13 are formed.
Also, an n-type impurity is introduced. Next, the photoresist film 15 is removed, and impurities are diffused from the n-type region 9a and the electrode 8 to the n-type diffusion region 5 by annealing at 900 to 1000 ° C. to form an n + -type diffusion region 16 shallower than the n-type diffusion region 5. Form.
次に、第１図（ｄ）に示すように、全面に層間絶縁膜
17を設け、ｎ型領域14a及び電極13の上の層間絶縁膜17
に第３のコンタクトホールを設ける。次に前記第３のコ
ンタクトホールを含む表面に金属を堆積し、これを選択
的にエッチングして前記第３のコンタクトホールの電極
13及びｎ型領域14aと接続する金属電極18a,18bをそれぞ
れ形成する。Next, as shown in FIG. 1D, an interlayer insulating film is formed on the entire surface.
17 is provided, and the interlayer insulating film 17 on the n-type region 14a and the electrode 13 is provided.
A third contact hole is provided in the. Next, a metal is deposited on the surface including the third contact hole and selectively etched to form an electrode for the third contact hole.
Metal electrodes 18a and 18b connected to 13 and the n-type region 14a are formed, respectively.
以上説明したように本発明は配線又は素子が多層に形
成された半導体装置において、コンタクト電極の特に半
導体基板上に設けられて従来技術ではアスペクト比が大
きくなるコンタクトの引き出し電極に前記多層に形成さ
れた配線又は素子を構成する層と同じ層を選択的にエッ
チングして設けたブロック状電極を積層して設けること
により、実効的にコンタクトホールのアスペクト比を小
さくすることができ、素子の微細化が進んでもコンタク
トホール上端での配線切れや、配線のカバレージの悪化
を無くすことができるという効果がある。第２図は本発
明を用いて製造したテストチップの配線の良品率を従来
法と比較した例で、コンタクト径Ｄが0.8μｍ、段差Ｈ
が1.2μｍ、アスペクト比1.5の場合のデータを示す。ま
た、不純物を導入した多結晶シリコン層や高融点金属シ
リサイド層を、本発明の第１の電極および第２の電極に
適用すればこの不純物を半導体基板に拡散し、浅い拡散
領域を形成することができる。As described above, according to the present invention, in a semiconductor device in which wirings or elements are formed in multiple layers, contact electrodes are provided on the semiconductor substrate, and in the prior art, a contact extraction electrode having a large aspect ratio is formed in the multiple layers. It is possible to effectively reduce the aspect ratio of the contact hole by stacking the block-shaped electrodes provided by selectively etching the same layer as the wiring or the layer constituting the element, and to miniaturize the element. There is an effect that it is possible to prevent wiring breakage at the upper end of the contact hole and deterioration of wiring coverage even if the progress is made. FIG. 2 shows an example in which the non-defective rate of the wiring of the test chip manufactured by using the present invention is compared with the conventional method. The contact diameter D is 0.8 μm and the step H is
Shows the data when is 1.2 μm and the aspect ratio is 1.5. Further, if a polycrystalline silicon layer or a refractory metal silicide layer into which an impurity is introduced is applied to the first electrode and the second electrode of the present invention, the impurity is diffused into the semiconductor substrate to form a shallow diffusion region. You can
第１図（ａ）〜（ｄ）は本発明の一実施例の製造方法を
説明するための工程順に示した半導体チップの断面図、
第２図は本発明を用いて製造したテストチップの配線の
良品率を示す図、第３図及び第４図は従来の半導体装置
の第１及び第２の例を説明するための半導体チップの断
面図である。 １……ｐ型半導体基板、２……フィールド酸化膜、３…
…酸化シリコン膜、4a,4b……ゲート電極、５……ｎ型
拡散領域、６……酸化シリコン膜、７……コタクトホー
ル、８……電極、９……抵抗層、9a……ｎ型領域、10…
…酸化シリコン膜、11,12……コンタクトホール、13…
…電極、14……抵抗層、14a……ｎ型領域、15……ホト
レジスト膜、16……n+型拡散領域、17……層間絶縁膜、
18a,18b……金属電極、19……空洞。1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention,
FIG. 2 is a diagram showing the non-defective rate of the wiring of the test chip manufactured by using the present invention, and FIGS. 3 and 4 are the semiconductor chips for explaining the first and second examples of the conventional semiconductor device. FIG. 1 ... p-type semiconductor substrate, 2 ... field oxide film, 3 ...
... silicon oxide film, 4a, 4b ... gate electrode, 5 ... n type diffusion region, 6 ... silicon oxide film, 7 ... contact hole, 8 ... electrode, 9 ... resistive layer, 9a ... n Mold area, 10 ...
... Silicon oxide film, 11,12 ... Contact hole, 13 ...
... electrode, 14 ... resistive layer, 14a ... n type region, 15 ... photoresist film, 16 ... n + type diffusion region, 17 ... interlayer insulating film,
18a, 18b …… Metal electrodes, 19 …… Cavity.
Claims (1)
域を含む表面に第１の絶縁膜を形成しこれら素子領域上
の前記第１の絶縁膜に第１のコンタクトホールをそれぞ
れ形成する工程と、前記第１のコンタクトホールを含む
表面に堆積した第１の多結晶シリコン膜をパターニング
して１つの前記第１のコンタクトホールの前記素子領域
に接続する第１の電極および他の前記第１のコンタクト
ホールの前記素子領域に一端を接続してこの素子領域上
の前記第１の絶縁膜上に延在する第１の抵抗層をそれぞ
れ同時に形成する工程と、前記第１の電極および第１の
抵抗層を含む表面に第２の絶縁膜を形成した後前記第１
の電極上および前記第１の抵抗層の他方の端部上の前記
第２の絶縁膜に第２のコンタクトホールをそれぞれ形成
する工程と、前記第２のコンタクトホールを含む表面に
堆積した第２の多結晶シリコン膜をパターニングして前
記第１の電極に１つの前記第２のコンタクトホールを介
して接続し且つこの第１の電極の直上に設けたブロック
状の第２の電極および前記第１の抵抗層の他端に他の前
記第２のコンタクトホールを介して一端を接続して前記
第１の抵抗層上の前記第２の絶縁膜上に延在させ他端を
前記第１の抵抗層の一端上に接するようにした第２の抵
抗層を同時に形成する工程と、前記第２の電極および前
記第２の抵抗層を含む表面に設けてパターニングしたホ
トレジスト膜をマスクとして不純物をそれぞれイオン注
入し前記第２の電極を通して前記第１の電極に不純物を
導入すると同時に前記第２の抵抗層の他方の端部および
前記第１の抵抗層の一端に不純物をそれぞれ導入する工
程と、前記ホトレジスト膜を除去した後アニールにより
前記第１の電極および前記第１の抵抗層からそれぞれの
素子領域に前記不純物を拡散して前記各素子領域の拡散
領域より浅い高濃度の拡散領域をそれぞれ形成する工程
と、前記第２の電極および前記第２の抵抗層を含む表面
に第３の絶縁膜を形成した後この第３の絶縁膜に第３の
コンタクトホールをそれぞれ形成しこれら第３のコンタ
クトホールに前記第２の電極および前記第２の抵抗層と
それぞれ接続する金属電極をそれぞれ形成する工程とを
含むことを特徴とする半導体装置の製造方法。1. A first insulating film is formed on a surface including a plurality of element regions provided on one main surface of a semiconductor substrate, and a first contact hole is formed in the first insulating film on these element regions, respectively. And a step of patterning the first polycrystalline silicon film deposited on the surface including the first contact hole to connect the first electrode and the other one of the first contact holes A step of connecting one end to the element region of the first contact hole and simultaneously forming a first resistance layer extending on the first insulating film on the element region; After forming the second insulating film on the surface including the first resistance layer, the first insulating film is formed.
Forming a second contact hole in the second insulating film on the second electrode and on the other end of the first resistance layer, and a second contact hole deposited on the surface including the second contact hole. Patterning the polycrystalline silicon film, and connecting it to the first electrode through one of the second contact holes, and providing the block-shaped second electrode and the first electrode immediately above the first electrode. One end of the resistance layer is connected to the other end of the resistance layer via the second contact hole, and the other end of the first resistance layer is extended to the second insulating film on the first resistance layer. A step of simultaneously forming a second resistance layer in contact with one end of the layer, and ion implantation of impurities using the photoresist film patterned on the surface including the second electrode and the second resistance layer as a mask. Inject the second electric charge Through the step of introducing impurities into the first electrode at the same time as introducing the impurities into the other end of the second resistance layer and one end of the first resistance layer through annealing after removing the photoresist film. Diffusing the impurities into the respective element regions from the first electrode and the first resistance layer to form high-concentration diffusion regions shallower than the diffusion regions of the respective element regions; and the second electrode. And after forming a third insulating film on the surface including the second resistance layer, third contact holes are formed in the third insulating film, and the second electrode and the third contact hole are formed in the third contact holes. And a step of forming metal electrodes respectively connected to the second resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63107027A JP2536050B2 (en) | 1988-04-27 | 1988-04-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63107027A JP2536050B2 (en) | 1988-04-27 | 1988-04-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01276644A JPH01276644A (en) | 1989-11-07 |
| JP2536050B2 true JP2536050B2 (en) | 1996-09-18 |
Family
ID=14448662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63107027A Expired - Lifetime JP2536050B2 (en) | 1988-04-27 | 1988-04-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536050B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6057952A (en) * | 1983-09-09 | 1985-04-03 | Toshiba Corp | Manufacture of semiconductor device |
| DE3650077T2 (en) * | 1985-03-15 | 1995-02-23 | Hewlett Packard Co | Metallic connection system with a flat surface. |
| JPH0715970B2 (en) * | 1985-09-26 | 1995-02-22 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JPS6340343A (en) * | 1986-08-05 | 1988-02-20 | Fujitsu Ltd | Three-dimensional semiconductor device and manufacture thereof |
| JPS6377138A (en) * | 1986-09-20 | 1988-04-07 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1988
- 1988-04-27 JP JP63107027A patent/JP2536050B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01276644A (en) | 1989-11-07 |
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