JP2509489Y2 - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JP2509489Y2 JP2509489Y2 JP1989104281U JP10428189U JP2509489Y2 JP 2509489 Y2 JP2509489 Y2 JP 2509489Y2 JP 1989104281 U JP1989104281 U JP 1989104281U JP 10428189 U JP10428189 U JP 10428189U JP 2509489 Y2 JP2509489 Y2 JP 2509489Y2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- film resistor
- chip element
- connecting portion
- conductive path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】 [産業上の利用分野] この考案は、混成集積回路基板の改良に関し、特に導
電路の改良によって高品質の高密度実装を可能にした混
成集積回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an improvement of a hybrid integrated circuit board, and more particularly to a hybrid integrated circuit board which enables high-quality and high-density mounting by improving a conductive path.
[従来の技術] 従来、混成集積回路の高密度実装を行うべく厚膜抵抗
の上部にチップ素子を載置することが有った。実公昭47
−5698号公報では高密度実装を目的としていないが基板
の上面に抵抗体及び絶縁物層を介して金属片6を載置し
たものが開示されている。[Prior Art] Conventionally, in order to perform high-density mounting of a hybrid integrated circuit, a chip element may be placed on a thick film resistor. Mitsuko 47
Japanese Laid-Open Patent Publication No. 5698-56 discloses that the metal piece 6 is placed on the upper surface of the substrate through a resistor and an insulating layer, although it is not intended for high-density mounting.
[考案が解決しようとする問題点] しかしながら、厚膜抵抗の上部にチップ素子を載置す
る場合、一箇所の導電路に前記厚膜抵抗及びチップ素子
の各端部を接続することと成る。すなわち、前記厚膜抵
抗の接続部は同時にチップ素子の接続部と成る。[Problems to be Solved by the Invention] However, when the chip element is placed on the thick film resistor, each end of the thick film resistor and the chip element is connected to one conductive path. That is, the connection portion of the thick film resistor simultaneously becomes the connection portion of the chip element.
前記厚膜抵抗は、抵抗ペーストを基板に印刷し約850
[℃]の熱を加えて焼成し形成するが、前記焼成時抵抗
ペースト中の非金属成分が導電路中に拡散する。該非金
属成分が拡散した導電路は、半田漏れ性すなわち半田の
接着性及び強度が低下する。その為、従来該導電路にチ
ップ素子を接続する場合、半田付け不良が多くまた信頼
性が低いという問題が有った。The thick film resistor has a resistance paste of about 850 printed on the substrate.
It is formed by applying heat of [° C.], and the non-metal component in the resistance paste diffuses into the conductive path during the baking. The conductive path in which the non-metal component is diffused deteriorates the solder leak property, that is, the solder adhesive property and strength. Therefore, conventionally, when a chip element is connected to the conductive path, there are many problems in soldering and reliability is low.
[問題点を解決するための手段] この考案は、チップ素子を接続する導電路に対する厚
膜抵抗を形成する抵抗ペーストの非金属成分の拡散を防
止し、チップ素子の半田付け不良を軽減することを目的
としたものである。[Means for Solving Problems] This invention is intended to prevent diffusion of non-metal components of a resistance paste forming a thick film resistance with respect to a conductive path connecting a chip element and reduce defective soldering of the chip element. It is intended for.
そして、前記目的を達成すべく厚膜抵抗の接続部と、
隣接したチップ素子の接続部との間に、厚膜抵抗の接続
部からチップ素子の接続部に向けて厚膜抵抗を形成する
抵抗ペースト中の非金属成分が拡散することを防止する
スリットを導電路のパターン印刷によって設けたことを
特徴とする混成集積回路基板を提供する。And, in order to achieve the above object, a thick film resistor connecting portion,
Conducts a slit between the connection part of the adjacent chip element to prevent diffusion of non-metallic components in the resistance paste that forms the thick film resistance from the connection part of the thick film resistor toward the connection part of the chip element. Provided is a hybrid integrated circuit board provided by pattern printing of a road.
[作用] そして、前記のごとくスリットを設けた導電路の一方
側、すなわち厚膜抵抗の接続部に対して厚膜抵抗を焼成
する時、厚膜抵抗を形成する抵抗ペーストの非金属成分
の拡散は前記スリットから先には進行しない。その為、
前記導電路の他方側、すなわちチップ素子の接続部に於
ける半田の漏れ性及び強度の低下が招来されることはな
い。[Operation] When the thick film resistor is fired on one side of the conductive path provided with the slit as described above, that is, the connection portion of the thick film resistor, diffusion of the non-metal component of the resistance paste forming the thick film resistor. Does not proceed beyond the slit. For that reason,
On the other side of the conductive path, that is, on the connecting portion of the chip element, the solder leakability and strength are not deteriorated.
[実施例] 添付図面第1図、第2図は、この考案の好適な実施例
を示した図面である。[Embodiment] FIGS. 1 and 2 of the accompanying drawings are drawings showing a preferred embodiment of the present invention.
同図に於いて、 1は基板、2は該基板1上に印刷形成した導電路、3は
該導電路2間に橋絡して印刷形成した厚膜抵抗、4は該
厚膜抵抗3の上部に重畳して載置しかつ端部を半田5に
よって前記各導電路2に半田付けしたチップ素子であ
る。In the figure, 1 is a substrate, 2 is a conductive path printed on the substrate 1, 3 is a thick film resistor printed by bridging between the conductive paths 2, and 4 is a thick film resistor 3. This is a chip element that is placed on top of each other and has its ends soldered to the conductive paths 2 with solder 5.
そして、前記各導電路2は厚膜抵抗3の接続部21とチ
ップ素子4の接続部22を分離する各スリット23を設けて
いる。Each of the conductive paths 2 is provided with each slit 23 for separating the connecting portion 21 of the thick film resistor 3 and the connecting portion 22 of the chip element 4.
詳述すると、前記基板1はセラミック等によって構成
されれたものである。More specifically, the substrate 1 is made of ceramic or the like.
前記各導電路2は前記基板1に導体ペーストを所定の
パターン形状で印刷し、焼成することによって形成す
る。The conductive paths 2 are formed by printing a conductive paste on the substrate 1 in a predetermined pattern and firing it.
また、厚膜抵抗3は前記基板1及び各導電路2上に抵抗
ペーストを所定のパターン形状で印刷し、焼成すること
によって形成する。The thick film resistor 3 is formed by printing a resistor paste on the substrate 1 and each conductive path 2 in a predetermined pattern shape and baking the paste.
該焼成工程は例えば赤外線焼成炉で約850[℃]の熱
を約15[分]加えて行なう。The firing step is performed by applying heat of about 850 [° C.] for about 15 [minutes] in an infrared firing furnace, for example.
前記厚膜抵抗3の焼成が完了した後、前記チップ素子
4の接続部22に半田ペーストを印刷してチップ素子を載
置し、リフロー炉により加熱して半田付けを行なう。After the firing of the thick film resistor 3 is completed, the solder paste is printed on the connection portion 22 of the chip element 4 to mount the chip element, and the chip element 4 is heated by a reflow furnace to be soldered.
ここに於いて、前記チップ素子の載置に際しチップ素
子4が所定の位置から若干はずれることが有るが、前記
半田付けを行うときの溶融した半田の表面張力によって
自動的に位置が修正されることと成る。Here, when the chip element is placed, the chip element 4 may be slightly displaced from a predetermined position, but the position is automatically corrected by the surface tension of the molten solder when the soldering is performed. Becomes
[考案の効果] この考案に係る厚膜抵抗の上部に重畳して載置し端部
を導電路のチップ素子の接続部に半田付けしたチップ素
子を備えた混成集積回路基板は、厚膜抵抗の接続部と、
隣接したチップ素子の接続部との間に、厚膜抵抗の接続
部からチップ素子の接続部に向けて厚膜抵抗を形成する
抵抗ペースト中の非金属成分が拡散することを防止する
スリットを導電路のパターン印刷によって設けたことを
特徴とする。[Effects of the Invention] A hybrid integrated circuit board having a chip element, which is placed on top of a thick film resistor according to the present invention and is soldered at its end to a connecting portion of a chip element of a conductive path, is Connection part of
Conducts a slit between the connection part of the adjacent chip element to prevent diffusion of non-metallic components in the resistance paste that forms the thick film resistance from the connection part of the thick film resistor toward the connection part of the chip element. It is characterized by being provided by pattern printing of the road.
これにより、厚膜抵抗を形成する抵抗ペースト中の非
金属成分が厚膜抵抗を焼成する際に厚膜抵抗の接続部か
らチップ素子の接続部に向けて拡散せず、そのためチッ
プ素子の接続部において半田漏れ性を維持することがで
き、そのためチップ素子の接続部における半田付け不良
を軽減することができ、しかもスリットを形成するため
に基板に孔を開ける等の特別な加工を施す必要がなく、
単に導電路のパターン印刷によって形成することができ
る効果が有る。As a result, the non-metal component in the resistance paste forming the thick film resistor does not diffuse from the connection part of the thick film resistor toward the connection part of the chip element when firing the thick film resistance, and therefore the connection part of the chip element The solder leakability can be maintained, and therefore, the soldering failure at the connecting portion of the chip element can be reduced, and there is no need to perform special processing such as forming a hole in the substrate to form the slit. ,
There is an effect that it can be formed simply by pattern printing of the conductive path.
第1図は、この考案の好適な実施例を示す平面図、第2
図は第1図の矢視A−A線方向断面図である。 1……基板、2……導電路、21……厚膜抵抗の接続部、
22……チップ素子の接続部、23……スリット、3……厚
膜抵抗、4……チップ素子、5……半田。FIG. 1 is a plan view showing a preferred embodiment of the present invention, and FIG.
The figure is a sectional view taken along the line AA of FIG. 1 ... Substrate, 2 ... Conductive path, 21 ... Connection part of thick film resistor,
22 ... Chip element connection, 23 ... Slit, 3 ... Thick film resistor, 4 ... Chip element, 5 ... Solder.
Claims (1)
(21)と該厚膜抵抗の接続部(21)に隣接して設けたチ
ップ素子の接続部(22)とを有した導電路(2)と、 該導電路(2)の各厚膜抵抗の接続部(21)間に橋絡し
て形成した厚膜抵抗(3)と、 該厚膜抵抗(3)の上部に重畳して載置しかつ端部を前
記導電路(2)のチップ素子の接続部(22)に半田付け
したチップ素子(4)とを備えた混成集積回路基板に於
いて、 前記厚膜抵抗の接続部(21)と、隣接したチップ素子の
接続部(22)との間に、厚膜抵抗の接続部(21)からチ
ップ素子の接続部(22)に向けて厚膜抵抗(3)を形成
する抵抗ペースト中の非金属成分が拡散することを防止
するスリット(23)を前記導電路(2)のパターン印刷
によって設けたことを特徴とする混成集積回路基板。1. A substrate (1), and a chip element formed on the substrate (1) and provided adjacent to the thick film resistor connecting portion (21) and the thick film resistor connecting portion (21). A conductive path (2) having a connecting part (22); and a thick film resistor (3) formed by bridging between the connecting parts (21) of the thick film resistors of the conductive path (2), A hybrid integrated circuit comprising a chip element (4) which is placed on top of a thick film resistor (3) and is soldered at its end to a connecting portion (22) of the chip element of the conductive path (2). In the substrate, between the thick film resistor connecting portion (21) and the adjacent chip element connecting portion (22), the thick film resistor connecting portion (21) to the chip element connecting portion (22) are provided. A slit (23) for preventing diffusion of a non-metal component in a resistance paste forming a thick film resistor (3) toward the surface is provided by pattern printing of the conductive path (2). Hybrid integrated circuit board, wherein the door.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989104281U JP2509489Y2 (en) | 1989-09-05 | 1989-09-05 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989104281U JP2509489Y2 (en) | 1989-09-05 | 1989-09-05 | Hybrid integrated circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0343764U JPH0343764U (en) | 1991-04-24 |
JP2509489Y2 true JP2509489Y2 (en) | 1996-09-04 |
Family
ID=31653078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989104281U Expired - Lifetime JP2509489Y2 (en) | 1989-09-05 | 1989-09-05 | Hybrid integrated circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2509489Y2 (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5722401Y2 (en) * | 1979-04-20 | 1982-05-15 | ||
JPS58131650U (en) * | 1982-02-27 | 1983-09-05 | 日本メクトロン株式会社 | flexible circuit board |
JPS6240462U (en) * | 1985-08-29 | 1987-03-11 |
-
1989
- 1989-09-05 JP JP1989104281U patent/JP2509489Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0343764U (en) | 1991-04-24 |
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