JP2023534276A - Tsvサポート構造を有するz高さの低いledアレイパッケージ - Google Patents
Tsvサポート構造を有するz高さの低いledアレイパッケージ Download PDFInfo
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- JP2023534276A JP2023534276A JP2023502868A JP2023502868A JP2023534276A JP 2023534276 A JP2023534276 A JP 2023534276A JP 2023502868 A JP2023502868 A JP 2023502868A JP 2023502868 A JP2023502868 A JP 2023502868A JP 2023534276 A JP2023534276 A JP 2023534276A
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
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- Engineering & Computer Science (AREA)
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
Claims (20)
- 発光体ピクセルアレイ用のパッケージング構造であって、
隣接ピクセルがピクセル光閉じ込め構造によって横方向に互いに分離された複数のピクセルと、
上部再配線層を有し、前記複数のピクセルに取り付けられる無機基板と、
導電体を含み、前記上部再配線層との電気的結合を支持するために前記無機基板を貫通するように画定された少なくとも1つのスルーシリコンビアであって、前記上部再配線層は、該少なくとも1つのスルーシリコンビアと、前記複数のピクセルとの間に配置されている、少なくとも1つのスルーシリコンビアと、
を含む、パッケージング構造。 - 前記上部再配線層は銅ポストを用いて各ピクセルに取り付けられている、請求項1に記載のパッケージング構造。
- 前記上部再配線層は前記銅ポストと直接接触し、各ピクセルは、それを前記銅ポストに取り付けるはんだ材料と直接接触している、請求項1に記載のパッケージング構造。
- 前記無機基板は、導電体を含む前記少なくとも1つのスルーシリコンビアに直接接触する底部再配線層をさらに含む、請求項1に記載の発光体ピクセルアレイ用パッケージング構造。
- 前記少なくとも1つのスルーシリコンビアは、前記上部再配線層と、前記底部再配線層との間にありながら、前記上部再配線層に直接接触している、請求項1に記載のパッケージング構造。
- 前記光閉じ込め構造は、反射側面コーティングで少なくとも部分的に取り囲まれた蛍光体材料をさらに含む、請求項1に記載のパッケージング構造。
- 前記光閉じ込め構造は、蛍光体材料と整列した拡散層をさらに含む、請求項1に記載のパッケージング構造。
- 前記パッケージング構造の全Z高さは300ミクロン未満である、請求項1に記載のパッケージング構造。
- 前記複数のピクセルは少なくとも9つのピクセルを含む、請求項1に記載のパッケージング構造。
- 前記複数のピクセルはセグメント化されたGaN層から形成されている、請求項1に記載のパッケージング構造。
- 前記複数のピクセルは、充填トレンチによって分離されたピクセルを有するセグメント化されたGaN層から形成されている、請求項1に記載のパッケージング構造。
- 前記無機基板の底部再配線層に取り付けられたCMOSダイをさらに含む、請求項1に記載のパッケージング構造。
- セグメント化されたGaN層と、前記無機基板との間にアンダーフィルをさらに含む、請求項1に記載のパッケージング構造。
- 前記無機基板上に形成された回路をさらに含む、請求項1に記載のパッケージング構造。
- 前記無機基板に取り付けられた少なくとも1つのセンサをさらに含む、請求項1に記載のパッケージング構造。
- 前記無機基板に取り付けられた少なくとも1つのセンサ温度センサをさらに含む、請求項1に記載のパッケージング構造。
- 隣接ピクセルは、前記ピクセル光閉じ込め構造によって30ミクロン未満で分離されている、請求項1に記載のパッケージング構造。
- 前記ピクセル光閉じ込め構造は、シリコーン又はエポキシによって前記上部再配線層から離隔されている、請求項1に記載のパッケージング構造。
- 隣接ピクセルがピクセル光閉じ込め構造によって横方向に互いに分離された複数のピクセルであって、該ピクセルのそれぞれは独立して制御可能である、複数のピクセルと、
上部再配線層を有し、前記複数のピクセルに取り付けられる無機基板と、
導電体を含み、前記上部再配線層との電気的結合を支持するために前記無機基板を貫通するように画定された少なくとも1つのスルーシリコンビアであって、前記上部再配線層は、該少なくとも1つのスルーシリコンビアと、前記複数のピクセルとの間に配置されている、少なくとも1つのスルーシリコンビアと、
前記複数のピクセルから離隔され、前記複数のピクセルによって放射される光を方向付けるレンズと、
を含むアダプティブ照明システム。 - カメラと、
フラッシュ照明システムであって、
隣接ピクセルがピクセル光閉じ込め構造によって横方向に互いに分離された複数のピクセルと、
上部再配線層を有し、前記複数のピクセルに取り付けられる無機基板と、
導電体を含み、前記上部再配線層との電気的結合を支持するために前記無機基板を貫通するように画定された少なくとも1つのスルーシリコンビアであって、前記上部再配線層は、該少なくとも1つのスルーシリコンビアと、前記複数のピクセルとの間に配置されている、少なくとも1つのスルーシリコンビアと、
前記複数のピクセルから離隔され、前記複数のピクセルによって放射される光を、前記カメラの視野内に向かわせるレンズと、
を含むフラッシュ照明システムと、
を含むモバイル装置。
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US202063052151P | 2020-07-15 | 2020-07-15 | |
US63/052,151 | 2020-07-15 | ||
EP20195344.5 | 2020-09-09 | ||
EP20195344.5A EP3968373A1 (en) | 2020-09-09 | 2020-09-09 | Low z-height led array package having tsv support structure |
PCT/US2021/041867 WO2022016004A1 (en) | 2020-07-15 | 2021-07-15 | Low z-height led array package having tsv support structure |
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JP2023502868A Pending JP2023534276A (ja) | 2020-07-15 | 2021-07-15 | Tsvサポート構造を有するz高さの低いledアレイパッケージ |
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US (2) | US20230154911A1 (ja) |
EP (1) | EP4182970A1 (ja) |
JP (1) | JP2023534276A (ja) |
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DE102007059133B4 (de) * | 2007-12-07 | 2023-04-06 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Substrat für ein LED-Submount, LED-Submount und LED-Lichtquelle |
US7928655B2 (en) * | 2008-11-10 | 2011-04-19 | Visera Technologies Company Limited | Light-emitting diode device and method for fabricating the same |
US8535961B1 (en) * | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US8653542B2 (en) * | 2011-01-13 | 2014-02-18 | Tsmc Solid State Lighting Ltd. | Micro-interconnects for light-emitting diodes |
JP5450680B2 (ja) * | 2012-02-01 | 2014-03-26 | スタンレー電気株式会社 | 半導体発光装置 |
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- 2021-07-15 CN CN202180063030.5A patent/CN116114062A/zh active Pending
- 2021-07-15 KR KR1020237005357A patent/KR20230039705A/ko active Search and Examination
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CN116114062A (zh) | 2023-05-12 |
WO2022016004A1 (en) | 2022-01-20 |
KR20230039705A (ko) | 2023-03-21 |
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