JP2023091083A - Substrate for mounting electronic element, electronic device, and electronic module - Google Patents

Substrate for mounting electronic element, electronic device, and electronic module Download PDF

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JP2023091083A
JP2023091083A JP2023080184A JP2023080184A JP2023091083A JP 2023091083 A JP2023091083 A JP 2023091083A JP 2023080184 A JP2023080184 A JP 2023080184A JP 2023080184 A JP2023080184 A JP 2023080184A JP 2023091083 A JP2023091083 A JP 2023091083A
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insulating layer
conductor
layer
electronic device
substrate
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JP2023091083A5 (en
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明彦 舟橋
Akihiko Funahashi
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Kyocera Corp
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Kyocera Corp
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Abstract

To provide a substrate for mounting an electronic element capable of suppressing cracks and breakage from occurring on the substrate from a gap part of an internal conductor by a stress from the exterior, and of improving the rigidity of the substrate for mounting an electronic element.SOLUTION: A substrate 1 for mounting an electronic element has: a first insulating layer 2a; a second insulating layer 2b located on a lower surface of the first insulating layer 2a; and a third insulating layer 2c located on a lower surface of the second insulating layer 2b. The substrate 1 for mounting an electronic element further comprises: a first conductor layer 5a located between the first insulating layer 2a and the second insulating layer 2b; and a second conductor layer 5b located between the second insulating layer 2b and the third insulating layer 2c. The first conductor layer 5a has a first gap 5ag. The second conductor layer 5b has a second gap 5bg. In a plan view, the first gap 5ag is located so as to be overlapped with the second conductor layer 5b, and the second gap 5bg is located so as to be overlapped with the first conductor layer 5a.SELECTED DRAWING: Figure 1

Description

本発明は、電子素子、例えばＣＣＤ（Charge Coupled Device）型またはＣＭＯＳ（Complementary Metal Oxide Semiconductor）型等の撮像素子、ＬＥＤ（Light Emitting Diode）等の発光素子または集積回路等が実装される電子素子実装用基板、電子装置および電子モジュールに関するものである。 The present invention provides an electronic device mounted with an electronic device such as an imaging device such as a CCD (Charge Coupled Device) type or a CMOS (Complementary Metal Oxide Semiconductor) type, a light emitting device such as an LED (Light Emitting Diode), or an integrated circuit. It relates to electronic substrates, electronic devices and electronic modules.

従来より、絶縁層からなる配線基板を備えた電子素子実装用基板が知られている。また、このような電子素子実装用基板に電子素子が実装された電子装置が知られている（特許文献１参照）。 2. Description of the Related Art Conventionally, there has been known an electronic element mounting board provided with a wiring board made of an insulating layer. Further, an electronic device in which an electronic element is mounted on such an electronic element mounting substrate is known (see Patent Document 1).

特開２０１１―１６５９９２号公報JP 2011-165992 A

特許文献１の電子素子実装用基板は、複数の絶縁層の間に内部導体が設けられている。内部導体は同一層に複数設けられており、複数電極を取る等の電極の都合上、複数の内部導体間は隙間が設けられている。このとき、一般的に、電子素子実装用基板は電気特性の向上が要求されている。そのため、内部導体の厚みは電気抵抗を低減させる為により厚くする傾向にあった。内部導体の厚みが厚くなると、各層の隙間も大きくなる傾向にあり、各層の隙間が重なると、外部からの応力等により、基板にクラックや割れ等が生じるおそれがあった。 In the electronic device mounting substrate of Patent Document 1, internal conductors are provided between a plurality of insulating layers. A plurality of internal conductors are provided in the same layer, and gaps are provided between the plurality of internal conductors for the convenience of the electrodes, such as taking a plurality of electrodes. At this time, in general, electronic device mounting substrates are required to have improved electrical characteristics. Therefore, the thickness of the internal conductor tends to be increased in order to reduce the electrical resistance. As the thickness of the internal conductor increases, the gaps between the layers tend to increase, and if the gaps between the layers overlap, there is a risk that cracks or splits will occur in the substrate due to external stress or the like.

本発明の１つの態様に係る電子素子実装用基板は、第１絶縁層と、第２絶縁層と、第３絶縁層と、第１導体層と、第２導体層とを備えている。第１絶縁層は、上方または下方に電子素子が位置する。第２絶縁層は、第１絶縁層の下面に位置する。第３絶縁層は、第２絶縁層の下面に位置する。第１導体層は、第１絶縁層と、第２絶縁層との間に位置した、第１の間を有する。第２導体層は、第２絶縁層と、第３絶縁層との間に位置した、第２の間を有する。平面視において、第１の間は第２導体層と重なって位置しており、第２の間は、第１導体層と重なって位置している。平面視において、第１の間と第２の間とは離れている。第１導体層の第１の間は、第１絶縁層または第２絶縁層の少なくとも一部が位置しており、第２導体層の第２の間は、第２絶縁層または第３絶縁層の少なくとも一部が位置しており、積層方向の断面視において、第１導体層の端部および第２導体層の端部は、それぞれ他の箇所よりも積層方向における厚みが小さいことを特徴とする。 An electronic device mounting substrate according to one aspect of the present invention includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductor layer, and a second conductor layer. Electronic elements are positioned above or below the first insulating layer. The second insulating layer is located on the lower surface of the first insulating layer. The third insulating layer is located on the lower surface of the second insulating layer. The first conductor layer has a first gap located between the first insulating layer and the second insulating layer. The second conductor layer has a second gap located between the second insulating layer and the third insulating layer. In plan view, the first space is positioned so as to overlap with the second conductor layer, and the second space is positioned so as to overlap with the first conductor layer. Planar view WHEREIN: Between 1st and 2nd is separated. At least a portion of the first insulating layer or the second insulating layer is located between the first of the first conductor layers, and the second insulating layer or the third insulating layer is located between the second of the second conductor layers. is located, and in a cross-sectional view in the stacking direction, the end of the first conductor layer and the end of the second conductor layer have a smaller thickness in the stacking direction than other locations. do.

本発明の１つの態様に係る電子装置は、電子素子実装用基板と、前記電子素子実装用基板に実装された電子素子とを備えていることを特徴としている。 An electronic device according to one aspect of the present invention is characterized by comprising an electronic element mounting board and an electronic element mounted on the electronic element mounting board.

本発明の１つの態様に係る電子モジュールは、電子装置の上面または電子装置を囲んで位置した筐体と、を備えている。 An electronic module according to one aspect of the present invention includes a top surface of an electronic device or a housing surrounding the electronic device.

本発明の１つの態様に係る電子素子実装用基板は、上記のような構成により、電子素子実装用基板のクラックや割れが発生する事が低減することができる。さらに、上述した電子素子実装用基板を備えた電子装置を用いることによって、剛性を向上させることが可能な電子装置および電子モジュールを提供することができる。 The substrate for mounting an electronic device according to one aspect of the present invention can reduce the occurrence of cracks and splits in the substrate for mounting an electronic device due to the configuration as described above. Furthermore, by using the electronic device including the electronic element mounting substrate described above, it is possible to provide an electronic device and an electronic module capable of improving rigidity.

図１（ａ）は本発明の第１の実施形態に係る電子素子実装用基板および電子装置の外観を示す上面図であり、図１（ｂ）は図１（ａ）のＸ１－Ｘ１線に対応する縦断面図である。FIG. 1(a) is a top view showing the appearance of an electronic device mounting substrate and an electronic device according to the first embodiment of the present invention, and FIG. 1(b) is taken along line X1-X1 of FIG. 1(a). Fig. 4 is a corresponding longitudinal sectional view; 図２（ａ）は本発明の第１の実施形態に係る電子モジュールの外観を示す上面図であり、図２（ｂ）は図２（ａ）のＸ２－Ｘ２線に対応する縦断面図である。FIG. 2(a) is a top view showing the appearance of the electronic module according to the first embodiment of the present invention, and FIG. 2(b) is a vertical sectional view corresponding to line X2-X2 in FIG. 2(a). be. 図３（ａ）は本発明の第１の実施形態に係る電子素子実装用基板の要部Ａの拡大した概要図であり、図３（ｂ）は本発明の第１の実施形態に係る電子素子実装用基板の要部Ａの拡大したその他の実施例の概要図である。FIG. 3(a) is an enlarged schematic view of the main part A of the electronic device mounting substrate according to the first embodiment of the present invention, and FIG. 3(b) is an electronic device according to the first embodiment of the present invention. FIG. 11 is a schematic diagram of another embodiment in which the main portion A of the element mounting board is enlarged; 図４（ａ）図４（ｂ）は本発明の第１の実施形態に係る電子素子実装用基板の一部を示す概要図である。4(a) and 4(b) are schematic diagrams showing a part of the electronic device mounting board according to the first embodiment of the present invention. 図５（ａ）図５（ｂ）は本発明の第１の実施形態に係る電子素子実装用基板の一部を示す概要図である。5(a) and 5(b) are schematic diagrams showing a part of the electronic device mounting board according to the first embodiment of the present invention. 図６（ａ）図６（ｂ）は本発明の第１の実施形態電子素子実装用基板に係る電子素子実装用基板の一部を示す概要図である。6(a) and 6(b) are schematic diagrams showing a part of the electronic device mounting substrate according to the first embodiment of the electronic device mounting substrate of the present invention. 図７（ａ）は本発明の第２の実施形態に係る電子素子実装用基板および電子装置の外観を示す上面図であり、図７（ｂ）は図７（ａ）のＸ７－Ｘ７線に対応する縦断面図である。FIG. 7(a) is a top view showing the appearance of an electronic device mounting board and an electronic device according to a second embodiment of the present invention, and FIG. 7(b) is taken along line X7-X7 of FIG. 7(a). Fig. 4 is a corresponding longitudinal sectional view; 図８（ａ）は本発明の第２の実施形態に係る電子素子実装用基板の要部Ａの拡大した概要図であり、図８（ｂ）は本発明の第２の実施形態に係る電子素子実装用基板の要部Ａの拡大したその他の実施例の概要図である。FIG. 8(a) is an enlarged schematic diagram of a main portion A of an electronic element mounting substrate according to a second embodiment of the present invention, and FIG. 8(b) is an electronic device according to a second embodiment of the present invention. FIG. 11 is a schematic diagram of another embodiment in which the main portion A of the element mounting board is enlarged; 図９（ａ）は本発明の第３の実施形態に係る電子素子実装用基板および電子装置の外観を示す上面図であり、図９（ｂ）は図９（ａ）のＸ９－Ｘ９線に対応する縦断面図である。FIG. 9(a) is a top view showing the appearance of an electronic device mounting board and an electronic device according to a third embodiment of the present invention, and FIG. 9(b) is taken along line X9-X9 of FIG. 9(a). Fig. 4 is a corresponding longitudinal sectional view; 図１０（ａ）は本発明の第３の他の実施形態に係る電子素子実装用基板および電子装置の外観を示す上面図であり、図１０（ｂ）は図１０（ａ）のＸ１０－Ｘ１０線に対応する縦断面図である。FIG. 10(a) is a top view showing the appearance of an electronic element mounting substrate and an electronic device according to a third alternative embodiment of the present invention, and FIG. 10(b) is a line X10-X10 of FIG. 10(a). It is a longitudinal cross-sectional view corresponding to the line.

＜電子素子実装用基板および電子装置の構成＞
以下、本発明のいくつかの例示的な実施形態について図面を参照して説明する。なお、以下の説明では、電子素子実装用基板に電子素子が実装された構成を電子装置とする。また、電子素子実装用基板の上面側に位置するようにまたは電子装置を囲んで設けられた筐体または部材を有する構成を電子モジュールとする。電子素子実装用基板、電子装置および電子モジュールは、いずれの方向が上方若しくは下方とされてもよいが、便宜的に、直交座標系ｘｙｚを定義するとともに、ｚ方向の正側を上方とする。 <Structure of Electronic Device Mounting Board and Electronic Device>
Several exemplary embodiments of the invention will now be described with reference to the drawings. In the following description, an electronic device is defined as a structure in which an electronic element is mounted on an electronic element mounting substrate. Further, an electronic module is defined as a structure having a housing or member provided so as to be located on the upper surface side of the electronic device mounting substrate or to surround the electronic device. The electronic element mounting board, the electronic device, and the electronic module may be oriented upward or downward, but for the sake of convenience, an orthogonal coordinate system xyz is defined, and the positive side in the z direction is oriented upward.

（第１の実施形態）
図１～図２を参照して本発明の第１の実施形態における電子モジュール３１、電子装置２１、および電子素子実装用基板１について説明する。図３を参照して要部Ａについて説明する。図４～図６を参照して、第１絶縁層２ａと第２絶縁層２ｂとの間に位置した第１の間５ａｇを有する第１導体層５ａと、第２絶縁層２ｂと第３絶縁層２ｃとの間に位置した第２の間５ｂｇを有する第２導体層５ｂについて説明する。また図４～図６では第１導体５ａ第２導体５ｂをドットおよび実線で示している。 (First embodiment)
An electronic module 31, an electronic device 21, and an electronic element mounting substrate 1 according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. The main part A will be described with reference to FIG. 4 to 6, a first conductor layer 5a having a first gap 5ag located between a first insulating layer 2a and a second insulating layer 2b, a second insulating layer 2b and a third insulating layer A second conductor layer 5b having a second gap 5bg located between it and the layer 2c will be described. 4 to 6, the first conductor 5a and the second conductor 5b are indicated by dots and solid lines.

電子素子実装用基板１は、第１絶縁層２ａと、第１絶縁層２ａの下面に位置する第２絶縁層２ｂと、第２絶縁層２ｂの下面に位置する第３絶縁層２ｃを有している。電子素子実装用基板１は第１絶縁層２ａと、第２絶縁層２ｂとの間に位置する第１導体層５ａと、第２絶縁層２ｂと第３絶縁層２ｃとの間に位置する第２導体層５ｂとを備えている。第１導体層５ａは、第１の間５ａｇを有している。第２導体層５ｂは、第２の間５ｂｇを有している。平面視において、第１の間５ａｇは第２導体層５ｂと重なって位置しており、第２の間５ｂｇは、第１導体層５ａと重なって位置している。 The electronic device mounting substrate 1 has a first insulating layer 2a, a second insulating layer 2b positioned on the lower surface of the first insulating layer 2a, and a third insulating layer 2c positioned on the lower surface of the second insulating layer 2b. ing. The electronic device mounting substrate 1 includes a first conductor layer 5a positioned between the first insulating layer 2a and the second insulating layer 2b, and a second conductor layer 5a positioned between the second insulating layer 2b and the third insulating layer 2c. and two conductor layers 5b. The first conductor layer 5a has a first gap 5ag. The second conductor layer 5b has a second gap 5bg. In plan view, the first gap 5ag overlaps the second conductor layer 5b, and the second gap 5bg overlaps the first conductor layer 5a.

電子素子実装用基板１は、第１絶縁層２ａと、第１絶縁層２ａの下面に位置する第２絶縁層２ｂと、第２絶縁層２ｂの下面に位置する第３絶縁層２ｃを有している。ここで、図１に示す例の様に、電子素子実装用基板１は第１絶縁層２ａ、第２絶縁層２ｂと第３絶縁層２ｃの他にその他の絶縁層２ｅを有していてもよい。 The electronic device mounting substrate 1 has a first insulating layer 2a, a second insulating layer 2b positioned on the lower surface of the first insulating layer 2a, and a third insulating layer 2c positioned on the lower surface of the second insulating layer 2b. ing. Here, as in the example shown in FIG. 1, the electronic device mounting board 1 may have another insulating layer 2e in addition to the first insulating layer 2a, the second insulating layer 2b, and the third insulating layer 2c. good.

第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｅを構成する絶縁層の材料は例えば、電気絶縁性セラミックスまたは樹脂などがある。なお以下、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｅからなる絶縁基体を基体２と称する。 The materials of the insulating layers that constitute the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c, and the other insulating layer 2e are, for example, electrically insulating ceramics or resins. Hereinafter, the insulating substrate composed of the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c, and the other insulating layer 2e is referred to as the substrate 2.

第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｅを形成する絶縁層の材料として使用される電気絶縁性セラミックスとしては例えば、酸化アルミニウム質焼結体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミニウム質焼結体、窒化珪素質焼結体またはガラスセラミック焼結体等がある。 Examples of electrically insulating ceramics used as materials for the insulating layers forming the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c, and the other insulating layer 2e include sintered aluminum oxide and mullite. sintered body, silicon carbide sintered body, aluminum nitride sintered body, silicon nitride sintered body, glass ceramic sintered body, and the like.

第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｅを形成する絶縁層の材料として使用される樹脂としては例えば、熱可塑性の樹脂、エポキシ樹脂、ポリイミド樹脂、アクリル樹脂、フェノール樹脂またはフッ素系樹脂等がある。フッ素系樹脂としては例えば、四フッ化エチレン樹脂等がある。 Examples of resins used as materials for the insulating layers forming the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c and the other insulating layer 2e include thermoplastic resins, epoxy resins, polyimide resins, There are acrylic resin, phenolic resin, fluorine-based resin, and the like. Examples of fluorine-based resins include tetrafluoroethylene resin and the like.

第１絶縁層２ａの上面または／および第３絶縁層２ｃの下面にはその他の絶縁層２ｅを複数上下に積層して形成されていてもよい。第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｅから成る基体２は、図１に示すように６層の絶縁層から形成されていてもよいし、５層以下または７層以上の絶縁層から形成されていてもよい。絶縁層が５層以下の場合には、電子素子実装用基板１の薄型化を図ることができる。また、絶縁層が６層以上の場合には、電子素子実装用基板１の剛性を高めることができる。また、図１～図２に示す例のように、各絶縁層に開口部を設け、設けた開口部の大きさを異ならせた上面に段差部を形成していてもよく、後述する電極パッド３が段差部に設けられていてもよい。 A plurality of other insulating layers 2e may be stacked vertically on the upper surface of the first insulating layer 2a and/or the lower surface of the third insulating layer 2c. The substrate 2 comprising the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c and/or other insulating layers 2e may be formed from six insulating layers as shown in FIG. , 5 layers or less, or 7 layers or more. When the number of insulating layers is five or less, the thickness of the electronic element mounting substrate 1 can be reduced. Further, when the number of insulating layers is six or more, the rigidity of the electronic element mounting substrate 1 can be increased. Further, as in the examples shown in FIGS. 1 and 2, an opening may be provided in each insulating layer, and a stepped portion may be formed on the upper surface of the opening having a different size. 3 may be provided at the stepped portion.

電子素子実装用基板１は例えば、最外周の１辺の大きさは０．３ｍｍ～１０ｃｍであり、平面視において電子素子実装用基板１が矩形状あるとき、正方形であってもよいし長方形であってもよい。また例えば、電子素子実装用基板１の厚みは０．２ｍｍ以上である。 For example, the size of one side of the outermost periphery of the electronic device mounting substrate 1 is 0.3 mm to 10 cm. There may be. Further, for example, the thickness of the electronic element mounting board 1 is 0.2 mm or more.

電子素子実装用基板１は、第１絶縁層２ａと第２絶縁層２ｂとの間に位置する第１導体層５ａと、第２絶縁層２ｂと第３絶縁層２ｃとの間に位置する第２導体層５ｂを有している。また、電子素子実装用基板１の第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｃからなる基体２は表面に電極パッド３を有していてもよい。ここで電極パッド３は上面視において第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｃの何れかの表面に設けられていればよく、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｃの何れかの表面のいずれか、またはすべての絶縁層に設けられていてもよい。 The electronic device mounting substrate 1 includes a first conductor layer 5a positioned between the first insulating layer 2a and the second insulating layer 2b, and a second conductor layer 5a positioned between the second insulating layer 2b and the third insulating layer 2c. It has two conductor layers 5b. Further, the substrate 2 composed of the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c and the other insulating layer 2c of the electronic element mounting substrate 1 may have electrode pads 3 on the surface. Here, the electrode pad 3 may be provided on the surface of any one of the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c and/or the other insulating layer 2c when viewed from above. It may be provided on any or all of the surfaces of the layer 2a, the second insulating layer 2b, the third insulating layer 2c and/or the other insulating layers 2c.

基体２の上面、側面または下面には、外部回路接続用の電極が設けられていてもよい。外部回路接続用の電極は、基体２と外部回路基板、あるいは電子装置２１と外部回路基板とを電気的に接続するものである。 Electrodes for external circuit connection may be provided on the upper surface, side surface, or lower surface of the substrate 2 . The electrodes for external circuit connection electrically connect the substrate 2 and the external circuit board, or the electronic device 21 and the external circuit board.

さらに基体２の第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｃの上面または下面には、電極パッド３、第１導体層５ａ、第２導体層５ｂおよびその他の内部導体層と、内部導体同士を上下に接続する貫通導体が設けられていてもよい。これら内部導体層または貫通導体は、基体２の表面に露出していてもよい。この内部導体層または貫通導体によって、電極パッド３、第１導体層５ａ、第２導体層５ｂ、それ以外の内部導体層と外部回路接続用の電極はそれぞれ電気的に接続されていてもよい。 Further, on the upper or lower surface of the first insulating layer 2a, second insulating layer 2b, third insulating layer 2c and/or other insulating layer 2c of the substrate 2, the electrode pad 3, the first conductive layer 5a, the second conductive layer 5b and other internal conductor layers, and through conductors may be provided to vertically connect the internal conductors. These internal conductor layers or penetrating conductors may be exposed on the surface of the substrate 2 . The electrode pad 3, the first conductor layer 5a, the second conductor layer 5b, other internal conductor layers and the electrodes for external circuit connection may be electrically connected to each other by the internal conductor layers or through conductors.

電極パッド３、第１導体層５ａ、第２導体層５ｂ、外部回路接続用の電極、内部導体層および貫通導体は、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃおよびその他の絶縁層２ｅが電気絶縁性セラミックスから成る場合には、タングステン（Ｗ）、モリブデン（Ｍｏ）、マンガン（Ｍｎ）、銀（Ａｇ）若しくは銅（Ｃｕ）またはこれらから選ばれる少なくとも１種以上の金属材料を含有する合金等から成る。また、電極パッド３、第１導体層５ａ、第２導体層５ｂ、外部回路接続用の電極、内部導体および貫通導体は、第１絶縁層２ａ、第２絶縁層２ｂ、第２絶縁層２ｃおよびその他の絶縁層２ｅが樹脂から成る場合には、銅（Ｃｕ）、金（Ａｕ）、アルミニウム（Ａｌ）、ニッケル（Ｎｉ）、モリブデン（Ｍｏ）若しくはチタン（Ｔｉ）またはこれらから選ばれる少なくとも１種以上の金属材料を含有する合金等がある。 The electrode pads 3, the first conductor layer 5a, the second conductor layer 5b, the electrodes for external circuit connection, the internal conductor layers and the penetrating conductors are the first insulation layer 2a, the second insulation layer 2b, the third insulation layer 2c and other layers. When the insulating layer 2e is made of electrically insulating ceramics, tungsten (W), molybdenum (Mo), manganese (Mn), silver (Ag) or copper (Cu) or at least one metal selected from these It consists of an alloy or the like containing a material. The electrode pads 3, the first conductor layer 5a, the second conductor layer 5b, the electrodes for external circuit connection, the internal conductors and the penetrating conductors are composed of the first insulating layer 2a, the second insulating layer 2b, the second insulating layer 2c and the When the other insulating layer 2e is made of resin, copper (Cu), gold (Au), aluminum (Al), nickel (Ni), molybdenum (Mo), titanium (Ti), or at least one selected from these There are alloys and the like containing the above metal materials.

電極パッド３、外部回路接続用の電極、内部導体および貫通導体の露出表面に、めっき層が設けられてもよい。この構成によれば、外部回路接続用の電極、内部導体および貫通導体の露出表面を保護して酸化を抑制できる。また、この構成によれば、電極パッド３と電子素子１０とをワイヤボンディング等の電子素子接続材１３を介して良好に電気的接続することができる。めっき層は、例えば、厚さ０．５μｍ～１０μｍのＮｉめっき層を被着させるか、またはこのＮｉめっき層および厚さ０．５μｍ～３μｍの金（Ａｕ）めっき層を順次被着させてもよい。 A plating layer may be provided on the exposed surfaces of the electrode pads 3, the electrodes for external circuit connection, the internal conductors, and the through conductors. According to this configuration, the exposed surfaces of the electrodes for external circuit connection, the internal conductors, and the through conductors can be protected and oxidized. Moreover, according to this configuration, the electrode pads 3 and the electronic element 10 can be electrically connected well through the electronic element connecting material 13 such as wire bonding. The plating layer is, for example, a Ni plating layer with a thickness of 0.5 μm to 10 μm, or a Ni plating layer and a gold (Au) plating layer with a thickness of 0.5 μm to 3 μm. good.

第１導体層５ａは、第１の間５ａｇを有している。また、第１導体層５ａは、第１導体５ａａと第２導体５ａｂを有している。第１の間５ａｇは、第１導体５ａａと第２導体５ａｂとの間に位置している。この第１の間５ａｇにより、第１導体５ａａと第２導体５ａｂとは電気的に絶縁する事ができる。第１導体５ａａと第２導体５ａｂを絶縁する場合は第１導体５ａａと第２導体５ａｂとは異なる電源電位や異なるシグナル信号線となり、第１導体５ａａと第２導体５ａｂを絶縁しない場合は第３導体５ｂａと第４導体５ｂｂとは同じ電源電位や同じシグナル信号線となる。同じ電源電位や同じシグナル信号線の場合、たとえば別の部分例えば上層または下層で導通していてもよい。第１導体５ａａと第２導体５ａｂとの第１の間５ａｇは、例えば２０μｍ以上もしくは、基体２の１辺の１％以上であればよい。 The first conductor layer 5a has a first gap 5ag. Also, the first conductor layer 5a has a first conductor 5aa and a second conductor 5ab. The first gap 5ag is positioned between the first conductor 5aa and the second conductor 5ab. The first conductor 5aa and the second conductor 5ab can be electrically insulated by the first gap 5ag. When the first conductor 5aa and the second conductor 5ab are insulated, the first conductor 5aa and the second conductor 5ab have different power supply potentials and different signal signal lines. The third conductor 5ba and the fourth conductor 5bb have the same power supply potential and the same signal signal line. In the case of the same power supply potential and the same signal line, for example, they may be conductive in another part, such as an upper layer or a lower layer. The first gap 5ag between the first conductor 5aa and the second conductor 5ab may be, for example, 20 μm or more, or 1% or more of one side of the substrate 2. As shown in FIG.

第１導体５ａａと第２導体５ａｂは、グランドまたは電源電位に用いられる、べた状、つまりワイドプレーン状の導体であってもよい。また、第１導体５ａａと第２導体５ａｂとがグランドまたは電源電位に用いられるワイドプレーン状の導体であるとき、第１導体５ａａと第２導体５ａｂと第１の間５ａｇに例えば信号導体が設けられていてもよい。例えば、ワイドプレーンは、そのワイドプレーンの１辺が１５０μｍ以上であればよい。 The first conductor 5aa and the second conductor 5ab may be solid or wide plane conductors used for ground or power potential. When the first conductor 5aa and the second conductor 5ab are wide plane conductors used for ground or power supply potential, for example, a signal conductor is provided between the first conductor 5aa and the second conductor 5ab and the first conductor 5ag. may have been For example, the wide plane may have a side of 150 μm or more.

第２導体層５ｂは、第２の間５ｂｇを有している。また、第２導体層５ｂは、第３導体５ｂａと第４導体５ｂｂを有している。第２の間５ｂｇは、第３導体５ｂａと第４導体５ｂｂとの間に位置している。この第２の間５ｂｇにより、第３導体５ｂａと第４導体５ｂｂとは電気的に絶縁する事ができる。第３導体５ｂａと第４導体５ｂｂを絶縁する場合は、第３導体５ｂａと第４導体５ｂｂとは異なる電源電位や異なるシグナル信号線となり、第３導体５ｂａと第４導体５ｂｂを絶縁しない場合は、第３導体５ｂａと第４導体５ｂｂとは同じ電源電位や同じシグナル信号線となる。同じ電源電位や同じシグナル信号線の場合、別の部分例えば上層または下層で導通していてもよい。第３導体５ｂａと第４導体５ｂｂとの第２の間５ｂｇは、例えば２０μｍ以上もしくは、基体２の１辺の１％以上であればよい。 The second conductor layer 5b has a second gap 5bg. Also, the second conductor layer 5b has a third conductor 5ba and a fourth conductor 5bb. The second gap 5bg is located between the third conductor 5ba and the fourth conductor 5bb. The third conductor 5ba and the fourth conductor 5bb can be electrically insulated by the second gap 5bg. When the third conductor 5ba and the fourth conductor 5bb are insulated, the third conductor 5ba and the fourth conductor 5bb have different power supply potentials and different signal signal lines. , the third conductor 5ba and the fourth conductor 5bb have the same power supply potential and the same signal signal line. In the case of the same power supply potential and the same signal line, they may be conductive in another part, for example, an upper layer or a lower layer. The second gap 5bg between the third conductor 5ba and the fourth conductor 5bb may be, for example, 20 μm or more, or 1% or more of one side of the substrate 2.

第３導体５ｂａと第４導体５ｂｂは、グランドまたは電源電位に用いられるワイドプレーン状の導体であってもよい。また、第３導体５ｂａと第４導体５ｂｂとがグランドまたは電源電位に用いられるワイドプレーン状の導体であるとき、第３導体５ｂａと第４導体５ｂｂと第２の間５ｂｇに例えば信号導体が設けられていてもよい。例えば、ワイドプレーンは、そのワイドプレーンの１辺が１５０μｍ以上であればよい。平面視において、第１の間５ａｇは第２導体層５ｂと重なって位置しており、第２の間５ｂｇは、第１導体層５ａと重なって位置している。 The third conductor 5ba and the fourth conductor 5bb may be wide plane conductors used for ground or power potential. When the third conductor 5ba and the fourth conductor 5bb are wide plane conductors used for ground or power supply potential, for example, a signal conductor is provided between the third conductor 5ba and the fourth conductor 5bb and the second conductor 5bg. may have been For example, the wide plane may have a side of 150 μm or more. In plan view, the first gap 5ag overlaps the second conductor layer 5b, and the second gap 5bg overlaps the first conductor layer 5a.

内部導体（第１導体層５ａおよび第２導体層５ｂ）の厚みは電気抵抗を低減させる為により厚くする傾向にある。さらに、電子素子実装用基板１は薄型化の要求があり、各絶縁層（第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｅ）は薄くなっている。つまり、絶縁層の厚みに比べて、隙間の高さが高くなる傾向にある。言い換えると、内部導体がもつ隙間、つまり第１の間５ａｇおよび第２の間５ｂｇが上面視で複数層重なることになり、外部からの応力により基体２にクラックや割れが発生するおそれが高くなる。このような傾向から、外部からの応力により内部導体の隙間が上面視で複数重なる部分から基体２にクラックや割れが発生する事が懸念されていた。 The thickness of the internal conductors (the first conductor layer 5a and the second conductor layer 5b) tends to be increased in order to reduce electrical resistance. Further, there is a demand for a thinner electronic device mounting substrate 1, and each insulating layer (first insulating layer 2a, second insulating layer 2b, third insulating layer 2c and/or other insulating layers 2e) is becoming thinner. there is That is, the height of the gap tends to be higher than the thickness of the insulating layer. In other words, the gaps of the internal conductors, that is, the first gaps 5ag and the second gaps 5bg overlap in a plurality of layers when viewed from the top, increasing the risk of cracks or cracks occurring in the substrate 2 due to external stress. . Due to this tendency, there is concern that external stress may cause cracks or fractures in the substrate 2 from the overlapping portions of the gaps between the internal conductors when viewed from the top.

これに対し、本実施形態では第１の間５ａｇは第２導体層５ｂと重なって位置しており、第２の間５ｂｇは、第１導体層５ａと重なって位置する。このことで外部からの応力により内部導体の隙間が上面視で複数重なる部分から基板にクラックや割れが発生するおそれを低減する事が可能となる。 On the other hand, in this embodiment, the first gap 5ag is positioned to overlap the second conductor layer 5b, and the second gap 5bg is positioned to overlap the first conductor layer 5a. As a result, it is possible to reduce the risk of cracks or cracks occurring in the substrate due to stress from the outside at portions where the gaps between the internal conductors are overlapped when viewed from the top.

このとき、第１導体層５ａと第２導体層５ｂは、別の金属材料でもよく、同一の金属材料でもよい。別の金属もしくはその組成が異なる場合は、各導体層の平面形状と導体強度から最適な金属材料を第１導体層５ａと第２導体層５ｂに使用することで基体２の靱性強度を向上することができる。同一の金属もしくはその組成が同じ場合は、基板２の製造時に発生する不具合を軽減することが可能となる。 At this time, the first conductor layer 5a and the second conductor layer 5b may be made of different metal materials or the same metal material. When another metal or its composition is different, the toughness strength of the substrate 2 is improved by using an optimum metal material for the first conductor layer 5a and the second conductor layer 5b from the planar shape and conductor strength of each conductor layer. be able to. When the same metal or its composition is the same, it is possible to reduce defects that occur during the manufacture of the substrate 2 .

第１導体層５ａと第２導体層５ｂは、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃに、断面視で厚み方向の一部が埋め込まれていてもよい。第１導体層５ａと第２導体層５ｂの一部が埋め込まれている場合、導体層と絶縁層の接合強度が向上することができる。そのため結果的に、基体２の靱性強度を向上することにつながる。同様に、第１導体層５ａと第２導体層５ｂは、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃは、断面視で厚み方向の全体が埋め込まれていてもよい。全体が埋め込まれている場合、導体層と絶縁層の接合強度が更に向上することができる。そのため結果的に、基体２の靱性強度を向上することにつながる。また、第１導体層５ａと第２導体層５ｂの端部の断面形状は、図１、図２～図３（ａ）に示す例の様に片刃形状、台形形状でもよく、図３（ｂ）に示す例のレンズ形状の様に他の形状でも構わない。例えばレンズ形状の場合は、第１導体層５ａ／第２導体層５ｂの端部の断面形状がよりなめらかになる。このことで例えば第１導体層５ａと第２導体層５ｂの形状が表面に現れた場合でも基体２の表面形状がなだらかになることで、電子素子１０や蓋体１２などの接合不良や傾き不良などの実装の不具体の低減を図ることができる。 The first conductor layer 5a and the second conductor layer 5b may be partly embedded in the thickness direction of the first insulating layer 2a, the second insulating layer 2b, and the third insulating layer 2c in a cross-sectional view. When the first conductor layer 5a and the second conductor layer 5b are partially embedded, the bonding strength between the conductor layer and the insulating layer can be improved. As a result, this leads to an improvement in toughness strength of the substrate 2 . Similarly, the first conductor layer 5a and the second conductor layer 5b, the first insulating layer 2a, the second insulating layer 2b, and the third insulating layer 2c may be entirely embedded in the thickness direction in a cross-sectional view. When the whole is embedded, the bonding strength between the conductor layer and the insulating layer can be further improved. As a result, this leads to an improvement in toughness strength of the substrate 2 . The cross-sectional shapes of the ends of the first conductor layer 5a and the second conductor layer 5b may be single-edged or trapezoidal as shown in FIGS. 1 and 2 to 3(a). ), other shapes such as the lens shape shown in FIG. For example, in the case of a lens shape, the cross-sectional shape of the end portion of the first conductor layer 5a/second conductor layer 5b becomes smoother. As a result, for example, even when the shapes of the first conductor layer 5a and the second conductor layer 5b appear on the surface, the surface shape of the substrate 2 is smoothed, which may cause defective bonding or tilting of the electronic element 10, the lid 12, or the like. It is possible to reduce imprecise implementation such as.

図３に要部Ａを示す。図３（ａ）の様に、第１の間５ａｇと、第２の間５ｂｇとは一部が重なっていてもよい。このような場合においても、第１の間５ａｇと第２の間５ｂｇの重なっている部分を小さくすることができるので、基体２の靱性強度を向上することが可能となり、クラックや割れの発生の懸念を低減することが可能となる。また、第１の間５ａｇと、第２の間５ｂｇの重なっている部分を小さくすることで、基体２の表面形状がなめらかになり、電子素子１０や蓋体１２などの実装の不具合の低減を図ることができる。 FIG. 3 shows the main part A. As shown in FIG. As shown in FIG. 3A, the first gap 5ag and the second gap 5bg may partially overlap. Even in such a case, it is possible to reduce the overlapping portion of the first gap 5ag and the second gap 5bg, so that the toughness of the substrate 2 can be improved, and the occurrence of cracks and cracks can be prevented. It becomes possible to reduce concerns. Further, by reducing the overlapping portion of the first gap 5ag and the second gap 5bg, the surface shape of the substrate 2 becomes smooth, and defects in mounting the electronic element 10, the lid 12, etc. can be reduced. can be planned.

さらに、図３（ｂ）の様に第１の間５ａｇと第２の間５ｂｇとが離れていてもよい。例えば、第１の間５ａｇと第２の間５ｂｇの幅の狭い隙間以上に離れているとよい。第１の間５ａｇと、第２の間５ｂｇとが重ならないことで、さらに基体２の靱性強度を向上することが可能となる。クラックや割れが発生することの懸念を低減することが可能となる。また、第１の間５ａｇと、第２の間５ｂｇとが重ならないことで、基体２の表面形状が更になめらかになり、電子素子１０や蓋体１２などの実装の不具合を更に低減するができる。 Furthermore, the first gap 5ag and the second gap 5bg may be separated as shown in FIG. 3(b). For example, it is preferable that the first gap 5ag and the second gap 5bg are separated from each other by a narrow gap or more. By not overlapping the first gap 5ag and the second gap 5bg, it is possible to further improve the toughness of the base body 2 . It is possible to reduce concerns about the occurrence of cracks and cracks. Further, since the first gap 5ag and the second gap 5bg do not overlap, the surface shape of the base body 2 becomes smoother, and defects in mounting the electronic element 10, the lid body 12, etc. can be further reduced. .

図４～図６を参照して第１導体層５ａ、第２導体層５ｂの形状について説明する。図４（ａ）は、第２絶縁層２ｂ上に第１導体層５ａが配置されていることを示しており、図４（ｂ）は、第３絶縁層２ｃ上に第２導体層５ｂが配置されていることを示している。また、α１は基体２の中心を通りＸ軸に平行な仮想線を、α２は基体２の中心を通りＹ軸に変更な仮想線を表している。基体２の仮想線α１、α２を図４～図６中に２点鎖線で示す。 The shapes of the first conductor layer 5a and the second conductor layer 5b will be described with reference to FIGS. 4 to 6. FIG. FIG. 4(a) shows that the first conductor layer 5a is arranged on the second insulating layer 2b, and FIG. 4(b) shows that the second conductor layer 5b is arranged on the third insulating layer 2c. It shows that it is placed. Also, α1 represents a virtual line passing through the center of the base 2 and parallel to the X-axis, and α2 represents a virtual line passing through the center of the base 2 and parallel to the Y-axis. Virtual lines α1 and α2 of the substrate 2 are indicated by two-dot chain lines in FIGS.

図４に示す例では第１の間５ａｇの位置する部分の第１導体５ａａの外縁と第２導体５ａｂの外縁の導体形状は直線状になっている。第２の間５ｂｇの位置する部分の第３導体５ｂａと第４導体５ｂｂの導体形状も直線状になっている。また、第１の間５ａｇは、上面視で第３導体５ｂａと重なっており、第２の間５ｂｇは第２導体５ａｂと重なっている。 In the example shown in FIG. 4, the outer edge of the first conductor 5aa and the outer edge of the second conductor 5ab in the portion where the first gap 5ag is positioned are linear. The conductor shapes of the third conductor 5ba and the fourth conductor 5bb in the portion where the second gap 5bg is located are also linear. The first gap 5ag overlaps the third conductor 5ba in top view, and the second gap 5bg overlaps the second conductor 5ab.

このような場合でも、第１の間５ａｇと、第２の間５ｂｇの重なっている部分を小さくすることで、基体２の靱性強度を向上することが可能となり、基体２にクラックや割れの発生の懸念を低減することが可能となる。 Even in such a case, by reducing the overlapping portion of the first gap 5ag and the second gap 5bg, it is possible to improve the toughness of the base body 2, and the base body 2 may crack or split. It is possible to reduce concerns about

図４では、上面視で第１の間５ａｇと第３導体５ｂａ、第２の間５ｂｇと第２導体５ａｂが重なっているが、上面視で第１の間５ａｇと第４導体５ｂｂ、第２の間５ｂｇと第１導体５ａａと重なっても第１の間５ａｇと、第２の間５ｂｇの重なっている部分を小さくすることで、基体２の靱性強度を向上することが可能となり、基体２にクラックや割れの発生の懸念を低減することが可能となる。 In FIG. 4, the first gap 5ag and the third conductor 5ba, and the second gap 5bg and the second conductor 5ab overlap when viewed from above. Even if the gap 5bg overlaps the first conductor 5aa, by reducing the overlapping portion of the first gap 5ag and the second gap 5bg, it is possible to improve the toughness of the base body 2. It is possible to reduce concerns about the occurrence of cracks and splits.

さらに、図４の様に導体層５ａと導体層５ｂが基体２全体に配置されることで基体２の靱性強度を向上することが可能となり、基体２にクラックや割れの発生の懸念を低減することが可能となる。導体層５ａと導体層５ｂがグランドまたは電源電位に用いられるワイドプレーン状の導体の場合、電源抵抗が低くなり電源ノイズの低減の効果も得られる。 Furthermore, by arranging the conductor layers 5a and 5b over the entire substrate 2 as shown in FIG. becomes possible. When the conductor layers 5a and 5b are wide-plane conductors used for ground or power supply potential, the power supply resistance is low, and the effect of reducing power supply noise is also obtained.

図５に示す例では、第１の間５ａｇの位置する部分の第１導体５ａａの外縁と第２導体５ａｂの外縁の導体形状と第２の間５ｂｇの位置する部分の第３導体５ｂａの外縁と第４導体５ｂｂの外縁の導体形状が、角度をもって直線的に蛇行している。さらに、上面視で第１の間５ａｇと第３導体５ｂａまたは/および第４導体５ｂｂ、第２の間５ｂｇと第１導体５ａａまたは/および第２導体５ａｂが重なっている。 In the example shown in FIG. 5, the conductor shape of the outer edge of the first conductor 5aa and the outer edge of the second conductor 5ab in the portion located at the first interval 5ag and the outer edge of the third conductor 5ba in the portion located at the second interval 5bg , and the conductor shape of the outer edge of the fourth conductor 5bb linearly meanders with an angle. Further, the first gap 5ag and the third conductor 5ba and/or the fourth conductor 5bb overlap, and the second gap 5bg and the first conductor 5aa and/or the second conductor 5ab overlap in top view.

図５に示すように第１の間５ａｇと第２の間５ｂｇが蛇行することで、第１の間５ａｇと第２の間５ｂｇの重なっている部分を小さくできる。このことから基体２の靱性強度を向上することが可能となり、基体２にクラックや割れの発生の懸念を低減することが可能となる。 As shown in FIG. 5, by meandering the first gap 5ag and the second gap 5bg, the overlapping portion of the first gap 5ag and the second gap 5bg can be reduced. As a result, it is possible to improve the toughness of the base 2 and reduce the risk of cracks or splits occurring in the base 2 .

なお、ここで蛇行とは、導体の外縁が直線で角度を持って曲がっている形状が連なった形状を指している。つまり、上面視において直線状になっている箇所を有している。このときの角度や、直線部の大きさなどは指定される必要はない。図６に示す例では、第１の間５ａｇの位置する部分の第１導体５ａａの外縁と第２導体５ａｂの外縁の導体形状と第２の間５ｂｇの位置する部分の第３導体５ｂａの外縁と第４導体５ｂｂの外縁の導体形状が、曲線でウエーブ形状となっている。 Here, meandering refers to a shape in which the outer edge of the conductor is straight and curved at an angle. In other words, it has a linear portion when viewed from above. At this time, it is not necessary to specify the angle or the size of the straight portion. In the example shown in FIG. 6, the conductor shape of the outer edge of the first conductor 5aa and the outer edge of the second conductor 5ab in the portion located at the first interval 5ag and the outer edge of the third conductor 5ba in the portion located at the second interval 5bg and the outer edge of the fourth conductor 5bb is a curved wave shape.

図６に示す例の様にウエーブ形状になることで、図５の第１の間５ａｇの位置する部分の第１導体５ａａの外縁と第２導体５ａｂの外縁の導体形状と第２の間５ｂｇの位置する部分の第３導体５ｂａの外縁と第４導体５ｂｂの外縁の導体形状の鋭角部分をなくすことができる。このことにより第１導体層５ａおよび第２導体層５ｂの角部での応力集中を低減することができる。その為局部的な応力集中のおそれを低減することができ、クラックや割れの発生の懸念を低減することが可能となる。 By forming a wave shape as in the example shown in FIG. 6, the outer edge of the first conductor 5aa and the outer edge of the second conductor 5ab in FIG. It is possible to eliminate an acute-angled portion of the conductor shape of the outer edge of the third conductor 5ba and the outer edge of the fourth conductor 5bb in the portion where the . As a result, stress concentration at the corners of the first conductor layer 5a and the second conductor layer 5b can be reduced. Therefore, it is possible to reduce the possibility of local stress concentration, and to reduce the concern of the occurrence of cracks and cracks.

なお、ここでウエーブ形状とは、導体の外縁が曲線で連なった形状を指している。この時の曲線の方向や、曲線の半径の大きさなどは指定される必要はない。 Here, the wave shape refers to a shape in which the outer edges of the conductor are connected with curved lines. At this time, the direction of the curve and the size of the radius of the curve do not need to be specified.

図４～図６では、第１導体５ａａ、第２導体５ａｂ、第３導体５ｂａおよび第４導体５ｂｂの外縁形状の一例を説明したが、第１導体５ａａ、第２導体５ａｂ、第３導体５ｂａおよび第４導体５ｂｂは上記以外の他の形状、例えば１か所だけでなく数カ所の間を配置させることができる。また、上下の導体層間の形状を変えることも可能である。これらの組み合わせで多様な形状であっても、第１の間５ａｇと第２の間５ｂｇが本実施形態の条件を満たすことで、基体２のクラックや割れの発生を低減することが可能となる。 4 to 6 illustrate examples of outer edge shapes of the first conductor 5aa, the second conductor 5ab, the third conductor 5ba, and the fourth conductor 5bb. and the fourth conductor 5bb may be arranged in other shapes than those described above, for example not only in one place but also in several places. It is also possible to change the shape between the upper and lower conductor layers. Even if these combinations have various shapes, the first gap 5ag and the second gap 5bg satisfy the conditions of the present embodiment, so that the occurrence of cracks and fractures in the base body 2 can be reduced. .

＜電子装置の構成＞
図１～図２に電子装置２１の例を示す。電子装置２１は、電子素子実装用基板１と、電子素子実装用基板１に実装された電子素子１０を備えている。 <Structure of Electronic Device>
An example of an electronic device 21 is shown in FIGS. The electronic device 21 includes an electronic element mounting board 1 and an electronic element 10 mounted on the electronic element mounting board 1 .

電子装置２１は、電子素子実装用基板１と、電子素子実装用基板１に実装された電子素子１０を有している。電子素子１０は、例えばＣＭＯＳ（Complementary Metal Oxide Semiconductor）、ＣＣＤ（Charge Coupled Device）等の撮像素子、またはＬＥＤ（Light Emitting Diode）などの発光素子、またはＬＳＩ（Large Scale Integrated）等の集積回路等である。なお、電子素子１０は、接着材を介して、基体２の上面に配置されていてもよい。この接着材は、例えば、銀エポキシまたは熱硬化性樹脂等が使用される。 The electronic device 21 has an electronic element mounting board 1 and an electronic element 10 mounted on the electronic element mounting board 1 . The electronic element 10 is, for example, an imaging element such as a CMOS (Complementary Metal Oxide Semiconductor) or a CCD (Charge Coupled Device), a light emitting element such as an LED (Light Emitting Diode), or an integrated circuit such as an LSI (Large Scale Integrated). be. Note that the electronic element 10 may be arranged on the upper surface of the base 2 via an adhesive. For this adhesive, for example, silver epoxy or thermosetting resin is used.

電子装置２１は、電子素子１０を覆うとともに、電子素子実装用基板１の上面に接合された蓋体１２を有していてもよい。ここで、電子素子実装用基板１は基体２枠状部分の上面に蓋体１２を接続してもよいし、蓋体１２支え、基体２の上面であって電子素子１０を取り囲むように設けられた枠状体を設けてもよい。また、枠状体と基体２とは同じ材料から構成されていてもよいし、別の材料で構成されていてもよい。 The electronic device 21 may have a lid 12 that covers the electronic element 10 and is joined to the upper surface of the electronic element mounting board 1 . Here, the electronic element mounting substrate 1 may have a cover 12 connected to the upper surface of the frame-shaped portion of the base 2, or may support the cover 12 and be provided on the upper surface of the base 2 so as to surround the electronic element 10. A frame-shaped body may be provided. Further, the frame-shaped body and the base 2 may be made of the same material, or may be made of different materials.

枠状体と基体２と、が同じ材料から成る場合、基体２は枠状体とは開口部を設けるなどして最上層の絶縁層と一体化するように作られていてもよいし、別に設けるろう材等でそれぞれ接合してもよい。 When the frame-shaped body and the base body 2 are made of the same material, the base body 2 may be formed so as to be integrated with the uppermost insulating layer by, for example, providing an opening with the frame-shaped body. They may be joined with a brazing material or the like provided.

また、基体２と枠状体とが別の材料から成る例として枠状体が蓋体１２と基体２とを接合する蓋体接合材１４と同じ材料から成る場合がある。このとき、蓋体接合材１４を厚く設けることで、接着の効果と枠状体（蓋体１２を支える部材）としての効果を併せ持つことが可能となる。このときの蓋体接合材１４は例えば熱硬化性樹脂または低融点ガラスまたは金属成分から成るろう材等が挙げられる。また、枠状体と蓋体１２とが同じ材料から成る場合もあり、このときは枠状体と蓋体１２は同一個体として構成されていてもよい。 Further, as an example in which the base body 2 and the frame-shaped body are made of different materials, the frame-shaped body may be made of the same material as the cover bonding material 14 that joins the cover body 12 and the base body 2 together. At this time, by providing the cover bonding material 14 thickly, it is possible to have both the effect of adhesion and the effect of the frame-like body (member supporting the cover 12). The lid bonding material 14 at this time may be, for example, thermosetting resin, low-melting-point glass, brazing material made of a metal component, or the like. Moreover, the frame-shaped body and the lid body 12 may be made of the same material, and in this case, the frame-shaped body and the lid body 12 may be configured as the same individual.

蓋体１２は、例えば電子素子１０がＣＭＯＳ、ＣＣＤ等の撮像素子、またはＬＥＤなどの発光素子である場合ガラス材料等の透明度の高い部材が用いられる。また蓋体１２は例えば、電子素子１０が集積回路等であるとき、金属製材料または有機材料が用いられていてもよい。 For example, when the electronic device 10 is an imaging device such as a CMOS or CCD, or a light emitting device such as an LED, a highly transparent member such as a glass material is used for the lid 12 . Further, for example, when the electronic element 10 is an integrated circuit or the like, the lid 12 may be made of a metallic material or an organic material.

蓋体１２は、蓋体接合材１４を介して電子素子実装用基板１と接合している。蓋体接合材１４を構成する材料として例えば、熱硬化性樹脂または低融点ガラスまたは金属成分から成るろう材等がある。 The lid 12 is bonded to the electronic device mounting substrate 1 via the lid bonding material 14 . Examples of the material forming the lid bonding material 14 include thermosetting resin, low-melting-point glass, brazing material made of metal components, and the like.

電子装置２１は、図１～図２に示すような電子素子実装用基板１を有する。電子素子実装用基板１に実装される電子素子１０や蓋体１２などと、第１の間５ａｇと第２の間５ｂｇが上面視で重なる場合は、電子装置２１の靱性を向上させることが可能となる。このことから電子素子実装用基板１のクラックや割れの可能性を低減でき、クラックや割れによる電子装置２１の誤動作の低減が可能となる。 The electronic device 21 has an electronic element mounting board 1 as shown in FIGS. When the electronic device 10 and the lid 12 mounted on the electronic device mounting substrate 1 overlap the first gap 5ag and the second gap 5bg in top view, the toughness of the electronic device 21 can be improved. becomes. Therefore, it is possible to reduce the possibility of the electronic element mounting substrate 1 cracking or cracking, and to reduce the malfunction of the electronic device 21 due to the cracking or cracking.

＜電子モジュールの構成＞
図２に電子素子実装用基板１を用いた電子モジュール３１の一例を示す。電子モジュール３１は、電子装置２１と電子装置２１の上面または電子装置２１を覆うように設けられた筐体３２とを有している。なお、以下に示す例では説明のため撮像モジュールを例に説明する。 <Structure of electronic module>
FIG. 2 shows an example of an electronic module 31 using the electronic element mounting board 1 . The electronic module 31 has an electronic device 21 and a housing 32 provided so as to cover the upper surface of the electronic device 21 or the electronic device 21 . For the sake of explanation, the following example will be described using an imaging module as an example.

電子モジュール３１は筐体３２（レンズホルダー）を有している。筐体３２を有することでより気密性の向上または外部からの応力が直接電子装置２１に加えられることを低減することが可能となる。筐体３２は、例えば樹脂または金属材料等から成る。また、筐体３２がレンズホルダーであるとき筐体３２は、樹脂、液体、ガラスまたは水晶等からなるレンズが１個以上組み込まれていてもよい。また、筐体３２は、上下左右の駆動を行う駆動装置等が付いていて、電子素子実装用基板１と電気的に接続されていてもよい。 The electronic module 31 has a housing 32 (lens holder). Having the housing 32 makes it possible to improve the airtightness or reduce the direct application of external stress to the electronic device 21 . The housing 32 is made of, for example, resin or metal material. Further, when the housing 32 is a lens holder, the housing 32 may incorporate one or more lenses made of resin, liquid, glass, crystal, or the like. Further, the housing 32 may be provided with a driving device or the like for driving up, down, left, and right, and may be electrically connected to the electronic element mounting board 1 .

なお、筐体３２は上面視において４方向の少なくとも一つの辺において開口部が設けられていてもよい。そして、筐体３２の開口部から外部回路基板が挿入され電子素子実装用基板１と電気的に接続していてもよい。また筐体３２の開口部は、外部回路基板が電子素子実装用基板１と電気的に接続された後、樹脂等の封止材等で開口部の隙間を閉じて電子モジュール３１の内部が気密されていてもよい。 The housing 32 may have openings on at least one side in four directions when viewed from above. An external circuit board may be inserted through the opening of the housing 32 and electrically connected to the electronic element mounting board 1 . After the external circuit board is electrically connected to the electronic element mounting board 1, the opening of the housing 32 is closed with a sealing material such as resin to keep the inside of the electronic module 31 airtight. may have been

電子モジュール３１は、図２に示すような電子素子実装用基板１を有する。電子素子実装用基板１に実装される電子素子１０や蓋体１２や筐体３２と、第１の間５ａｇと第２の間５ｂｇが上面視で重なる場合は、電子モジュール３１の靱性を向上させることが可能となる。このことから電子素子実装用基板１のクラックや割れの可能性を低減でき、クラックや割れによる電子モジュール３１の誤動作の低減が可能となる。 The electronic module 31 has an electronic element mounting board 1 as shown in FIG. When the electronic element 10, the lid 12, or the housing 32 mounted on the electronic element mounting substrate 1 overlaps the first gap 5ag and the second gap 5bg in top view, the toughness of the electronic module 31 is improved. becomes possible. As a result, it is possible to reduce the possibility of the electronic element mounting substrate 1 cracking or cracking, and to reduce the malfunction of the electronic module 31 due to the cracking or cracking.

＜電子素子実装用基板および電子装置の製造方法＞
次に、本実施形態の電子素子実装用基板１および電子装置２１の製造方法の一例について説明する。なお、下記で示す製造方法の一例は、基体２を多数個取り配線基板を用いた製造方法である。 <Electronic device mounting board and manufacturing method for electronic device>
Next, an example of a method for manufacturing the electronic element mounting substrate 1 and the electronic device 21 of this embodiment will be described. An example of the manufacturing method described below is a manufacturing method using a multi-piece wiring substrate for the substrate 2 .

（１）まず、基体２を構成するセラミックグリーンシートを形成する。例えば、酸化アルミニウム（Ａｌ２Ｏ３）質焼結体である基体２を得る場合には、Ａｌ２Ｏ３の粉末に焼結助材としてシリカ（ＳｉＯ２）、マグネシア（ＭｇＯ）またはカルシア（ＣａＯ）等の粉末を添加し、さらに適当なバインダー、溶剤および可塑剤を添加し、次にこれらの混合物を混錬してスラリー状となす。その後、ドクターブレード法またはカレンダーロール法等の成形方法によって多数個取り用のセラミックグリーンシートを得る。 (1) First, a ceramic green sheet constituting the substrate 2 is formed. For example, when obtaining the substrate 2 which is an aluminum oxide (Al 2 O 3 ) based sintered body, silica (SiO 2 ), magnesia (MgO) or calcia (CaO) is added to Al 2 O 3 powder as a sintering aid. ) are added, followed by the addition of suitable binders, solvents and plasticizers, and then the mixture is kneaded to form a slurry. After that, a molding method such as a doctor blade method or a calender roll method is used to obtain a ceramic green sheet for multi-piece production.

なお、基体２が、例えば樹脂から成る場合は、所定の形状に成形できるような金型を用いて、トランスファーモールド法またはインジェクションモールド法等で成形することによって基体２を形成することができる。また、基体２は、例えばガラスエポキシ樹脂のように、ガラス繊維から成る基材に樹脂を含浸させたものであってもよい。この場合には、ガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって基体２を形成できる。 When the substrate 2 is made of resin, for example, the substrate 2 can be formed by molding using a mold that can be molded into a predetermined shape by a transfer molding method, an injection molding method, or the like. Further, the substrate 2 may be a substrate made of glass fiber impregnated with a resin such as a glass epoxy resin. In this case, the substrate 2 can be formed by impregnating a substrate made of glass fiber with an epoxy resin precursor and thermally curing the epoxy resin precursor at a predetermined temperature.

（２）次に、スクリーン印刷法等によって、上記（１）の工程で得られたセラミックグリーンシートに金属層（第１導体層５ａや第２導体層５ｂなど）、電極パッド３、外部回路接続用電極、内部配線および貫通導体となる部分に、金属ペーストを塗布または充填する。この金属ペーストは、前述した金属材料から成る金属粉末に適当な溶剤およびバインダーを加えて混練することによって、適度な粘度に調整して作製される。なお、金属ペーストは、基体２との接合強度を高めるために、ガラスまたはセラミックスを含んでいても構わない。 (2) Next, metal layers (first conductor layer 5a, second conductor layer 5b, etc.), electrode pads 3, and external circuit connections are formed on the ceramic green sheet obtained in step (1) by screen printing or the like. A metal paste is applied or filled on the parts that will become the internal electrodes, internal wiring, and through conductors. This metal paste is prepared by adjusting the viscosity to an appropriate level by adding a suitable solvent and binder to the metal powder made of the metal material described above and kneading the mixture. In addition, the metal paste may contain glass or ceramics in order to increase the bonding strength with the substrate 2 .

例えば、第１の間５ａｇを作成する場合は、第１導体５ａａと第２導体５ａｂとの間に所定の隙間を設けて金属ペーストを塗布することで作成することができる。同様に第２の間５ｂｇを作成する場合は、第３導体５ｂａと第４導体５ｂｂとの間に所定の隙間を設けて金属ペーストを塗布することで作成することができる。 For example, when creating the first gap 5ag, it can be created by providing a predetermined gap between the first conductor 5aa and the second conductor 5ab and applying a metal paste. Similarly, when creating the second gap 5bg, it can be created by providing a predetermined gap between the third conductor 5ba and the fourth conductor 5bb and applying a metal paste.

（３）次に、前述のグリーンシートを金型等によって加工する。ここで基体２がキャスタレーション、キャビティ等になる凹部またはノッチ等を有する場合、基体２となるグリーンシートの所定の箇所に、凹部（貫通孔）またはノッチ等を形成してもよい。 (3) Next, the aforementioned green sheet is processed with a mold or the like. If the substrate 2 has recesses or notches that serve as castellations, cavities, etc., recesses (through-holes) or notches may be formed at predetermined locations on the green sheet that serves as the substrate 2 .

（４）次に、各絶縁層となるセラミックグリーンシートを積層して加圧する。このことにより各絶縁層となるグリーンシートを積層し、基体２（電子素子実装用基板１）となるセラミックグリーンシート積層体を作製してもよい。 (4) Next, ceramic green sheets to be each insulating layer are laminated and pressed. As a result, the green sheets to be each insulating layer may be laminated to produce a ceramic green sheet laminate to be the base 2 (electronic device mounting board 1).

（５）次に、このセラミックグリーンシート積層体を約１５００℃～１８００℃の温度で焼成して、基体２（電子素子実装用基板１）が複数配列された多数個取り配線基板を得る。なお、この工程によって、前述した金属ペーストは、基体２（電子素子実装用基板１）となるセラミックグリーンシートと同時に焼成され、導体層（第１導体層５ａおよび第２導体層５ｂなど）、電極パッド３、外部回路接続用電極、内部配線および貫通導体となる。 (5) Next, this ceramic green sheet laminate is fired at a temperature of about 1500° C. to 1800° C. to obtain a multi-cavity wiring board on which a plurality of substrates 2 (electronic element mounting substrates 1) are arranged. In this step, the metal paste described above is fired at the same time as the ceramic green sheet serving as the substrate 2 (electronic device mounting substrate 1), and the conductor layers (the first conductor layer 5a and the second conductor layer 5b, etc.), the electrodes. It becomes a pad 3, an electrode for external circuit connection, an internal wiring and a penetrating conductor.

（６）次に、焼成して得られた多数個取り配線基板を複数の基体２（電子素子実装用基板１）に分断する。この分断においては、基体２（電子素子実装用基板１）の外縁となる箇所に沿って多数個取り配線基板に分割溝を形成しておき、この分割溝に沿って破断させて分割する方法またはスライシング法等により基体２（電子素子実装用基板１）の外縁となる箇所に沿って切断する方法等を用いることができる。なお、分割溝は、焼成後にスライシング装置により多数個取り配線基板の厚みより小さく切り込むことによって形成することができるが、多数個取り配線基板用のセラミックグリーンシート積層体にカッター刃を押し当てたり、スライシング装置によりセラミックグリーンシート積層体の厚みより小さく切り込んだりすることによって形成してもよい。なお、上述した多数個取り配線基板を複数の基体２（電子素子実装用基板１）に分割する前もしくは分割した後に、それぞれ電解または無電解めっき法を用いて、電極パッド３、外部接続用パッドおよび露出した配線導体にめっきを被着させてもよい。 (6) Next, the multi-cavity wiring board obtained by firing is divided into a plurality of substrates 2 (electronic element mounting substrates 1). In this division, a division groove is formed in the multi-cavity wiring board along the outer edge of the substrate 2 (electronic device mounting board 1), and the wiring board is broken along the division groove to divide. A method such as a slicing method or the like can be used in which the substrate 2 (electronic element mounting substrate 1) is cut along the outer edge thereof. Incidentally, the dividing grooves can be formed by cutting with a slicing apparatus after firing to a size smaller than the thickness of the multi-cavity wiring board. It may be formed by cutting the ceramic green sheet laminate to a size smaller than the thickness thereof using a slicing machine. Before or after dividing the multi-cavity wiring board described above into a plurality of substrates 2 (electronic element mounting substrates 1), the electrode pads 3 and the external connection pads are formed by electrolytic or electroless plating, respectively. and exposed wiring conductors may be plated.

（７）次に、電子素子実装用基板１の上面または下面に電子素子１０を実装する。電子素子１０はワイヤボンディング等で電子素子実装用基板１と電気的に接合させる。またこのとき、電子素子１０または電子素子実装用基板１に接着材等を設け、電子素子実装用基板１に固定しても構わない。また、電子素子１０を電子素子実装用基板１に実装した後、蓋体１２を蓋体接合材１４で接合してもよい。 (7) Next, the electronic device 10 is mounted on the upper or lower surface of the electronic device mounting board 1 . The electronic element 10 is electrically connected to the electronic element mounting substrate 1 by wire bonding or the like. At this time, the electronic element 10 or the electronic element mounting substrate 1 may be fixed to the electronic element mounting substrate 1 by providing an adhesive or the like. Further, after the electronic element 10 is mounted on the electronic element mounting substrate 1 , the lid 12 may be bonded with the lid bonding material 14 .

以上（１）～（６）の工程の様にして電子素子実装用基板１を作製し、（７）の工程の様に電子素子１０を実装することで、電子装置２１を作製することができる。なお、上記（１）～（７）の工程順番は指定されない。 The electronic device 21 can be manufactured by manufacturing the electronic device mounting board 1 in the steps (1) to (6) above and mounting the electronic device 10 in the step (7). . The order of steps (1) to (7) is not specified.

（第２の実施形態）
次に、本発明の第２の実施形態による電子素子実装用基板１について、図７～図８を参照しつつ説明する。なお、図７は本実施形態における電子素子実装用基板１および電子装置２１の形状を示す。図８は要部Ｂを示す。 (Second embodiment)
Next, an electronic device mounting substrate 1 according to a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 shows the shapes of the electronic element mounting substrate 1 and the electronic device 21 in this embodiment. FIG. 8 shows the main part B. FIG.

本実施形態における電子素子実装用基板１において、第１の実施形態の電子素子実装用基板１と異なる点は、第３絶縁層２ｃの下面に位置した第４絶縁層２ｄと、第３絶縁層２ｃと第４絶縁層２ｄとの間に位置した、第３の間５ｃｇを有する第３導体層５ｃとをさらに有している点である。第３の間５ｃｇは、第１導体層５ａおよび第２導体層５ｂと重なって位置しているとともに、第１の間５ａｇおよび第２の間５ｂｇは、第３導体層と重なって位置している点である。 The electronic device mounting substrate 1 of the present embodiment differs from the electronic device mounting substrate 1 of the first embodiment in that the fourth insulating layer 2d located on the lower surface of the third insulating layer 2c and the third insulating layer 2c and a third conductor layer 5c having a third gap 5cg located between the fourth insulating layer 2d. The third gap 5cg overlaps the first conductor layer 5a and the second conductor layer 5b, and the first gap 5ag and the second gap 5bg overlap the third conductor layer. This is the point.

図７に示す例では、第３絶縁層２ｃの下面に位置した第４絶縁層２ｄを有している。第３絶縁層２ｃと第４絶縁層２ｄとの間に位置した、第３の間５ｃｇを有する第３導体層５ｃとをさらに有している。 The example shown in FIG. 7 has a fourth insulating layer 2d located on the lower surface of the third insulating layer 2c. It further has a third conductor layer 5c having a third gap 5cg located between the third insulating layer 2c and the fourth insulating layer 2d.

内部導体（第１導体層５ａ、第２導体層５ｂおよび第３導体層５ｃ）の厚みは電気抵抗を低減させる為により厚くする傾向にある。さらに、電子素子実装用基板１は薄型化の要求があり、各絶縁層（第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃ、第４絶縁層２ｄまたは／およびその他の絶縁層２ｅ）は薄くなっている。言い換えると、内部導体がもつ隙間、第１の間５ａｇ、第２の間５ｂｇおよび第３の間５ｃｇが上面視で複数層重なることになり、内部導体がもつ隙間が上面視で複数層重なることになり、外部からの応力により基体２にクラックや割れが発生する可能性が高くなる。このような傾向から、外部からの応力により内部導体の隙間が上面視で重なる部分から基体２板にクラックや割れが発生する事が懸念されていた。図８（ａ）に示す例では、第３の間５ｃｇは、第１導体層５ａおよび第２導体層５ｂと重なって位置し、第１の間５ａｇおよび第２の間５ｂｇは、第３導体層と重なって位置している。このことで外部からの応力による第１導体層５ａおよび第２導体層５ｂの第３の間５ｃｇと第２の間５ｂｇが重なった面積を低減でき、第３の間５ｃｇと第２の間５ｂｇが重なった部分から基体２にクラックや割れが発生する可能性を低減する事が可能となる。 The thickness of the internal conductors (the first conductor layer 5a, the second conductor layer 5b and the third conductor layer 5c) tends to be thicker in order to reduce the electrical resistance. Further, there is a demand for a thinner electronic device mounting board 1, and each insulating layer (first insulating layer 2a, second insulating layer 2b, third insulating layer 2c, fourth insulating layer 2d or/and other insulating layers) 2e) is thinner. In other words, the gaps of the internal conductors, the first gap 5ag, the second gap 5bg, and the third gap 5cg overlap in multiple layers when viewed from the top, and the gaps of the internal conductor overlap in multiple layers when viewed from the top. As a result, there is a high possibility that cracks or splits will occur in the substrate 2 due to stress from the outside. Due to this tendency, there is concern that external stress may cause cracks or splits in the base plate 2 from the portion where the gaps of the internal conductors overlap when viewed from above. In the example shown in FIG. 8(a), the third gap 5cg is located overlapping the first conductor layer 5a and the second conductor layer 5b, and the first gap 5ag and the second gap 5bg are positioned over the third conductor. It is located overlapping the layers. As a result, the overlapping area of the third gap 5cg and the second gap 5bg between the first conductor layer 5a and the second conductor layer 5b due to external stress can be reduced. It is possible to reduce the possibility that cracks or cracks will occur in the substrate 2 from the overlapped portion.

第２の実施形態の電子素子実装用基板１の製造方法は、第４絶縁層２ｄと第３導体層２ｃを第１の実施形態の（１）、（２）の工程で作成し、(３)工程以降は第１の実施形態と同様に作成することができる。 In the method of manufacturing the electronic device mounting substrate 1 of the second embodiment, the fourth insulating layer 2d and the third conductor layer 2c are formed in the steps (1) and (2) of the first embodiment, and (3 ) and subsequent steps can be produced in the same manner as in the first embodiment.

（第３の実施形態）
次に、本発明の第３の実施形態による電子素子実装用基板１について、図９～図１０を参照しつつ説明する。なお、図９～図１０は本実施形態における電子素子実装用基板１および電子装置の形状を示す。本実施形態における電子素子実装用基板１において、第１の実施形態の電子素子実装用基板１と異なる点は、基体２が貫通孔を有する（電子素子１０の実装方法が異なる）点、基体２が側面の一部において切欠き７およびメタライズ層７ａを有している点である。 (Third embodiment)
Next, an electronic device mounting board 1 according to a third embodiment of the present invention will be described with reference to FIGS. 9 to 10. FIG. 9 and 10 show the shapes of the electronic element mounting board 1 and the electronic device in this embodiment. The electronic device mounting substrate 1 of this embodiment differs from the electronic device mounting substrate 1 of the first embodiment in that the base 2 has through holes (the mounting method of the electronic device 10 is different); has a notch 7 and a metallized layer 7a on a part of the side surface.

図９に示す例では、電子素子実装用基板１は上面視において電子素子１０と重なる位置に貫通孔を有している。また、電子装置２１に実装された電子素子１０は上面視において基体２に設けられた貫通孔の中に位置するように設けられている。このような構成により、例えば電子素子１０が撮像素子である場合において、より電子モジュール３１の低背化が可能となる。また、電子素子実装用基板１は表面に電子部品２２を有しているが、図９に示す例構造においてはより多くの電子部品２２を実装することが可能となるため、電子装置の更なる小型化が可能となる。 In the example shown in FIG. 9, the electronic element mounting substrate 1 has a through-hole at a position overlapping the electronic element 10 when viewed from above. Further, the electronic element 10 mounted on the electronic device 21 is provided so as to be located inside the through hole provided in the base 2 when viewed from above. With such a configuration, for example, when the electronic device 10 is an imaging device, it is possible to further reduce the height of the electronic module 31 . Further, the electronic element mounting board 1 has electronic components 22 on its surface, but in the example structure shown in FIG. Miniaturization is possible.

電子部品２２は例えばチップコンデンサ、インダクタ、抵抗等の受動部品、またはOIS（Optical Image Stabilization）、信号処理回路、ジャイロセンサー等の能動部品などである。これら電子部品２２はハンダ、導電性樹脂等によって接合材により、基体２に設けられたパッドに接続されている。なお、これら電子部品２２は基体２に設けられた内部導体等を介して電子素子１０と接続していても構わない。 The electronic components 22 are, for example, passive components such as chip capacitors, inductors, and resistors, or active components such as OIS (Optical Image Stabilization), signal processing circuits, and gyro sensors. These electronic components 22 are connected to pads provided on the base 2 by a bonding material such as solder or conductive resin. Note that these electronic components 22 may be connected to the electronic element 10 via internal conductors or the like provided on the base 2 .

なお図９に示す例の様な実装形態の場合、電子素子１０は金バンプまたは半田ボール等の電子素子接続材１３で電子素子実装用基板１に接続された後、封止材で接続を強化し、さらに封止されていてもよい。また、例えばＡＣＦ（Anisotropic Conductive Film）等の電子素子接続材１３で接続されていてもよい。 In the case of the mounting form shown in FIG. 9, the electronic element 10 is connected to the electronic element mounting substrate 1 by means of electronic element connecting members 13 such as gold bumps or solder balls, and then the connection is strengthened by the sealing material. and may be further sealed. Alternatively, they may be connected by an electronic element connecting material 13 such as ACF (Anisotropic Conductive Film).

図９に示す例では、電子素子実装用基板１は、第１絶縁層２ａの側壁から第２絶縁層２ｂの側壁にかけて、切欠き７を有しており、切欠き７にメタライズ層７ａが設けられている。このように、電子素子実装用基板１は切欠き７を有し、切欠き７にメタライズ層７ａを有していることで、切欠き７および切欠き７に設けられたメタライズ層７ａを側面端子として使用することができる。よって、電子素子実装用基板１を用いた電子モジュール３１において、筐体３２と電子素子実装用基板１とを電気的に接続させることが可能となる。 In the example shown in FIG. 9, the electronic device mounting substrate 1 has a notch 7 extending from the sidewall of the first insulating layer 2a to the sidewall of the second insulating layer 2b, and the notch 7 is provided with the metallized layer 7a. It is As described above, the electronic device mounting board 1 has the notch 7 and the metallized layer 7a in the notch 7, so that the notch 7 and the metallized layer 7a provided in the notch 7 can be used as side terminals. can be used as Therefore, in the electronic module 31 using the electronic element mounting board 1, the housing 32 and the electronic element mounting board 1 can be electrically connected.

また、電子素子実装用基板１に切欠き７を有していることで、筐体３２の脚部等を切欠き７に嵌め込むことができる。また切欠き７にメタライズ層７ａを設けることで、筐体３２と電子素子実装用基板１とをハンダ等の金属材で固定することができ、より接続強度を向上させることが可能となる。また、切欠き７または／およびメタライズ層７ａはその他の絶縁層２ｅにも設けられていても良く、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃまたは／およびその他の絶縁層２ｅに設けられた切欠き７の大きさはそれぞれの層で異ならせていてもよい。 In addition, since the electronic element mounting substrate 1 has the notch 7 , the legs of the housing 32 can be fitted into the notch 7 . Further, by providing the metallized layer 7a in the notch 7, the housing 32 and the electronic element mounting board 1 can be fixed with a metal material such as solder, and the connection strength can be further improved. Also, the cutout 7 and/or the metallized layer 7a may be provided on other insulating layers 2e, and the first insulating layer 2a, the second insulating layer 2b, the third insulating layer 2c and/or the other insulating layers may be provided. The size of the notch 7 provided in 2e may be different for each layer.

メタライズ層７ａは第１導体層５ａ、第２導体層５ｂまたは、第３導体層５ｃと類似の材料から成っていてもよい。ここで、メタライズ層７ａと第１導体層５ａ、第２導体層５ｂまたは／および第３導体層５ｃとは同じ材料から成っていてもよいし、異なる材料から成っていてもよい。メタライズ層７ａと第１導体層５ａ、第２導体層５ｂまたは／および第３導体層５ｃとは同じ材料から成っていることで、物性及び特性を等しくすることが可能となるため、製造時における仕様を揃えることが可能となる。また、メタライズ層７ａと第１導体層５ａ、第２導体層５ｂまたは／および第３導体層５ｃとは異なる材料から成っているとき、物性及び特性を等しくすることが可能となるため、より製造しやすい仕様を有する材料を適宜選択することが可能となる。とくにメタライズ層７ａは側面に設けられる仕様の為、粘度が高い材料等を選択することもメタライズ層７ａと第１導体層５ａ、第２導体層５ｂまたは／および第３導体層５ｃとの材料を異ならせることでできる。 The metallization layer 7a may consist of a material similar to that of the first conductor layer 5a, the second conductor layer 5b or the third conductor layer 5c. Here, the metallized layer 7a and the first conductor layer 5a, the second conductor layer 5b and/or the third conductor layer 5c may be made of the same material, or may be made of different materials. Since the metallized layer 7a and the first conductor layer 5a, the second conductor layer 5b and/or the third conductor layer 5c are made of the same material, the physical properties and characteristics can be made equal. It is possible to align the specifications. In addition, when the metallized layer 7a and the first conductor layer 5a, the second conductor layer 5b and/or the third conductor layer 5c are made of different materials, it becomes possible to equalize the physical properties and characteristics, thus making it easier to manufacture. It is possible to appropriately select a material having specifications that are easy to manufacture. In particular, since the metallized layer 7a is designed to be provided on the side surface, it is possible to select a material with high viscosity, etc., depending on the material of the metallized layer 7a and the first conductor layer 5a, the second conductor layer 5b and/or the third conductor layer 5c. You can do it by making it different.

図９および図１０に示す例の様な電子素子実装用基板１の製造方法は、第１実施形態に記載の工程に加えて、第１導体層５ａ、第２導体層５ｂまたは第３導体層５ｃを、第１絶縁層２ａ、第２絶縁層２ｂ、第３絶縁層２ｃの側壁にかけて設ける工程と、切欠き７側に伸ばした第１導体５ａまたは第２導体５ｂの上面から、その他の位置に設けられた第１導体５ａまたは第２導体５ｂの上面にかけて、切欠き７の側面をメタライズ膜７ａで覆う工程を備えている。このような工程を得る事で、図９～図１０に示す例の様な電子素子実装用基板１を作製することが可能となる。 9 and 10, in addition to the steps described in the first embodiment, a first conductor layer 5a, a second conductor layer 5b or a third conductor layer 5c is provided over the sidewalls of the first insulating layer 2a, the second insulating layer 2b, and the third insulating layer 2c; A step of covering the side surface of the notch 7 with the metallized film 7a over the upper surface of the first conductor 5a or the second conductor 5b provided in the . By obtaining such a process, it becomes possible to manufacture the electronic element mounting substrate 1 as shown in FIGS.

切欠き７の側面をメタライズ膜７ａで覆う工程として、例えばスクリーン印刷法等を用いて、切欠き７の側面よりも内側に印刷が位置するように作成した製版をもちいて切欠き７の上面からメタライズ膜７ａとなる金属ペーストを塗布する方法等が挙げられる。 As a step of covering the side surface of the notch 7 with the metallized film 7a, for example, by using a screen printing method or the like, a printing plate is prepared so that the printing is positioned inside the side surface of the notch 7, and from the upper surface of the notch 7 A method of applying a metal paste to be the metallized film 7a can be used.

なお、本発明は上述の実施形態の例に限定されるものではなく、本発明に係る各実施形態、その内容に矛盾をきたさない限り、すべてにおいて組合せ可能である。数値などの種々の変形は可能である。また、例えば、図４～図６に示す例では、導体層の形状の一例を説明したが、導体層は上記以外の他の形状、例えば１か所だけでなく数カ所の間を配置させることができる。また、隙間を介して対向する導体層の形状や、上下層の導体層間の形状を変えることも可能である。それらの組み合わせで多種多様な間の形状が実現可能であることで、クラックや割れの発生を低減することが可能となる。また、本実施形態における電極パッド３、部品パッド５の配置、数、形状および電子素子の実装方法などは指定されない。 It should be noted that the present invention is not limited to the examples of the embodiments described above, and all of the embodiments according to the present invention can be combined as long as there is no contradiction. Various modifications such as numerical values are possible. Further, for example, in the examples shown in FIGS. 4 to 6, an example of the shape of the conductor layer has been described, but the conductor layer may be arranged in other shapes other than the above, for example, not only in one place but also in several places. can. It is also possible to change the shape of the conductor layers facing each other with a gap and the shape of the upper and lower conductor layers. It is possible to reduce the occurrence of cracks and cracks by realizing a wide variety of shapes by combining them. Also, the arrangement, number and shape of the electrode pads 3 and the component pads 5, the mounting method of the electronic elements, and the like in this embodiment are not specified.

１・・・・電子素子実装用基板
２・・・・基体
２ａ・・・第１絶縁層
２ｂ・・・第２絶縁層
２ｃ・・・第３絶縁層
２ｄ・・・第４絶縁層
２ｅ・・・その他の絶縁層
３・・・・電極パッド
５ａ・・・第１導体層
５ａａ・・第１導体
５ａｂ・・第２導体
５ａｇ・・第１の間
５ｂ・・・第２導体層
５ｂａ・・第３導体
５ｂｂ・・第４導体
５ｂｇ・・第２の間
５ｃ・・・第３導体層
５ｃａ・・第５導体
５ｃｂ・・第６導体
５ｃｇ・・第３の間
７・・・・切欠き
７ａ・・・メタライズ層
１０・・・電子素子
１２・・・蓋体
１３・・・電子素子接続部材
１４・・・蓋体接合材
２１・・・電子装置
２２・・・電子部品
３１・・・電子モジュール
３２・・・筐体 Reference Signs List 1 Electronic device mounting board 2 Substrate 2a First insulating layer 2b Second insulating layer 2c Third insulating layer 2d Fourth insulating layer 2e Other insulating layers 3 Electrode pad 5a First conductor layer 5aa First conductor 5ab Second conductor 5ag First interval 5b Second conductor layer 5ba Third conductor 5bb Fourth conductor 5bg Second interval 5c Third conductor layer 5ca Fifth conductor 5cb Sixth conductor 5cg Third interval 7 Off Notch 7a Metallized layer 10 Electronic element 12 Lid 13 Electronic element connecting member 14 Lid bonding material 21 Electronic device 22 Electronic component 31・Electronic module 32 ... housing

Claims (8)

上方または下方に電子素子が位置する第１絶縁層と、
前記第１絶縁層の下面に位置する第２絶縁層と、
前記第２絶縁層の下面に位置する第３絶縁層と、
前記第１絶縁層と、前記第２絶縁層との間に位置した、第１の間を有する第１導体層と、
前記第２絶縁層と、前記第３絶縁層との間に位置した、第２の間を有する第２導体層と、を備えており、
平面視において、前記第１の間は前記第２導体層と重なって位置しており、前記第２の間は、前記第１導体層と重なって位置しており、かつ前記第１の間と前記第２の間とは離れており、
前記第１導体層の前記第１の間は、前記第１絶縁層または前記第２絶縁層の少なくとも一部が位置しており、
前記第２導体層の前記第２の間は、前記第２絶縁層または前記第３絶縁層の少なくとも一部が位置しており、
積層方向の断面視において、前記第１導体層の端部および前記第２導体層の端部は、それぞれ他の箇所よりも積層方向における厚みが小さいことを特徴とする電子素子実装用基板。 a first insulating layer above or below which an electronic element is positioned;
a second insulating layer located on the lower surface of the first insulating layer;
a third insulating layer located on the lower surface of the second insulating layer;
a first conductor layer having a first gap positioned between the first insulating layer and the second insulating layer;
a second conductor layer positioned between the second insulating layer and the third insulating layer and having a second gap;
In plan view, the first space overlaps with the second conductor layer, the second space overlaps with the first conductor layer, and overlaps with the first space. separated from the second space,
at least a portion of the first insulating layer or the second insulating layer is positioned between the first spaces of the first conductor layer;
at least part of the second insulating layer or the third insulating layer is positioned between the second spaces of the second conductor layer;
1. An electronic element mounting board, wherein, in a cross-sectional view in a stacking direction, an end portion of the first conductor layer and an end portion of the second conductor layer have a smaller thickness in the stacking direction than other portions. 前記第１導体層および前記第２導体層は、グランドまたは電源と接続されることを特徴とする請求項１に記載の電子素子実装用基板。 2. The substrate for mounting an electronic element according to claim 1, wherein the first conductor layer and the second conductor layer are connected to a ground or a power source. 平面視において、前記第１導体層および前記第２導体層は、外縁が直線的に蛇行した形状またはウェーブ形状を有していることを特徴とする請求項１に記載の電子素子実装用基板。 2. The substrate for mounting an electronic element according to claim 1, wherein the first conductor layer and the second conductor layer have a linearly meandering outer edge or a wavy shape in plan view. 前記第３絶縁層の下面に位置した第４絶縁層と、
前記第３絶縁層と前記第４絶縁層との間に位置した、第３の間を有する第３導体層とをさらに有しており、
平面視において、前記第３の間は、前記１導体層および前記第２導体層と重なって位置しているとともに、
前記第１の間および前記第２の間は、前記第３導体層と重なって位置していることを特徴とする請求項１～３のいずれか１つに記載の電子素子実装用基板。 a fourth insulating layer located on the lower surface of the third insulating layer;
a third conductor layer having a third gap between the third insulating layer and the fourth insulating layer;
In a plan view, the third space overlaps the first conductor layer and the second conductor layer, and
4. The electronic element mounting board according to claim 1, wherein the first space and the second space are positioned so as to overlap with the third conductor layer. 平面視において、前記第１絶縁層、前記第２絶縁層および前記第３絶縁層は中央部に貫通孔を有することを特徴とする請求項１～３のいずれか１つに記載の電子素子実装用基板。 4. The electronic device mounting method according to claim 1, wherein the first insulating layer, the second insulating layer, and the third insulating layer each have a through hole in the center when viewed from above. substrate. 平面視において、前記第１絶縁層、前記第２絶縁層、前記第３絶縁層および前記第４絶縁層は中央部に貫通孔を有することを特徴とする請求項４に記載の電子素子実装用基板。 5. The electronic element mounting device according to claim 4, wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each have a through hole in a central portion thereof in a plan view. substrate. 請求項１～６のいずれか１つに記載の電子素子実装用基板と、
前記電子素子実装用基板に実装された電子素子と、を備えたことを特徴とする電子装置。 An electronic device mounting substrate according to any one of claims 1 to 6;
and an electronic device mounted on the electronic device mounting board. 請求項７に記載の電子装置と、
前記電子装置の上面に位置した筐体とを備えたことを特徴とする電子モジュール。 an electronic device according to claim 7;
An electronic module, comprising: a housing located on the upper surface of the electronic device.
JP2023080184A 2017-10-26 2023-05-15 Substrate for mounting electronic element, electronic device, and electronic module Pending JP2023091083A (en)

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