JP2022534538A - ディープアイソレーション構造体を備えた3次元メモリデバイス - Google Patents
ディープアイソレーション構造体を備えた3次元メモリデバイス Download PDFInfo
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- JP2022534538A JP2022534538A JP2021571423A JP2021571423A JP2022534538A JP 2022534538 A JP2022534538 A JP 2022534538A JP 2021571423 A JP2021571423 A JP 2021571423A JP 2021571423 A JP2021571423 A JP 2021571423A JP 2022534538 A JP2022534538 A JP 2022534538A
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Abstract
Description
101 メモリ平面
103 メモリブロック
105 周辺部領域
108 領域
200 メモリアレイ構造体
210 階段領域
211 チャネル構造体領域
212 メモリストリング
214 接触構造体
216 スリット構造体
216-1 スリット構造体
216-2 スリット構造体
218 メモリフィンガー
220 上部選択ゲートカット
300 例示的な方法
330 基板
331 絶縁フィルム
332 下側選択ゲート(LSG)
333、333-1、333-2、333-3 制御ゲート
334 上部選択ゲート(TSG)
335 フィルムスタック
336 チャネルホール部
337 メモリフィルム
338 チャネル層
339 コア充填フィルム
340、340-1、340-2、340-3 メモリセル
341 ビットライン(BL)
343 金属相互接続ライン
344 ソースライン領域
400 周辺回路、CMOSウエハ
430 第1の基板
430-1 第1の側
430-2 第2の側
450A、450B 周辺デバイス
451 第1のウェル
452 シャロートレンチアイソレーション(STI)
454 ウェル
455 ディープウェル
456 ゲートスタック
457 第3のウェル
458 ゲートスペーサー
460 ソース/ドレイン
462 周辺相互接続層
464 接触構造体
466、466-2 導電性ライン
468 絶縁層
470 金属レベル
470-1 底部金属レベル、導電性レベル
470-2 上側金属レベル、導電性レベル
471 接触部
472 基板接触部
473 ディープウェル接触部
500 メモリアレイ
530 第2の基板
540 メモリセル
562 アレイ相互接続層
564 接触構造体
566 導電性ライン
568 絶縁層
572 基板接触部
574 導体層
576 第1の誘電体層
578 交互の導体/誘電体スタック
580 エピタキシャル層、エピタキシャルプラグ
582 半導体層
584 ビットライン接触部
586 相互接続VIA
600 3Dメモリデバイス
688 結合界面
690 ボンディング層
700 3Dメモリデバイス
701 領域
792 誘電体層
800 3Dメモリデバイス
894 ディープアイソレーショントレンチ
896 トレンチ
900 3Dメモリデバイス
994 ディープアイソレーション構造体
D 深さ
L 長さ
T、t 厚さ
W1 上部幅
W2 底部幅
α 角度
Claims (20)
- 3次元メモリデバイスを形成するための方法であって、
第1および第2の周辺デバイス、第1の相互接続層、および、前記第1の周辺デバイスと前記第2の周辺デバイスとの間のシャロートレンチアイソレーション(STI)構造体を含む周辺回路を、第1の基板の第1の側に形成するステップと、
複数のメモリセルおよび第2の相互接続層を含むメモリアレイを第2の基板の上に形成するステップと、
前記第1および第2の相互接続層を結合するステップと、
前記第1の基板を通してアイソレーショントレンチを形成し、前記STI構造体の一部分を露出させるステップであって、前記アイソレーショントレンチが、前記第1の側の反対側にある前記第1の基板の第2の側を通して形成される、ステップと、
アイソレーション材料を配設し、前記アイソレーショントレンチの中にアイソレーション構造体を形成するステップと
前記第1の基板の前記第2の側に配設されている前記アイソレーション材料の部分を除去するために平坦化プロセスを実施するステップと
を含む、方法。 - 前記第1および第2の相互接続層を結合するステップの後に、前記第2の側を通して前記第1の基板を薄くするステップをさらに含む、請求項1に記載の方法。
- 前記第1の基板を薄くするステップは、前記第1の基板の前記第2の側に前記ディープウェルを露出させるステップを含む、請求項1に記載の方法。
- 前記アイソレーション材料を配設する前に、前記アイソレーショントレンチの中にライナー層を配設するステップをさらに含む、請求項1に記載の方法。
- 前記第1の基板の前記第2の側に誘電体層を配設するステップをさらに含む、請求項1に記載の方法。
- 結合する前記ステップは、直接的なボンディングを含む、請求項1に記載の方法。
- 前記第1の周辺デバイスに隣接して別のSTI構造体を形成するステップと、前記第1の基板を通して別のディープアイソレーショントレンチを形成するステップと、前記別のSTI構造体を露出させるステップとをさらに含む、請求項1に記載の方法。
- 前記別のディープアイソレーショントレンチの中に前記アイソレーション材料を配設するステップをさらに含む、請求項7に記載の方法。
- 前記アイソレーション材料を配設するステップは、酸化ケイ素材料を配設するステップを含む、請求項1に記載の方法。
- 前記第1および第2の相互接続層を結合するステップは、結合界面における誘電体-誘電体結合および金属-金属結合を含む、請求項1に記載の方法。
- 3次元メモリデバイスを形成するための方法であって、
複数の周辺デバイスおよび第1の相互接続層を含む周辺回路を第1の基板の第1の側に形成するステップと、
前記第1の基板の中に複数のシャロートレンチアイソレーション(STI)構造体を形成するステップであって、前記複数のSTI構造体のそれぞれのSTI構造体が、前記複数の周辺デバイスの隣接する周辺デバイス同士の間に形成される、ステップと、
複数のメモリセルおよび第2の相互接続層を含むメモリアレイを第2の基板の上に形成するステップと、
前記第1および第2の相互接続層を結合するステップであって、前記複数の周辺デバイスのうちの少なくとも1つの周辺デバイスが、前記複数のメモリセルのうちの少なくとも1つのメモリセルに電気的に連結されるようになっている、ステップと、
前記第1の基板の第2の側を通して前記第1の基板を薄くするステップであって、前記第2の側は、前記第1の側の反対側にある、ステップと、
前記第1の基板を通して複数のアイソレーショントレンチを形成し、前記複数のSTI構造体のSTI構造体の一部分を露出させるステップであって、前記複数のアイソレーショントレンチは、前記第1の基板の前記第2の側を通して形成される、ステップと、
前記複数のアイソレーショントレンチの中にアイソレーション材料を配設するステップと、
前記第1の基板の前記第2の側に配設されている前記アイソレーション材料の部分を除去するために平坦化プロセスを実施するステップと
を含む、方法。 - 結合する前記ステップは、直接的なボンディングを含む、請求項11に記載の方法。
- 前記第1の基板の前記第2の側に誘電体層を配設するステップであって、前記複数のアイソレーショントレンチは、前記誘電体層を通って延在する、ステップをさらに含む、請求項11に記載の方法。
- 前記アイソレーション材料を配設する前に、前記アイソレーショントレンチの中にライナー層を配設するステップをさらに含む、請求項11に記載の方法。
- 前記アイソレーション材料を配設するステップは、酸化ケイ素材料を配設するステップを含む、請求項11に記載の方法。
- 3次元メモリデバイスであって、前記3次元メモリデバイスは、
周辺回路ウエハと、
メモリアレイウエハと
を含み、
前記周辺回路ウエハは、
第1の基板と、
前記第1の基板の第1の側に形成された複数の周辺デバイスおよび第1の相互接続層と、
前記第1の基板の中の複数のシャロートレンチアイソレーション(STI)構造体であって、少なくとも1つのSTI構造体は、前記複数の周辺デバイスの隣接する周辺デバイス同士の間に形成されている、複数のシャロートレンチアイソレーション(STI)構造体と、
前記第1の側の反対側にある前記第1の基板の第2の側に形成された複数のディープアイソレーション構造体であって、前記複数のディープアイソレーション構造体の少なくとも1つのディープアイソレーション構造体は、前記少なくとも1つのSTI構造体と物理的な接触をしている、複数のディープアイソレーション構造体と
を含み、
前記メモリアレイウエハは、
複数のメモリセルであって、前記複数の周辺デバイスのうちの少なくとも1つの周辺デバイスは、前記複数のメモリセルのうちの少なくとも1つのメモリセルに電気的に連結されている、複数のメモリセルと、
前記第1の相互接続層と物理的な接触をしている第2の相互接続層と
を含む、3次元メモリデバイス。 - 前記少なくとも1つのディープアイソレーション構造体は、ライナー層およびアイソレーション材料を含み、前記ライナー層は、前記アイソレーション材料と前記第1の基板との間にある、請求項16に記載の3次元メモリデバイス。
- 前記物理的な接触は、前記第1の相互接続層と前記第2の相互接続層との間に形成された化学結合を含む、請求項16に記載の3次元メモリデバイス。
- 前記少なくとも1つのディープアイソレーション構造体は、酸化ケイ素を含む、請求項16に記載の3次元メモリデバイス。
- 前記少なくとも1つのディープアイソレーション構造体の幅は、約0.2μmである、請求項16に記載の3次元メモリデバイス。
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CN110506334A (zh) | 2019-11-26 |
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