JP2022529165A - 3次元相変化メモリを伴う3次元メモリデバイス - Google Patents
3次元相変化メモリを伴う3次元メモリデバイス Download PDFInfo
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- JP2022529165A JP2022529165A JP2021561775A JP2021561775A JP2022529165A JP 2022529165 A JP2022529165 A JP 2022529165A JP 2021561775 A JP2021561775 A JP 2021561775A JP 2021561775 A JP2021561775 A JP 2021561775A JP 2022529165 A JP2022529165 A JP 2022529165A
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Abstract
Description
本出願は、2019年4月30日に出願された「THREE-DIMENSIONAL MEMORY DEVICE WITH EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY」という標題の国際出願第PCT/CN2019/085237号の優先権の利益を主張し、その文献は、その全体が参照により本明細書に組み込まれている。
102 第1の半導体構造体
104 第2の半導体構造体
106 ボンディングインターフェース
200 半導体構造体
202 ワードラインドライバー
204 ページバッファー
206 3D PCM
300 3Dメモリデバイス
302 第1の半導体構造体
304 第2の半導体構造体
306 ボンディングインターフェース
308 基板
310 デバイス層
312 高速ロジックトランジスター
314 センシング&コントローラー回路
316 トランジスター
318 3D XPointメモリセル
322 相互接続層
324 ボンディング層
326 ボンディングコンタクト
328 ボンディング層
330 ボンディングコンタクト
332 相互接続層
333 メモリスタック
334 導体層
336 誘電体層
338 3D NANDメモリストリング
340 メモリフィルム
342 半導体チャネル
344 プラグ
346 プラグ
348 半導体層
350 パッドアウト相互接続層
352 接触パッド
354 コンタクト
360 ワードライン
362 ビットライン
364 メモリエレメント
400 3Dメモリデバイス
402 第1の半導体構造体
404 第2の半導体構造体
406 ボンディングインターフェース
408 基板
410 メモリスタック
412 導体層
414 誘電体層
416 3D NANDメモリストリング
418 メモリフィルム
420 半導体チャネル層
422 プラグ
424 プラグ
426 相互接続層
428 ボンディング層
430 ボンディングコンタクト
432 ボンディング層
434 ボンディングコンタクト
436 相互接続層
438 デバイス層
440 半導体層
442、444 周辺回路
446 トランジスター
448 3D XPointメモリセル
452 パッドアウト相互接続層
454 接触パッド
456 コンタクト
460 ワードライン
462 ビットライン
464 メモリエレメント
502 シリコン基板
504 トランジスター
506 3D XPointメモリセル
507 ワードライン
508 ビットライン
509 メモリエレメント
510 デバイス層
512 相互接続層
514 ボンディング層
516 ボンディングコンタクト
602 シリコン基板
604 メモリスタック
606 導体層
608 誘電体層
610 3D NANDメモリストリング
612 プラグ
614 メモリフィルム
616 半導体層
618 プラグ
620 相互接続層
622 ボンディング層
624 ボンディングコンタクト
702 ボンディングインターフェース
704 半導体層
706 パッドアウト相互接続層
708 パッドコンタクト
710 コンタクト
800 3Dメモリデバイス
802 ホスト
804 I/O回路
806 3D PCM
808 3D NANDメモリ
Claims (26)
- 3次元(3D)メモリデバイスであって、
周辺回路、3D相変化メモリ(PCM)セルのアレイ、および、複数の第1のボンディングコンタクトを含む第1のボンディング層を含む第1の半導体構造体と、
3D NANDメモリストリングのアレイ、および、複数の第2のボンディングコンタクトを含む第2のボンディング層を含む第2の半導体構造体と、
前記第1のボンディング層と前記第2のボンディング層との間のボンディングインターフェースであって、前記第1のボンディングコンタクトは前記ボンディングインターフェースにおいて前記第2のボンディングコンタクトと接触している、ボンディングインターフェースと
を含む、3Dメモリデバイス。 - 前記第1の半導体構造体は、
基板と、
前記基板の上の前記周辺回路と、
前記周辺回路の上方の前記3D PCMセルのアレイと、
前記3D PCMセルのアレイの上方の前記第1のボンディング層と
を含む、請求項1に記載の3Dメモリデバイス。 - 前記第2の半導体構造体は、
前記第1のボンディング層の上方の前記第2のボンディング層と、
前記第2のボンディング層の上方のメモリスタックと、
前記メモリスタックを通って垂直方向に延在する前記3D NANDメモリストリングのアレイと、
前記3D NANDメモリストリングのアレイの上方にあり、前記3D NANDメモリストリングのアレイと接触している半導体層と
を含む、請求項2に記載の3Dメモリデバイス。 - 前記半導体層の上方にパッドアウト相互接続層をさらに含む、請求項3に記載の3Dメモリデバイス。
- 前記半導体層は、ポリシリコンを含む、請求項3または4に記載の3Dメモリデバイス。
- 前記半導体層は、単結晶シリコンを含む、請求項3または4に記載の3Dメモリデバイス。
- 前記第2の半導体構造体は、
基板と、
前記基板の上方のメモリスタックと、
前記メモリスタックを通って垂直方向に延在する前記3D NANDメモリストリングのアレイと、
前記メモリスタックおよび前記3D NANDメモリストリングのアレイの上方の前記第2のボンディング層と
を含む、請求項1に記載の3Dメモリデバイス。 - 前記第1の半導体構造体は、
前記第2のボンディング層の上方の前記第1のボンディング層と、
前記第1のボンディング層の上方の前記3D PCMセルのアレイと、
前記3D PCMセルのアレイの上方の前記周辺回路と、
前記周辺回路の上方にあり、前記周辺回路と接触している半導体層と
を含む、請求項7に記載の3Dメモリデバイス。 - 前記半導体層の上方にパッドアウト相互接続層をさらに含む、請求項8に記載の3Dメモリデバイス。
- 前記周辺回路は、前記NANDメモリストリングのアレイの周辺回路と、前記3D PCMセルのアレイの周辺回路とを含む、請求項1に記載の3Dメモリデバイス。
- 各々の3D PCMセルは3D XPointメモリセルを含む、請求項1から10のいずれか一項に記載の3Dメモリデバイス。
- 前記第1の半導体構造体は、垂直方向に前記第1のボンディング層と前記3D PCMセルのアレイとの間に第1の相互接続層を含み、前記第2の半導体構造体は、垂直方向に前記第2のボンディング層と前記3D NANDメモリストリングのアレイとの間に第2の相互接続層を含む、請求項1から11のいずれか一項に記載の3Dメモリデバイス。
- 前記3D PCMセルのアレイは、前記第1および第2の相互接続層ならびに前記第1および第2のボンディングコンタクトを通して、前記3D NANDメモリストリングのアレイに電気的に接続されている、請求項12に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイスを形成するための方法であって、
第1の半導体構造体を形成するステップであって、前記第1の半導体構造体は、周辺回路、3D相変化メモリ(PCM)セルのアレイ、および、複数の第1のボンディングコンタクトを含む第1のボンディング層を含む、ステップと、
第2の半導体構造体を形成するステップであって、前記第2の半導体構造体は、3D NANDメモリストリングのアレイ、および、複数の第2のボンディングコンタクトを含む第2のボンディング層を含む、ステップと、
前記第1のボンディングコンタクトがボンディングインターフェースにおいて前記第2のボンディングコンタクトと接触するように、前記第1の半導体構造体および前記第2の半導体構造体を向かい合った様式で接合するステップと
を含む、方法。 - 前記第1の半導体構造体を形成するステップは、
第1の基板の上に前記周辺回路を形成するステップと、
前記周辺回路の上方に前記3D PCMセルのアレイを形成するステップと、
前記3D PCMセルのアレイの上方に第1の相互接続層を形成するステップと、
前記第1の相互接続層の上方に前記第1のボンディング層を形成するステップと
を含む、請求項14に記載の方法。 - 前記3D PCMセルのアレイを形成するステップは、3D XPointメモリセルのアレイを形成するステップを含む、請求項15に記載の方法。
- 前記第2の半導体構造体を形成するステップは、
第2の基板の上方にメモリスタックを形成するステップと、
前記メモリスタックを通って垂直方向に延在する前記3D NANDメモリストリングのアレイを形成するステップと、
前記3D NANDメモリストリングのアレイの上方に第2の相互接続層を形成するステップと、
前記第2の相互接続層の上方に前記第2のボンディング層を形成するステップと
を含む、請求項14から16のいずれか一項に記載の方法。 - 前記第2の半導体構造体は、前記接合するステップの後に、前記第1の半導体構造体の上方にある、請求項14から17のいずれか一項に記載の方法。
- 前記接合するステップの後に半導体層を形成するために前記第2の基板を薄くするステップと、
前記半導体層の上方にパッドアウト相互接続層を形成するステップと
をさらに含む、請求項18に記載の方法。 - 前記第1の半導体構造体は、前記接合するステップの後に、前記第2の半導体構造体の上方にある、請求項14から17のいずれか一項に記載の方法。
- 前記接合するステップの後に半導体層を形成するために前記第1の基板を薄くするステップと、
前記半導体層の上方にパッドアウト相互接続層を形成するステップと
をさらに含む、請求項20に記載の方法。 - 前記接合するステップは、ハイブリッドボンディングを含む、請求項14から21のいずれか一項に記載の方法。
- 入力/出力回路と、3次元(3D)相変化メモリ(PCM)セルのアレイと、3D NANDメモリストリングのアレイとを同じチップに含む3Dメモリデバイスを動作させるための方法であって、
前記入力/出力回路を通して、前記3D PCMセルのアレイへとデータを転送するステップと、
前記3D PCMセルのアレイにおいて前記データをバッファリングするステップと、
前記3D PCMセルのアレイから前記3D NANDメモリストリングのアレイにおいて前記データを記憶するステップと
を含む、方法。 - 複数のボンディングコンタクトを通して、前記3D NANDメモリストリングのアレイと前記3D PCMセルのアレイとの間で前記データを転送するステップをさらに含む、請求項23に記載の方法。
- 前記転送は、前記3Dメモリデバイスのパワーオンまたはパワーオフに応じて起動される、請求項23または24に記載の方法。
- 前記3D PCMセルのアレイは、3D XPointメモリセルのアレイを含む、請求項23から25のいずれか一項に記載の方法。
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