JP2022161707A - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP2022161707A JP2022161707A JP2021066721A JP2021066721A JP2022161707A JP 2022161707 A JP2022161707 A JP 2022161707A JP 2021066721 A JP2021066721 A JP 2021066721A JP 2021066721 A JP2021066721 A JP 2021066721A JP 2022161707 A JP2022161707 A JP 2022161707A
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- Japan
- Prior art keywords
- pixel
- light shielding
- shielding layer
- layer
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract
Description
図1は、本発明の一実施形態に係る表示装置100を構成する第1基板SUB1に設けられる各層の概要を示す断面図である。図1に示すように、第1基板SUB1には、第1トランジスタTr1、第2トランジスタTr2、データ信号線DL、第1配線W1、第2配線W2、接続電極ZTCO、画素電極PTCO、共通補助電極CMTL、及び共通電極CTCOが設けられる。なお、TCOという記号に特段の意味はないが、本明細書でITO、ZnO、IZO等の透明導電性酸化物又はこれに類するものを示すときの用いられることがある。第1トランジスタTr1は表示装置100の画素PXに含まれる素子であり、第2トランジスタTr2は駆動回路に含まれる素子である。なお、詳細は後述するが、駆動回路は画素PXを駆動する回路である。
第1トランジスタTr1は、半導体層OS、ゲート絶縁層GI1、及びゲート電極GL1を含む。半導体層OSは、例えば、酸化物半導体層である。また、半導体層OSは、多結晶シリコン層であってもよい。ゲート電極GL1は半導体層OSに対向する。ゲート絶縁層GI1は半導体層OSとゲート電極GL1との間に設けられる。図1は、ゲート電極GL1より基板SUB側に半導体層OSが設けられたトップゲート型トランジスタを例示するが、ゲート電極GL1と半導体層OSとの位置関係が逆であるボトムゲート型トランジスタであってもよい。
駆動回路は第2トランジスタTr2(pチャネル型トランジスタTr2-1及びnチャネル型トランジスタTr2-2)を含む。pチャネル型トランジスタTr2-1及びnチャネル型トランジスタTr2-2は、いずれもゲート電極GL2、ゲート絶縁層GI2、半導体層Sを含む。半導体層Sは、第1半導体領域S1、第2半導体領域S2、第3半導体領域S3を含む。半導体層Sにおいて、第1半導体領域S1はチャネルを形成する領域に該当し、第2半導体領域S2はソース領域及びドレイン領域を形成する領域に該当し、第3半導体領域S3は低濃度ドレイン(LDD)を形成する領域に該当する。ゲート電極GL2は第1半導体領域S1に重なる領域を含む。ゲート絶縁層GI2は半導体層Sとゲート電極GL2との間に設けられる。図1は、第2トランジスタTr2(pチャネル型トランジスタTr2-1及びnチャネル型トランジスタTr2-2)において、ゲート電極GL2が半導体層Sの第1基板SUB1側に設けられたボトムゲート型トランジスタを例示する。第2トランジスタTr2(pチャネル型トランジスタTr2-1及びnチャネル型トランジスタTr2-2)は、しかし、半導体層Sとゲート電極GL2との位置関係が逆であるトップゲート型トランジスタであってもよい。
図2は、画素PXの部分的な断面構造の一例を示す。画素PXは、第1基板SUB1、第2基板SUB2、及び第1基板SUB1と第2基板SUB2との間の液晶層LCを含む。図1を参照して説明したように、第1基板SUB1は、第1遮光層LS1、第1トランジスタTr1、接続電極ZTCO、画素電極PTCO、共通電極CTCOを含む。第2基板SUB2は、第2遮光層BM、カラーフィルタ層CF(第1カラーフィルタ層CF1、第2カラーフィルタ層CF2)、オーバーコート層OCを含む。前述のように、第2基板SUB2には、第1スペーサSP1に対応する位置に第2スペーサSP2が設けられる。第1基板SUB1と第2基板SUB2の間隔(セルギャップ)は第1スペーサSP1及び第2スペーサSP2によって一定の間隔となるように保持される。
表示装置100は、図2に示す要素を含む画素PXが複数配列された画素部102を有する。図3は、画素部102を第2基板SUB2側からみたときの平面模式構造を示す。図3は、画素PXが、第1副画素SPX1、第2副画素SPX2、第3副画素SPX3を含む態様を示す。例えば、第1副画素SPX1は青色に対応する副画素であり、第2副画素SPX2は緑色に対応する副画素であり、第3副画素SPX3は赤色に対応する副画素であるものとする。
以下に、画素PXを構成する各層の詳細なレイアウトを説明する。
図6は、第1遮光層LS1、LS2、LS3を示す。第1遮光層LS1、LS2、LS3は第1方向D1に延伸するパターンを有する。図3を参照して説明したように、第1遮光層LS1は、画素の配置に合わせてパターン幅が異なっている。すなわち、第1遮光層LS1は、第1方向D1に沿って幅が広い部分と、その幅が広い部分に比べて狭い部分を含む。例えば、図3に示すような第1副画素SPX1、第2副画素SPX2、及び第3副画素SPX3が第1方向D1に沿って周期的に配列される場合、第1遮光層LS1は周期的に変化するパターンを有する。第1遮光層LS2、LS3についても同様である。
図7に示すように、第1半導体層OSa、第2半導体層OSb、第3半導体層OScは、第2方向D2に延びる島状パターンを有する。第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScは、第1遮光層LS1の上層側に配置される。第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScは、第1遮光層LS1と一部が重なるように設けられる。
図8は走査信号線SCLを示す。走査信号線SCLは、第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScと交差するように第1方向D1に延伸する。走査信号線SCLが第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScと交差する部分はゲート電極(GL1)として機能する。走査信号線SCL(ゲート電極GL1)のパターンは第1遮光層LS1のパターンの内側に設けられる。
図9は、第1データ信号線DL1、第2データ信号線DL2、第3データ信号線DL3を示す。第1データ信号線DL1、第2データ信号線DL2、及び第3データ信号線DL3は、第2方向D2に延伸し、走査信号線SCLと交差するように設けられる。図9に示すように、開口部WCONは、第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScの島状パターンの一方の端部の付近において、第1データ信号線DL1、第2データ信号線DL2、第3データ信号線DL3と重なる領域に設けられる。第1半導体層OSaの主たる部分は第1データ信号線DL1と第2データ信号線DL2との間に配置され、第2方向D2に延びている。第1半導体層OSaの一方の端部は、第1データ信号線DL1及び第2データ信号線DL2に挟まれた部分から開口部WCONの方向に向かって屈曲するパターンを有する。第1データ信号線DL1は、開口部WCONと重なるように配設される。第1半導体層OSaは、開口部WCONにおいて第1データ信号線DL1と接続される。第2半導体層OSb及び第3半導体層OScについても同様である。
図10に示すように、開口部ZCONは第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScの島状パターンと重なるように設けられる。開口部WCONが第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScの一方の端部の側に設けられるのに対し、開口部ZCONは第1半導体層OSa、第2半導体層OSb、及び第3半導体層OScの他方の端部の側に設けられる。また、開口部ZCONは走査信号線SCLと重ならない位置に設けられる。
図11は、第1画素電極PTCO1、第2画素電極PTCO2、及び第3画素電極PTCO3を示す。第1画素電極PTCO1は開口部PCONにより第1接続電極ZTCO1と接続され、第2画素電極PTCO2は開口部PCONにより第2接続電極ZTCO2と接続され、第3画素電極PTCO3は開口部PCONにより第3接続電極ZTCO3と接続される。開口部PCONは第1接続電極ZTCO1、第2接続電極ZTCO2、第3接続電極ZTCO3のパターンの上端付近であって、走査信号線SCL(ゲート電極GL1)のパターンと重なる領域に設けられる。第1画素電極PTCO1は、第1データ信号線DL1と第2データ信号線DL2との間において、走査信号線SCL(ゲート電極GL1)、半導体層OS1a、及び第1接続電極ZTCO1と重なり、第2方向D2に延伸するように設けられる。第2画素電極PTCO2及び第3画素電極PTCO3についても同様である。
図12は、共通補助電極CMTLを示す。共通補助電極CMTLは、第1画素電極PTCO1、第2画素電極PTCO2、及び第3画素電極PTCO3の周囲を囲む格子状のパターンを有する。共通補助電極CMTLは、第1データ信号線DL1、第2データ信号線DL2、及び第3データ信号線DL3と重なるように第2方向D2に延伸するパターンと、開口部PCONと重なり第1方向D1に延伸するパターンとを含む。共通補助電極CMTLの第1方向D1に延伸するパターンの幅は、第1遮光層LS1の幅よりも狭い。共通補助電極CMTLは画素部102の全体に亘って設けられる。換言すると、共通補助電極CMTLは、第1画素電極PTCO1、第2画素電極PTCO2、及び第3画素電極PTCO3を露出する開口部を有する。
図13は、共通電極CTCOを示す。共通電極CTCOは、複数の画素に対して共通に設けられる。共通電極CTCOは、第1画素PX1、第2画素PX2、及び第3画素PX3の開口部に対応する領域にスリットSLが設けられる。スリットSLは湾曲した形状(縦に長いS字形状)を有しており、先端ほど延伸方向に対する幅が小さくなる形状を有している。以上のようにして、IPSモード(横電界モード)で液晶を駆動する画素PXが作製される。
第1基板SUB1及び第2基板SUB2として、ガラス基板、石英基板、およびサファイア基板など、透光性を有し、可撓性を有しない剛性基板を用いることができる。一方、第1基板SUB1及び第2基板SUB2が可撓性を有する必要がある場合は、基板材料としてポリイミド基板、アクリル基板、シロキサン基板、またはフッ素樹脂基板など、樹脂を含み、可撓性を有するフレキシブル基板を用いることができる。第1基板SUB1及び第2基板SUB2の耐熱性を向上させるために、上記の樹脂に不純物を導入してもよい。
図14は、本発明の一実施形態に係る表示装置100の構成を示す。表示装置100は、第1基板SUB1、第2基板SUB2、ドライバIC110、及びフレキシブルプリント回路基板112を含む。本実施形態で示すように、第1基板SUB1には第1遮光層LS1を含む画素PXが設けられ、第2基板SUB2には第2遮光層BM及びカラーフィルタ層CFが設けられる。第1基板SUB1と第2基板SUB2との間には図示されないシール材が設けられる。第1基板SUB1と第2基板SUB2とはシール材で張り合わされる。
Claims (10)
- 第1基板と、
前記第1基板に設けられた少なくとも1つの画素と、
前記第1基板に設けられた第1遮光層と、
第2基板と、
前記第2基板に設けられた第2遮光層と、
を有し、
前記第1遮光層は、第1方向に延伸し、
前記第2遮光層は、前記第1方向と交差する第2方向に延伸し、
前記少なくとも1つの画素は、前記第1遮光層と前記第2遮光層とにより開口部が画定される、
ことを特徴とする表示装置。 - 前記第1基板は、前記第1方向に延伸する走査信号線を含み、
前記第1遮光層が前記走査信号線と重なり、
前記第1遮光層の幅が前記走査信号線の幅よりも広い、
請求項1に記載の表示装置。 - 前記第1遮光層と前記走査信号線との間に少なくとも1層の絶縁層を有し、
前記第1遮光層が前記走査信号線より前記第1基板側に設けられている、
請求項2に記載の表示装置。 - 前記第1基板は、前記第2方向に延伸するデータ信号線を含み、
前記データ信号線が前記第2遮光層と重なる、
請求項1に記載の表示装置。 - 前記第1基板は、前記第1方向に延伸する走査信号線、及び前記第2方向に延伸するデータ信号線を含み、
前記第1遮光層が前記走査信号線と重なり、前記第1遮光層の幅が前記走査信号線の幅よりも広く、
前記第2遮光層が、前記走査信号線及び前記データ信号線、並びに前記第1遮光層と重なり、
前記第2遮光層の前記走査信号線と重なる領域の幅が、前記第1遮光層の幅よりも狭い、
請求項1に記載の表示装置。 - 前記少なくとも1つの画素が複数の画素からなり、
前記複数の画素が、前記第1方向に配列された第1画素、第2画素、及び第3画素を含み、
前記第1画素、前記第2画素、及び前記第3画素のそれぞれの開口率が異なるように、前記第1遮光層の幅が前記第1方向に沿って異なっている、
請求項1に記載の表示装置。 - 前記第1画素が青色に対応する画素であり、前記第2画素が緑色に対応する画素であり、前記第3画素が赤色に対応する画素であり、
前記第1遮光層は、前記第3画素に対応する領域の幅が、前記第1画素及び前記第2画素に対応する領域の幅よりも狭い、
請求項6に記載の表示装置。 - 前記第1基板と第2基板との間にスペーサを有し、
前記第1遮光層が前記スペーサと重なる領域を遮光する遮光パターンを含む、
請求項1に記載の表示装置。 - 前記第1遮光層が金属膜であり、前記第2遮光層が樹脂膜である、
請求項1に記載の表示装置。 - 前記第1基板が、前記データ信号線と重なる共通補助電極を有し、
前記少なくとも1つの画素は、前記第1遮光層と、前記第2遮光層に代えて前記共通補助電極とにより開口部が画定される、
請求項4に記載の表示装置。
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