JP2022021293A - Light emitting element and manufacturing method thereof - Google Patents

Light emitting element and manufacturing method thereof Download PDF

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JP2022021293A
JP2022021293A JP2021021054A JP2021021054A JP2022021293A JP 2022021293 A JP2022021293 A JP 2022021293A JP 2021021054 A JP2021021054 A JP 2021021054A JP 2021021054 A JP2021021054 A JP 2021021054A JP 2022021293 A JP2022021293 A JP 2022021293A
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JP7312953B2 (en
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泰伸 細川
Yasunobu Hosokawa
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Nichia Chemical Industries Ltd
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Abstract

To provide a light emitting element and a manufacturing method thereof that can improve the efficiency of light emission.SOLUTION: A first conductive semiconductor layer 10 is a nitride semiconductor layer containing Al and Ga, and has a first layer 11 and a second layer 12. The Al composition ratio of the first layer is lower than the Al composition ratio of the second layer. The first conductive semiconductor layer includes a first region a1 in which a second conductive semiconductor layer 15 and an active layer 14 are laminated, and a second region a2 exposed from the second conductive semiconductor layer and the active layer and connected to a first conductive member. The thickness of the first layer provided in the first region is thinner than the thickness of the first layer provided in the second region, or the first layer is not provided in the first region.SELECTED DRAWING: Figure 2

Description

本発明は、発光素子及び発光素子の製造方法に関する。 The present invention relates to a light emitting element and a method for manufacturing the light emitting element.

特許文献１には、発光素子の半導体積層体において、活性層上における光取り出し面側に設けられた半導体層の厚さを部分的に薄くして、光抽出効率を改善することが開示されている。 Patent Document 1 discloses that in a semiconductor laminate of a light emitting device, the thickness of the semiconductor layer provided on the light extraction surface side on the active layer is partially reduced to improve the light extraction efficiency. There is.

特開２０１３－０８４８７８号公報Japanese Unexamined Patent Publication No. 2013-08487

本発明の一実施形態は、光取り出し効率の向上が可能な発光素子及び発光素子の製造方法を提供することを目的とする。 It is an object of the present invention to provide a light emitting element and a method for manufacturing a light emitting element capable of improving the light extraction efficiency.

本発明の一態様によれば、発光素子は、第１導電型半導体層と、第２導電型半導体層と、前記第１導電型半導体層と前記第２導電型半導体層との間に設けられた活性層とを有する半導体積層体と、前記第１導電型半導体層と電気的に接続された第１導電部材と、前記第２導電型半導体層と電気的に接続された第２導電部材と、を備える。第１導電型半導体層は、ＡｌとＧａを含む窒化物半導体層であり、第１層と第２層とを有し、前記第１層のＡｌ組成比は前記第２層のＡｌ組成比よりも低い。前記第１導電型半導体層は、前記第２導電型半導体層および前記活性層が積層された第１領域と、前記第２導電型半導体層および前記活性層から露出し、前記第１導電部材と接続される第２領域とを有する。前記第１領域に設けられた前記第１層の厚さは、前記第２領域に設けられた前記第１層の厚さよりも薄い、または、前記第１領域には前記第１層が設けられていない。 According to one aspect of the present invention, the light emitting element is provided between the first conductive semiconductor layer, the second conductive semiconductor layer, the first conductive semiconductor layer, and the second conductive semiconductor layer. A semiconductor laminate having an active layer, a first conductive member electrically connected to the first conductive semiconductor layer, and a second conductive member electrically connected to the second conductive semiconductor layer. , Equipped with. The first conductive semiconductor layer is a nitride semiconductor layer containing Al and Ga, has a first layer and a second layer, and the Al composition ratio of the first layer is higher than the Al composition ratio of the second layer. Is also low. The first conductive semiconductor layer is exposed from the first region in which the second conductive semiconductor layer and the active layer are laminated, the second conductive semiconductor layer and the active layer, and the first conductive member. It has a second area to be connected. The thickness of the first layer provided in the first region is thinner than the thickness of the first layer provided in the second region, or the first layer is provided in the first region. Not.

本発明の一態様によれば、発光素子の製造方法は、基板上に、第１導電型半導体層と、前記第１導電型半導体層上に設けられた活性層と、前記活性層上に設けられた第２導電型半導体層とを含む半導体積層体を形成する工程であって、前記第１導電型半導体層は、ＡｌとＧａを含む窒化物半導体層であり、前記基板上に設けられた第１層と、前記第１層上に設けられた第２層とを有し、前記第１層のＡｌ組成比は前記第２層のＡｌ組成比よりも低い、前記半導体積層体を形成する工程と、前記第２導電型半導体層の一部および前記活性層の一部を除去し、前記第２導電型半導体層および前記活性層から前記第１導電型半導体層の一部を露出させ、前記第１導電型半導体層に、前記第２導電型半導体層および前記活性層が除去されずに残っている第１領域と、前記第２導電型半導体層および前記活性層から露出された前記第１導電型半導体層の前記一部を含む第２領域とを形成する工程と、前記第１領域と前記第２領域を形成した後、前記基板を除去し、前記第１導電型半導体層の前記第１層の表面を露出させる工程と、前記第１層の表面を露出させた後、前記第１領域に設けられた前記第１層の少なくとも一部を除去し、前記第２領域に、前記第１領域に設けられた第１層よりも厚い第１層を残す、または、前記第１領域に設けられた第２層を前記第１層から露出させる工程と、を備える。 According to one aspect of the present invention, the method for manufacturing a light emitting element is provided on a substrate, a first conductive semiconductor layer, an active layer provided on the first conductive semiconductor layer, and an active layer. In the step of forming a semiconductor laminate including the second conductive semiconductor layer, the first conductive semiconductor layer is a nitride semiconductor layer containing Al and Ga, and is provided on the substrate. The semiconductor laminate is formed by having a first layer and a second layer provided on the first layer, and the Al composition ratio of the first layer is lower than the Al composition ratio of the second layer. In the step, a part of the second conductive semiconductor layer and a part of the active layer are removed, and a part of the first conductive semiconductor layer is exposed from the second conductive semiconductor layer and the active layer. The first region in which the second conductive semiconductor layer and the active layer remain without being removed from the first conductive semiconductor layer, and the second region exposed from the second conductive semiconductor layer and the active layer. After forming the first region and the second region in the step of forming the second region including the part of the first conductive semiconductor layer, the substrate is removed and the first conductive semiconductor layer is described. After exposing the surface of the first layer and the surface of the first layer, at least a part of the first layer provided in the first region is removed, and the second region is covered with the above. It comprises a step of leaving a first layer thicker than the first layer provided in the first region, or exposing a second layer provided in the first region from the first layer.

本発明の一実施形態によれば、光取り出し効率の向上が可能な発光素子及び発光素子の製造方法を提供することができる。 According to one embodiment of the present invention, it is possible to provide a light emitting element and a method for manufacturing the light emitting element, which can improve the light extraction efficiency.

本発明の第１実施形態の発光素子における構成の一部を示す模式平面図である。It is a schematic plan view which shows a part of the structure in the light emitting element of 1st Embodiment of this invention. 図１のII-II線における模式断面図である。It is a schematic cross-sectional view in line II-II of FIG. 本発明の第１実施形態の発光素子における半導体積層体の一部を拡大した模式断面図である。It is a schematic cross-sectional view which enlarged a part of the semiconductor laminate in the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 本発明の第１実施形態の発光素子の製造方法の他の工程の例を示す模式断面図である。It is a schematic cross-sectional view which shows the example of another process of the manufacturing method of the light emitting element of 1st Embodiment of this invention. 図１１に示す工程で得られる発光素子の模式断面図である。It is a schematic cross-sectional view of the light emitting element obtained in the process shown in FIG. 本発明の第２実施形態の発光素子の模式断面図である。It is a schematic cross-sectional view of the light emitting element of the 2nd Embodiment of this invention. 本発明の第３実施形態の発光素子の模式断面図である。It is a schematic cross-sectional view of the light emitting element of the 3rd Embodiment of this invention. 第１実施形態の変形例の発光素子の模式断面図である。It is a schematic cross-sectional view of the light emitting element of the modification of 1st Embodiment. 第１実施形態の他の変形例の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of another modification of 1st Embodiment. 第１実施形態の他の変形例の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of another modification of 1st Embodiment. 第１実施形態の他の変形例の発光素子の製造方法の一工程を示す模式断面図である。It is a schematic cross-sectional view which shows one step of the manufacturing method of the light emitting element of another modification of 1st Embodiment. 第１実施形態の他の変形例の発光素子の模式断面図である。It is a schematic cross-sectional view of the light emitting element of another modification of 1st Embodiment.

以下、図面を参照し、実施形態について説明する。なお、各図面中、同じ構成には同じ符号を付している。 Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals.

［第１実施形態］
図１は、本発明の第１実施形態の発光素子１における構成の一部を示す模式平面図である。図２は、図１のII-II線における端面のみを示す模式断面図である。 [First Embodiment]
FIG. 1 is a schematic plan view showing a part of the configuration of the light emitting device 1 according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing only the end face of the line II-II of FIG.

発光素子１は、支持基板１００と、支持基板１００上に設けられた半導体積層体２０とを有する。 The light emitting element 1 has a support substrate 100 and a semiconductor laminate 20 provided on the support substrate 100.

図３は、半導体積層体２０の一部を拡大した模式断面図である。 FIG. 3 is an enlarged schematic cross-sectional view of a part of the semiconductor laminate 20.

半導体積層体２０は、第１導電型半導体層１０と、第２導電型半導体層１５と、活性層１４とを有する。活性層１４は、第１導電型半導体層１０と第２導電型半導体層１５との間に設けられ、光を発する発光層である。例えば、活性層１４からの光のピーク波長は４００ｎｍ以下であり、具体的には２１０ｎｍ以上４００ｎｍ以下であり、より具体的には３００ｎｍ以上４００ｎｍ以下である。例えば、活性層１４は紫外光を発する。なお、活性層１４の厚さは、第１導電型半導体層１０及び第２導電型半導体層１５の厚さに比べて薄いため、図２において線で示している。また、図４から図１３、及び図１５～図１９においても同様に、活性層１４は線で示している。 The semiconductor laminate 20 has a first conductive type semiconductor layer 10, a second conductive type semiconductor layer 15, and an active layer 14. The active layer 14 is a light emitting layer that is provided between the first conductive type semiconductor layer 10 and the second conductive type semiconductor layer 15 and emits light. For example, the peak wavelength of the light from the active layer 14 is 400 nm or less, specifically 210 nm or more and 400 nm or less, and more specifically 300 nm or more and 400 nm or less. For example, the active layer 14 emits ultraviolet light. Since the thickness of the active layer 14 is thinner than the thickness of the first conductive type semiconductor layer 10 and the second conductive type semiconductor layer 15, it is shown by a line in FIG. Similarly, in FIGS. 4 to 13 and FIGS. 15 to 19, the active layer 14 is shown by a line.

第１導電型半導体層１０、第２導電型半導体層１５、および活性層１４は、窒化物半導体層からなる。窒化物半導体は、ＩｎｘＡｌｙＧａ１－ｘ－ｙＮ（０≦ｘ≦１、０≦ｙ≦１、ｘ＋ｙ≦１）なる化学式において組成比ｘ及びｙをそれぞれの範囲内で変化させた全ての組成の半導体を含む。第１導電型半導体層１０は、ＡｌとＧａを含む窒化物半導体層であり、例えばＡｌＧａＮ層である。第１導電型半導体層１０は、例えばｎ型半導体層である。第１導電型半導体層１０は、ｎ型不純物として、例えばＳｉを含む。第２導電型半導体層１５は、例えばｐ型半導体層である。第２導電型半導体層１５は、ｐ型不純物として、例えばＭｇを含む。 The first conductive semiconductor layer 10, the second conductive semiconductor layer 15, and the active layer 14 are made of a nitride semiconductor layer. In the nitride semiconductor, the composition ratios x and y were changed within the respective ranges in the chemical formula In x Al y Ga 1-x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). Includes semiconductors of all compositions. The first conductive semiconductor layer 10 is a nitride semiconductor layer containing Al and Ga, for example, an AlGaN layer. The first conductive type semiconductor layer 10 is, for example, an n-type semiconductor layer. The first conductive type semiconductor layer 10 contains, for example, Si as an n-type impurity. The second conductive type semiconductor layer 15 is, for example, a p-type semiconductor layer. The second conductive semiconductor layer 15 contains, for example, Mg as a p-type impurity.

第１導電型半導体層１０は、第１層１１と第２層１２とを有する。第１層１１および第２層１２は、例えばＡｌＧａＮ層である。第１層１１のＡｌ組成比は、第２層１２のＡｌ組成比よりも低い。例えば、第１層１１のＡｌ組成比は１％以上３％以下である。第２層１２のＡｌ組成比は３％以上５％以下である。第１層１１のＡｌ組成比と第２層１２のＡｌ組成比の差は、１％以上４％以下であることが好ましい。例えば、第１層１１のＡｌ組成比は３％であり、第２層１２のＡｌ組成比は５％である。 The first conductive semiconductor layer 10 has a first layer 11 and a second layer 12. The first layer 11 and the second layer 12 are, for example, an AlGaN layer. The Al composition ratio of the first layer 11 is lower than the Al composition ratio of the second layer 12. For example, the Al composition ratio of the first layer 11 is 1% or more and 3% or less. The Al composition ratio of the second layer 12 is 3% or more and 5% or less. The difference between the Al composition ratio of the first layer 11 and the Al composition ratio of the second layer 12 is preferably 1% or more and 4% or less. For example, the Al composition ratio of the first layer 11 is 3%, and the Al composition ratio of the second layer 12 is 5%.

第１導電型半導体層１０は、第１領域ａ１と第２領域ａ２とを有する。第１領域ａ１および第２領域ａ２は、それぞれ第２層１２を有する。第１領域ａ１の第２層１２には、活性層１４および第２導電型半導体層１５が積層されている。第１領域ａ１の第２層１２における支持基板１００側の面に、活性層１４と第２導電型半導体層１５が順に積層されている。 The first conductive semiconductor layer 10 has a first region a1 and a second region a2. The first region a1 and the second region a2 each have a second layer 12. The active layer 14 and the second conductive semiconductor layer 15 are laminated on the second layer 12 of the first region a1. The active layer 14 and the second conductive semiconductor layer 15 are sequentially laminated on the surface of the second layer 12 of the first region a1 on the support substrate 100 side.

第１領域ａ１には第１層１１が設けられていない。第１領域ａ１の第２層１２における支持基板１００とは反対側の第１面１２ａには第１層１１が設けられず、第１面１２ａは第１層１１から露出している。第１面１２ａは、光の主な取り出し面として機能する。上面視において、第１領域ａ１は、第１面１２ａが設けられた領域である。断面視において、第１領域ａ１は、第１導電型半導体層１０のうち、第１面１２ａの直下に設けられた領域である。 The first layer 11 is not provided in the first region a1. The first layer 11 is not provided on the first surface 12a of the second layer 12 of the first region a1 opposite to the support substrate 100, and the first surface 12a is exposed from the first layer 11. The first surface 12a functions as a main extraction surface for light. In top view, the first region a1 is a region provided with the first surface 12a. In the cross-sectional view, the first region a1 is a region of the first conductive semiconductor layer 10 provided directly below the first surface 12a.

第２領域ａ２の第２層１２には第１層１１が積層され、活性層１４および第２導電型半導体層１５は積層されていない。第２領域ａ２の第２層１２における支持基板１００側の面（第２面）１２ｂは、第２導電型半導体層１５および活性層１４から露出している。第２面１２ｂは、後述する第１導電部材４０とのコンタクト面として機能する。上面視において、第２領域ａ２は、第２面１２ｂが設けられた領域である。断面視において、第２領域ａ２は、第１導電型半導体層１０のうち、第２面１２ｂの直上に設けられた領域である。 The first layer 11 is laminated on the second layer 12 of the second region a2, and the active layer 14 and the second conductive semiconductor layer 15 are not laminated. The surface (second surface) 12b on the support substrate 100 side in the second layer 12 of the second region a2 is exposed from the second conductive semiconductor layer 15 and the active layer 14. The second surface 12b functions as a contact surface with the first conductive member 40 described later. In top view, the second region a2 is a region provided with the second surface 12b. In the cross-sectional view, the second region a2 is a region of the first conductive semiconductor layer 10 provided directly above the second surface 12b.

図１に示すように、平面視において、複数の第２領域ａ２が島状に配置され、それぞれの第２領域ａ２の周囲は第１領域ａ１に囲まれている。平面視において、第１領域ａ１の面積は、複数の第２領域ａ２の合計面積よりも大きい。 As shown in FIG. 1, in a plan view, a plurality of second regions a2 are arranged in an island shape, and the periphery of each of the second regions a2 is surrounded by the first region a1. In a plan view, the area of the first region a1 is larger than the total area of the plurality of second regions a2.

図３に示す例では、第１領域ａ１と第２領域ａ２との間に、第１層１１、第２層１２、活性層１４、および第２導電型半導体層１５が積層された第３領域ａ３が存在する。第３領域ａ３は、第１領域ａ１と第２領域ａ２の間に位置し、少なくとも第１層１１及び第２層１２を含む。第３領域ａ３における活性層１４および第２導電型半導体層１５が除去され、第１領域ａ１と第２領域ａ２とが連続していてもよい。 In the example shown in FIG. 3, the third region in which the first layer 11, the second layer 12, the active layer 14, and the second conductive semiconductor layer 15 are laminated between the first region a1 and the second region a2. a3 exists. The third region a3 is located between the first region a1 and the second region a2 and includes at least the first layer 11 and the second layer 12. The active layer 14 and the second conductive semiconductor layer 15 in the third region a3 may be removed, and the first region a1 and the second region a2 may be continuous.

第２領域ａ２には、第１層１１と第２層１２が積層されている。第１領域ａ１には、第１層１１は設けられず、第２層１２が設けられている。図２に示す例においては、第１領域ａ１における第１導電型半導体層１０の厚さは、第２領域ａ２における第１導電型半導体層１０の厚さよりも薄い。第１領域ａ１又は第２領域ａ２における第１導電型半導体層１０の厚さとは、第１領域ａ１又は第２領域ａ２における第１導電型半導体層１０の最大厚さを意味する。 The first layer 11 and the second layer 12 are laminated on the second region a2. The first layer 11 is not provided in the first region a1, but the second layer 12 is provided. In the example shown in FIG. 2, the thickness of the first conductive semiconductor layer 10 in the first region a1 is thinner than the thickness of the first conductive semiconductor layer 10 in the second region a2. The thickness of the first conductive semiconductor layer 10 in the first region a1 or the second region a2 means the maximum thickness of the first conductive semiconductor layer 10 in the first region a1 or the second region a2.

第２領域ａ２に設けられた第２層１２の厚さは、第２領域ａ２に設けられた第１層１１の厚さよりも薄いことが好ましい。例えば、第２領域ａ２に設けられた第２層１２の厚さは、第２領域ａ２に設けられた第１層１１の厚さの８０％以下であることが好ましく、７０％以下であることがさらに好ましい。第２領域ａ２に設けられた第１層１１の厚さは、例えば、０．３μｍ以上３μｍ以下であることが好ましく、１μｍ以上２．５μｍ以下であることがさらに好ましい。例えば、第２領域ａ２に設けられた第２層１２の厚さは、例えば、０．３μｍ以上１．５μｍ以下であることが好ましく、０．５μｍ以上１．２μｍ以下であることがさらに好ましい。なお、図１５に示すように、第１層１１の厚さは、第２層１２の厚さと同じとしてもよい。ここで、第２領域ａ２に設けられた第１層１１の厚さとは、第２領域ａ２に設けられた第１層１１の最大厚さを意味する。また、第２領域ａ２に設けられた第２層１２の厚さとは、第２領域ａ２に設けられた第２層１２の最大厚さを意味する。 The thickness of the second layer 12 provided in the second region a2 is preferably thinner than the thickness of the first layer 11 provided in the second region a2. For example, the thickness of the second layer 12 provided in the second region a2 is preferably 80% or less, and preferably 70% or less of the thickness of the first layer 11 provided in the second region a2. Is even more preferable. The thickness of the first layer 11 provided in the second region a2 is preferably, for example, 0.3 μm or more and 3 μm or less, and more preferably 1 μm or more and 2.5 μm or less. For example, the thickness of the second layer 12 provided in the second region a2 is preferably, for example, 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.2 μm or less. As shown in FIG. 15, the thickness of the first layer 11 may be the same as the thickness of the second layer 12. Here, the thickness of the first layer 11 provided in the second region a2 means the maximum thickness of the first layer 11 provided in the second region a2. Further, the thickness of the second layer 12 provided in the second region a2 means the maximum thickness of the second layer 12 provided in the second region a2.

第２領域ａ２の第１層１１は、第２層１２が積層された面の反対側に第３面１１ａを有する。第１領域ａ１の第２層１２の第１面１２ａと、第２領域ａ２の第１層１１の第３面１１ａとの間には段差が形成されている。図１に示すように、上面視において、第３面１１ａの外縁は、第１導電部材４０のｎ側導通部４０ａと反射電極３０の外縁との間に位置している。 The first layer 11 of the second region a2 has a third surface 11a on the opposite side of the surface on which the second layer 12 is laminated. A step is formed between the first surface 12a of the second layer 12 of the first region a1 and the third surface 11a of the first layer 11 of the second region a2. As shown in FIG. 1, in top view, the outer edge of the third surface 11a is located between the n-side conductive portion 40a of the first conductive member 40 and the outer edge of the reflective electrode 30.

第１領域ａ１の第２層１２の第１面１２ａは粗面化され、第１面１２ａに凹凸が形成されている。第２領域ａ２の第１層１１の第３面１１ａも粗面化され、第３面１１ａに凹凸が形成されている。第１面１２ａの凹凸の大きさ、および第３面１１ａの凹凸の大きさは、第１面１２ａと第３面１１ａとの間の段差の大きさよりも小さい。 The first surface 12a of the second layer 12 of the first region a1 is roughened, and unevenness is formed on the first surface 12a. The third surface 11a of the first layer 11 of the second region a2 is also roughened, and unevenness is formed on the third surface 11a. The size of the unevenness of the first surface 12a and the size of the unevenness of the third surface 11a are smaller than the size of the step between the first surface 12a and the third surface 11a.

第１面１２ａの凹凸は複数の第１凸部１０ａを含む。第３面１１ａの凹凸は複数の第２凸部１０ｂを含む。第１凸部１０ａの算術平均高さは、第２凸部１０ｂの算術平均高さよりも高い。第１凸部１０ａおよび第２凸部１０ｂは、例えば錐体形状に形成されている。第１凸部１０ａおよび第２凸部１０ｂは図３の断面視において三角形で表され、第１凸部１０ａの高さおよび第２凸部１０ｂの高さは、その三角形の高さで表している。 The unevenness of the first surface 12a includes a plurality of first convex portions 10a. The unevenness of the third surface 11a includes a plurality of second convex portions 10b. The arithmetic mean height of the first convex portion 10a is higher than the arithmetic average height of the second convex portion 10b. The first convex portion 10a and the second convex portion 10b are formed in, for example, a cone shape. The first convex portion 10a and the second convex portion 10b are represented by triangles in the cross-sectional view of FIG. 3, and the height of the first convex portion 10a and the height of the second convex portion 10b are represented by the height of the triangle. There is.

図２に示すように、第１導電型半導体層１０の外周部には、第１層１１および第２層１２が積層されている。その外周部の第２層１２には、活性層１４および第２導電型半導体層１５が積層されず、活性層１４および第２導電型半導体層１５から露出した第４面１２ｃが形成されている。第４面１２ｃは、図１に示す平面視において、第１領域ａ１および第２領域ａ２が形成された領域を囲んでいる。第１導電型半導体層１０の外周部における第１層１１の表面である第５面１１ｂも粗面化され、第５面１１ｂに複数の第２凸部１０ｂが形成されている。第１領域ａ１に形成された第１凸部１０ａの算術平均高さは、第１導電型半導体層１０の外周部の第５面１１ｂに形成された第２凸部１０ｂの算術平均高さよりも高い。 As shown in FIG. 2, the first layer 11 and the second layer 12 are laminated on the outer peripheral portion of the first conductive semiconductor layer 10. The active layer 14 and the second conductive semiconductor layer 15 are not laminated on the second layer 12 on the outer peripheral portion thereof, and the fourth surface 12c exposed from the active layer 14 and the second conductive semiconductor layer 15 is formed. .. The fourth surface 12c surrounds the region in which the first region a1 and the second region a2 are formed in the plan view shown in FIG. The fifth surface 11b, which is the surface of the first layer 11 on the outer peripheral portion of the first conductive semiconductor layer 10, is also roughened, and a plurality of second convex portions 10b are formed on the fifth surface 11b. The arithmetic mean height of the first convex portion 10a formed in the first region a1 is larger than the arithmetic average height of the second convex portion 10b formed on the fifth surface 11b of the outer peripheral portion of the first conductive semiconductor layer 10. high.

発光素子１は、さらに、第１導電部材４０と、第２導電部材５０と、第３導電部材６０と、反射電極３０と、第１パッド電極７１と、第２パッド電極７２と、第１絶縁膜８１～第４絶縁膜８４とを有する。 The light emitting element 1 further includes a first conductive member 40, a second conductive member 50, a third conductive member 60, a reflection electrode 30, a first pad electrode 71, a second pad electrode 72, and a first insulation. It has a film 81 to a fourth insulating film 84.

第２導電型半導体層１５の表面（活性層１４が積層された面の反対側の面）に、反射電極３０が設けられている。反射電極３０は、第２導電型半導体層１５の表面に接し、第２導電型半導体層１５と電気的に接続されている。反射電極３０は、活性層１４が発する光に対して高い反射性を有することが好ましい。反射電極３０は、例えばＡｇを含む金属層である。ここで、反射電極３０が、活性層１４が発する光に対して高い反射率を有するとは、反射電極３０が活性層１４からの光の波長に対して、７０％以上の反射率、好ましくは８０％以上の反射率を有していることを意味する。 A reflective electrode 30 is provided on the surface of the second conductive semiconductor layer 15 (the surface opposite to the surface on which the active layer 14 is laminated). The reflective electrode 30 is in contact with the surface of the second conductive semiconductor layer 15 and is electrically connected to the second conductive semiconductor layer 15. The reflective electrode 30 preferably has high reflectivity with respect to the light emitted by the active layer 14. The reflective electrode 30 is, for example, a metal layer containing Ag. Here, the fact that the reflective electrode 30 has a high reflectance with respect to the light emitted by the active layer 14 means that the reflective electrode 30 has a reflectance of 70% or more, preferably 70% or more, with respect to the wavelength of the light from the active layer 14. It means that it has a reflectance of 80% or more.

第２導電型半導体層１５の表面は、反射電極３０が設けられていない領域も有する。その領域は第１絶縁膜８１で覆われている。また、第１絶縁膜８１は、反射電極３０の一部も覆っている。第１絶縁膜８１は、例えば、シリコン窒化膜またはシリコン酸化膜である。 The surface of the second conductive semiconductor layer 15 also has a region in which the reflective electrode 30 is not provided. The region is covered with the first insulating film 81. The first insulating film 81 also covers a part of the reflective electrode 30. The first insulating film 81 is, for example, a silicon nitride film or a silicon oxide film.

第１絶縁膜８１を第２絶縁膜８２が覆っている。第２絶縁膜８２は、第１導電型半導体層１０の第４面１２ｃ、活性層１４の側面、および第２導電型半導体層１５の側面も覆っている。第２絶縁膜８２は、例えば、シリコン酸化膜である。 The first insulating film 81 is covered with the second insulating film 82. The second insulating film 82 also covers the fourth surface 12c of the first conductive semiconductor layer 10, the side surface of the active layer 14, and the side surface of the second conductive semiconductor layer 15. The second insulating film 82 is, for example, a silicon oxide film.

第２絶縁膜８２の表面に、第２導電部材５０が設けられている。第２導電部材５０は、例えば、ＡｌおよびＣｕの少なくともいずれかを含む金属層である。第２導電部材５０は、ｐ側導通部５０ａを有する。 A second conductive member 50 is provided on the surface of the second insulating film 82. The second conductive member 50 is, for example, a metal layer containing at least one of Al and Cu. The second conductive member 50 has a p-side conductive portion 50a.

反射電極３０は第１絶縁膜８１および第２絶縁膜８２から露出された表面を有し、その表面に第２導電部材５０のｐ側導通部５０ａが接している。第２導電部材５０は、ｐ側導通部５０ａおよび反射電極３０を介して、第１領域ａ１に積層された第２導電型半導体層１５と電気的に接続されている。 The reflective electrode 30 has a surface exposed from the first insulating film 81 and the second insulating film 82, and the p-side conductive portion 50a of the second conductive member 50 is in contact with the surface thereof. The second conductive member 50 is electrically connected to the second conductive semiconductor layer 15 laminated in the first region a1 via the p-side conductive portion 50a and the reflective electrode 30.

第２導電部材５０を第３絶縁膜８３が覆っている。第３絶縁膜８３は、例えば、シリコン酸化膜である。 The second conductive member 50 is covered with the third insulating film 83. The third insulating film 83 is, for example, a silicon oxide film.

第３絶縁膜８３の表面に、第１導電部材４０が設けられている。第１導電部材４０は、例えば、ＡｌおよびＣｕの少なくともいずれかを含む金属層である。第１導電部材４０は、ｎ側導通部４０ａを有する。 The first conductive member 40 is provided on the surface of the third insulating film 83. The first conductive member 40 is, for example, a metal layer containing at least one of Al and Cu. The first conductive member 40 has an n-side conductive portion 40a.

第２領域ａ２の第２層１２の第２面１２ｂの一部は、第２絶縁膜８２に覆われている。第２面１２ｂは平面視において例えば円形に形成され、その外周側に第１絶縁膜８１が配置されている。第２面１２ｂの中心を含む部分は、第１絶縁膜８１から露出され、第１導電部材４０のｎ側導通部４０ａが接している。第１導電部材４０は、ｎ側導通部４０ａを介して、第１導電型半導体層１０と電気的に接続されている。 A part of the second surface 12b of the second layer 12 of the second region a2 is covered with the second insulating film 82. The second surface 12b is formed, for example, in a circular shape in a plan view, and the first insulating film 81 is arranged on the outer peripheral side thereof. The portion including the center of the second surface 12b is exposed from the first insulating film 81 and is in contact with the n-side conductive portion 40a of the first conductive member 40. The first conductive member 40 is electrically connected to the first conductive semiconductor layer 10 via the n-side conductive portion 40a.

第１導電部材４０と第２導電部材５０との間には第３絶縁膜８３が設けられ、第１導電部材４０と第２導電部材５０とは第３絶縁膜８３によって絶縁分離されている。 A third insulating film 83 is provided between the first conductive member 40 and the second conductive member 50, and the first conductive member 40 and the second conductive member 50 are insulated and separated by the third insulating film 83.

図１に示すように、支持基板１００は平面視において四角形状に形成されている。その支持基板１００の対角位置に第１パッド電極７１と第２パッド電極７２が配置されている。半導体積層体２０は、平面視において、第１パッド電極７１および第２パッド電極７２が配置された対角の角部を欠いた略四角形状に形成されている。 As shown in FIG. 1, the support substrate 100 is formed in a rectangular shape in a plan view. The first pad electrode 71 and the second pad electrode 72 are arranged at diagonal positions of the support substrate 100. In a plan view, the semiconductor laminate 20 is formed in a substantially quadrangular shape lacking diagonal corners where the first pad electrode 71 and the second pad electrode 72 are arranged.

図２に示すように、第１導電部材４０は、第１パッド電極７１の下方に位置するパッド接続部４０ｂを有する。パッド接続部４０ｂ上に第３導電部材６０が設けられている。第３導電部材６０は、例えば、第２導電部材５０と同じ材料且つ同じ工程で形成することができる。第３導電部材６０は、第２導電部材５０から分離した島状に形成されている。第３導電部材６０上に、第１パッド電極７１が設けられている。第１パッド電極７１は、第３導電部材６０を介して第１導電部材４０と電気的に接続されている。 As shown in FIG. 2, the first conductive member 40 has a pad connecting portion 40b located below the first pad electrode 71. A third conductive member 60 is provided on the pad connecting portion 40b. The third conductive member 60 can be formed, for example, with the same material and the same process as the second conductive member 50. The third conductive member 60 is formed in an island shape separated from the second conductive member 50. A first pad electrode 71 is provided on the third conductive member 60. The first pad electrode 71 is electrically connected to the first conductive member 40 via the third conductive member 60.

第２導電部材５０は、第２パッド電極７２の下方に位置するパッド接続部５０ｂを有する。パッド接続部５０ｂ上に第２パッド電極７２が設けられ、第２パッド電極７２は第２導電部材５０と電気的に接続されている。 The second conductive member 50 has a pad connecting portion 50b located below the second pad electrode 72. A second pad electrode 72 is provided on the pad connecting portion 50b, and the second pad electrode 72 is electrically connected to the second conductive member 50.

第１パッド電極７１および第２パッド電極７２は、例えば、Ｔｉ、Ｐｔ、およびＡｕからなる群から選択される少なくとも１つの金属材料を含む。 The first pad electrode 71 and the second pad electrode 72 include, for example, at least one metal material selected from the group consisting of Ti, Pt, and Au.

第１導電部材４０は、接合層１０１を介して、支持基板１００に接合されている。接合層１０１は、例えばＳｎ等のはんだ材料を含む金属層である。支持基板１００は、例えばシリコン基板である。 The first conductive member 40 is bonded to the support substrate 100 via the bonding layer 101. The bonding layer 101 is a metal layer containing a solder material such as Sn. The support substrate 100 is, for example, a silicon substrate.

半導体積層体２０の上面および側面は、第４絶縁膜８４に覆われている。半導体積層体２０の上面は、第１領域ａ１の第２層１２の第１面１２ａ、第２領域ａ２の第１層１１の第３面１１ａ、および外周部の第１層１１の第５面１１ｂを含む。第４絶縁膜８４は、例えばシリコン酸化膜である。 The upper surface and the side surface of the semiconductor laminate 20 are covered with the fourth insulating film 84. The upper surface of the semiconductor laminate 20 is the first surface 12a of the second layer 12 of the first region a1, the third surface 11a of the first layer 11 of the second region a2, and the fifth surface of the first layer 11 on the outer peripheral portion. Includes 11b. The fourth insulating film 84 is, for example, a silicon oxide film.

第１領域ａ１の第１面１２ａに形成された複数の第１凸部１０ａを含む凹凸を覆う第４絶縁膜８４の表面にも凹凸が形成される。第２領域ａ２の第３面１１ａに形成された複数の第２凸部１０ｂを含む凹凸を覆う第４絶縁膜８４の表面にも凹凸が形成される。第１導電型半導体層１０の外周部の第１層１１の第５面１１ｂに形成された複数の第２凸部１０ｂを含む凹凸を覆う第４絶縁膜８４の表面にも凹凸が形成される。 The unevenness is also formed on the surface of the fourth insulating film 84 that covers the unevenness including the plurality of first convex portions 10a formed on the first surface 12a of the first region a1. The unevenness is also formed on the surface of the fourth insulating film 84 that covers the unevenness including the plurality of second convex portions 10b formed on the third surface 11a of the second region a2. Concavities and convexities are also formed on the surface of the fourth insulating film 84 that covers the irregularities including the plurality of second convex portions 10b formed on the fifth surface 11b of the first layer 11 on the outer peripheral portion of the first conductive semiconductor layer 10. ..

第１領域ａ１の第４絶縁膜８４の表面に形成された複数の凸部の算術平均高さは、第２領域ａ２の第４絶縁膜８４の表面に形成された複数の凸部の算術平均高さよりも高い。また、第１領域ａ１の第４絶縁膜８４の表面に形成された複数の凸部の算術平均高さは、第１導電型半導体層１０の外周部の第４絶縁膜８４の表面に形成された複数の凸部の算術平均高さよりも高い。活性層１４が積層され、光の取り出し効率に大きく寄与する第１領域ａ１の第４絶縁膜８４の表面に算術平均高さがより高い凸部を形成することで、光取り出し効率を向上できる。 The arithmetic mean height of the plurality of protrusions formed on the surface of the fourth insulating film 84 of the first region a1 is the arithmetic mean of the plurality of protrusions formed on the surface of the fourth insulating film 84 of the second region a2. Higher than height. Further, the arithmetic mean height of the plurality of convex portions formed on the surface of the fourth insulating film 84 of the first region a1 is formed on the surface of the fourth insulating film 84 on the outer peripheral portion of the first conductive semiconductor layer 10. It is higher than the arithmetic mean height of multiple convex parts. The light extraction efficiency can be improved by forming a convex portion having a higher arithmetic mean height on the surface of the fourth insulating film 84 of the first region a1 in which the active layer 14 is laminated and greatly contributes to the light extraction efficiency.

活性層１４が発する光は、第１導電型半導体層１０中を伝播して、半導体積層体２０の外部に取り出される。第１導電型半導体層１０において、第２層１２のＡｌ組成比は第１層１１のＡｌ組成比よりも高いため、第２層１２における光吸収率は第１層１１における光吸収率よりも低い。特に活性層１４からピーク波長が４００ｎｍ以下の比較的波長の短い光が出射される場合、第１導電型半導体層１０にＡｌ組成比の高いＡｌＧａＮを用いることで、第１導電型半導体層１０にＧａＮを用いるよりも第１導電型半導体層１０による光吸収を抑制することができる。活性層１４が積層された第１領域ａ１における光吸収は、活性層１４が積層されていない第２領域ａ２における光吸収よりも、半導体積層体２０からの光取り出し効率に大きく影響する。そのため、第１領域ａ１に、第２層１２よりも光吸収率が高い第１層１１を設けないことで、第１領域ａ１に第１層１１を設けた場合よりも光の取り出し効率を向上させることができる。 The light emitted by the active layer 14 propagates in the first conductive semiconductor layer 10 and is taken out of the semiconductor laminate 20. In the first conductive semiconductor layer 10, the Al composition ratio of the second layer 12 is higher than the Al composition ratio of the first layer 11, so that the light absorption rate of the second layer 12 is higher than the light absorption rate of the first layer 11. Low. In particular, when light having a peak wavelength of 400 nm or less is emitted from the active layer 14, the first conductive semiconductor layer 10 is formed by using AlGaN having a high Al composition ratio for the first conductive semiconductor layer 10. Light absorption by the first conductive semiconductor layer 10 can be suppressed as compared with the use of GaN. The light absorption in the first region a1 on which the active layer 14 is laminated has a greater influence on the light extraction efficiency from the semiconductor laminate 20 than the light absorption in the second region a2 in which the active layer 14 is not laminated. Therefore, by not providing the first layer 11 having a higher light absorption rate than the second layer 12 in the first region a1, the light extraction efficiency is improved as compared with the case where the first layer 11 is provided in the first region a1. Can be made to.

また、第１領域ａ１に第１層１１を設けないため、第１領域ａ１の第１導電型半導体層１０の厚さは、第２領域ａ２の第１導電型半導体層１０の厚さよりも薄い。光取り出し効率に大きく影響する第１領域ａ１の第１導電型半導体層１０の薄膜化により、第１領域ａ１における光吸収を抑制し、光取り出し効率を向上させることができる。 Further, since the first layer 11 is not provided in the first region a1, the thickness of the first conductive semiconductor layer 10 in the first region a1 is thinner than the thickness of the first conductive semiconductor layer 10 in the second region a2. .. By thinning the first conductive semiconductor layer 10 in the first region a1 that greatly affects the light extraction efficiency, it is possible to suppress light absorption in the first region a1 and improve the light extraction efficiency.

第２領域ａ２においては、第１導電部材４０が第１導電型半導体層１０に接続し、第１導電型半導体層１０に対する電流の導通部が配置されている。この第２領域ａ２においては、第２層１２だけでなく、第２層１２よりもＡｌ組成比が低い第１層１１も設けることで、第２領域ａ２に第１層１１を設けない場合に比べて、順方向電圧（駆動電圧）Ｖｆを低減することができ、また、第２領域ａ２における電流集中を抑制できる。さらに、第２領域ａ２の第１導電型半導体層１０の厚さを、第１領域ａ１の第１導電型半導体層１０の厚さより厚くすることで、第２領域ａ２の抵抗を低減し、Ｖｆを低減できる。 In the second region a2, the first conductive member 40 is connected to the first conductive type semiconductor layer 10, and a current conducting portion with respect to the first conductive type semiconductor layer 10 is arranged. In the second region a2, not only the second layer 12 but also the first layer 11 having a lower Al composition ratio than the second layer 12 is provided, so that the first layer 11 is not provided in the second region a2. In comparison, the forward voltage (drive voltage) Vf can be reduced, and the current concentration in the second region a2 can be suppressed. Further, by making the thickness of the first conductive semiconductor layer 10 in the second region a2 thicker than the thickness of the first conductive semiconductor layer 10 in the first region a1, the resistance of the second region a2 is reduced and Vf. Can be reduced.

ＡｌとＧａを含む窒化物半導体層におけるＡｌ組成比が高くなるにつれて、その窒化物半導体層におけるクラック発生率が上昇しやすい。また、ＡｌとＧａを含む窒化物半導体層の厚さを厚くするにつれて、その窒化物半導体層におけるクラック発生率が上昇しやすい。本実施形態によれば、第１層１１よりもＡｌ組成比が高い第２層１２の厚さを、第１層１１の厚さよりも薄く形成することで、第１導電型半導体層１０におけるクラックの発生を抑制できる。 As the Al composition ratio in the nitride semiconductor layer containing Al and Ga increases, the crack generation rate in the nitride semiconductor layer tends to increase. Further, as the thickness of the nitride semiconductor layer containing Al and Ga is increased, the crack generation rate in the nitride semiconductor layer tends to increase. According to the present embodiment, the thickness of the second layer 12, which has a higher Al composition ratio than that of the first layer 11, is formed to be thinner than the thickness of the first layer 11, whereby cracks in the first conductive semiconductor layer 10 are formed. Can be suppressed.

第１領域ａ１における光吸収の抑制、第２領域ａ２におけるＶｆの低減、および第１導電型半導体層１０におけるクラックの発生の抑制のため、第１導電型半導体層１０のＡｌ組成比は１％以上５％以下が好ましい。また第２領域ａ２に設けられた第２層１２の厚さは第２領域ａ２に設けられた第１層１１の厚さよりも薄いことが好ましい。例えば、第２領域ａ２に設けられた第２層１２の厚さは、第２領域ａ２に設けられた第１層１１の厚さの８０％以下が好ましい。第２領域ａ２に設けられた第２層１２の厚さを第２領域ａ２に設けられた第１層１１の厚さよりも薄くすることで、第１導電型半導体層１０におけるクラックの発生を抑制しつつ、第２領域ａ２におけるＶｆを低減させることができる。 The Al composition ratio of the first conductive semiconductor layer 10 is 1% in order to suppress light absorption in the first region a1, reduce Vf in the second region a2, and suppress the occurrence of cracks in the first conductive semiconductor layer 10. 5% or more is preferable. Further, it is preferable that the thickness of the second layer 12 provided in the second region a2 is thinner than the thickness of the first layer 11 provided in the second region a2. For example, the thickness of the second layer 12 provided in the second region a2 is preferably 80% or less of the thickness of the first layer 11 provided in the second region a2. By making the thickness of the second layer 12 provided in the second region a2 thinner than the thickness of the first layer 11 provided in the second region a2, the generation of cracks in the first conductive semiconductor layer 10 is suppressed. However, Vf in the second region a2 can be reduced.

第１領域ａ１から取り出される光の一部は、第２領域ａ２に設けられた第１層１１により吸収される場合があるため、第１領域ａ１と第２領域ａ２との間の距離を離して光吸収を抑制することが好ましい。一方で、第１領域ａ１と第２領域ａ２との間の距離を離しすぎると第２領域ａ２の平面視における面積が小さくなり、第２領域ａ２に電流が集中するおそれがある。本実施形態によれば、上面視において、第３面１１ａの外縁を、第１導電部材４０のｎ側導通部４０ａの外縁と反射電極３０外縁との間に位置させている。これにより、第２領域ａ２に設けられた第１層１１による光吸収を抑制しつつ、第２領域ａ２における電流集中を抑制できる。 Since a part of the light extracted from the first region a1 may be absorbed by the first layer 11 provided in the second region a2, the distance between the first region a1 and the second region a2 is increased. It is preferable to suppress light absorption. On the other hand, if the distance between the first region a1 and the second region a2 is too large, the area of the second region a2 in the plan view becomes small, and the current may be concentrated in the second region a2. According to the present embodiment, the outer edge of the third surface 11a is positioned between the outer edge of the n-side conductive portion 40a of the first conductive member 40 and the outer edge of the reflective electrode 30 in the top view. As a result, it is possible to suppress the current concentration in the second region a2 while suppressing the light absorption by the first layer 11 provided in the second region a2.

第１導電部材４０は、第１導電型半導体層１０の外周部における第２層１２の第４面１２ｃに電気的に接続してもよい。この場合、第１導電型半導体層１０の外周部において、第２層１２だけでなく、第２層１２よりもＡｌ組成比が低い第１層１１も設けることで、外周部に第１層１１を設けない場合に比べてＶｆを低減することができる。また、外周部におけるクラックの発生を抑制することができる。 The first conductive member 40 may be electrically connected to the fourth surface 12c of the second layer 12 in the outer peripheral portion of the first conductive type semiconductor layer 10. In this case, by providing not only the second layer 12 but also the first layer 11 having a lower Al composition ratio than the second layer 12 on the outer peripheral portion of the first conductive semiconductor layer 10, the first layer 11 is provided on the outer peripheral portion. Vf can be reduced as compared with the case where is not provided. In addition, it is possible to suppress the occurrence of cracks in the outer peripheral portion.

次に、図４～図１１を参照して、本発明の第１実施形態の発光素子１の製造方法について説明する。 Next, a method for manufacturing the light emitting device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 11.

図４に示すように、基板２００上に、例えばアンドープのＧａＮ層を含む下地層２０１を成長させる。下地層２０１の厚さは、例えば、６μｍ以上８μｍ以下である。そして下地層２０１を介して、半導体積層体２０が形成される。基板２００は、窒化物半導体層を成長させるための基板であり、例えば、サファイア基板である。基板２００上に下地層２０１を成長させる前に、例えばＡｌＧａＮやＡｌＮからなるバッファ層を形成してもよい。 As shown in FIG. 4, a base layer 201 including, for example, an undoped GaN layer is grown on the substrate 200. The thickness of the base layer 201 is, for example, 6 μm or more and 8 μm or less. Then, the semiconductor laminate 20 is formed via the base layer 201. The substrate 200 is a substrate for growing a nitride semiconductor layer, and is, for example, a sapphire substrate. Before growing the base layer 201 on the substrate 200, a buffer layer made of, for example, AlGaN or AlN may be formed.

半導体積層体２０は、第１導電型半導体層１０と、活性層１４と、第２導電型半導体層１５とを含む。第１導電型半導体層１０は、第１層１１と第２層１２を含む。下地層２０１上に、第１層１１、第２層１２、活性層１４、および第２導電型半導体層１５が順にエピタキシャル成長される。半導体積層体２０に含まれる半導体層の形成には、例えば、ＭＯＣＶＤ（metal organic chemical vapor deposition）法等を用いることができる。 The semiconductor laminate 20 includes a first conductive semiconductor layer 10, an active layer 14, and a second conductive semiconductor layer 15. The first conductive semiconductor layer 10 includes a first layer 11 and a second layer 12. The first layer 11, the second layer 12, the active layer 14, and the second conductive semiconductor layer 15 are epitaxially grown on the base layer 201 in this order. For the formation of the semiconductor layer contained in the semiconductor laminate 20, for example, a MOCVD (metal organic chemical vapor deposition) method or the like can be used.

前述したように、第１導電型半導体層１０は、ＡｌとＧａを含む窒化物半導体層であり、第１層１１のＡｌ組成比は第２層１２のＡｌ組成比よりも低い。例えば、第１層１１のＡｌ組成比は３％であり、第２層１２のＡｌ組成比は５％である。 As described above, the first conductive semiconductor layer 10 is a nitride semiconductor layer containing Al and Ga, and the Al composition ratio of the first layer 11 is lower than the Al composition ratio of the second layer 12. For example, the Al composition ratio of the first layer 11 is 3%, and the Al composition ratio of the second layer 12 is 5%.

半導体積層体２０を形成する工程において、第１層１１の厚さを、例えば、０．３μｍ以上３μｍ以下で形成することが好ましく、１μｍ以上２．５μｍ以下で形成することがさらに好ましい。例えば、第２層１２の厚さを、例えば、０．３μｍ以上１．５μｍ以下で形成することが好ましく、０．５μｍ以上１．２μｍ以下で形成することがさらに好ましい。例えば、第１層１１の厚さを２μｍとし、第２層１２の厚さを１μｍとする。第１層１１よりもＡｌ組成比が高い第２層１２の厚さを、第１層１１の厚さよりも薄く形成することで、第１導電型半導体層１０を成長させる際に生じるクラックの発生を抑制できる。 In the step of forming the semiconductor laminate 20, the thickness of the first layer 11 is preferably formed to be, for example, 0.3 μm or more and 3 μm or less, and more preferably 1 μm or more and 2.5 μm or less. For example, the thickness of the second layer 12 is preferably formed to be, for example, 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.2 μm or less. For example, the thickness of the first layer 11 is 2 μm, and the thickness of the second layer 12 is 1 μm. By forming the thickness of the second layer 12, which has a higher Al composition ratio than that of the first layer 11, to be thinner than the thickness of the first layer 11, cracks generated when the first conductive semiconductor layer 10 is grown are generated. Can be suppressed.

半導体積層体２０を形成した後、図５に示すように、第２導電型半導体層１５の一部および活性層１４の一部を除去する。例えば、ＲＩＥ（Reactive Ion Etching）法により、第２導電型半導体層１５の一部および活性層１４の一部を除去する。第２導電型半導体層１５の一部および活性層１４の一部が除去されることで、第２導電型半導体層１５および活性層１４から第１導電型半導体層１０の第２層１２の一部が露出される。 After forming the semiconductor laminate 20, as shown in FIG. 5, a part of the second conductive semiconductor layer 15 and a part of the active layer 14 are removed. For example, a part of the second conductive semiconductor layer 15 and a part of the active layer 14 are removed by the RIE (Reactive Ion Etching) method. By removing a part of the second conductive semiconductor layer 15 and a part of the active layer 14, the second conductive semiconductor layer 15 and the active layer 14 are one of the second layers 12 of the first conductive semiconductor layer 10. The part is exposed.

第１領域ａ１は、第２導電型半導体層１５および活性層１４が除去されずに残っている部分に位置する。第２領域ａ２は、第２導電型半導体層１５および活性層１４から露出された第２層１２の一部（第１導電型半導体層１０に対する導通部となる第２面１２ｂ）に位置する。 The first region a1 is located in a portion where the second conductive semiconductor layer 15 and the active layer 14 remain without being removed. The second region a2 is located on a part of the second layer 12 exposed from the second conductive semiconductor layer 15 and the active layer 14 (the second surface 12b which is the conductive portion with respect to the first conductive semiconductor layer 10).

この後、半導体積層体２０が基板２００上に形成された状態において、図２を参照して前述した反射電極３０、第１絶縁膜８１、第２絶縁膜８２、第２導電部材５０、第３導電部材６０、第３絶縁膜８３、および第１導電部材４０が形成される。反射電極３０、第１絶縁膜８１、第２絶縁膜８２、第２導電部材５０、第３導電部材６０、第３絶縁膜８３、および第１導電部材４０は、例えば、スパッタリング法、蒸着法等を用いて形成することができる。なお、第２導電部材５０と第３導電部材６０は同じ工程で形成することができる。第２導電部材５０のｐ側導通部５０ａは反射電極３０に接し、第１導電部材４０のｎ側導通部４０ａは第１導電型半導体層１０の第２面１２ｂに接する。 After that, in a state where the semiconductor laminate 20 is formed on the substrate 200, the reflective electrode 30, the first insulating film 81, the second insulating film 82, the second conductive member 50, and the third are described above with reference to FIG. The conductive member 60, the third insulating film 83, and the first conductive member 40 are formed. The reflective electrode 30, the first insulating film 81, the second insulating film 82, the second conductive member 50, the third conductive member 60, the third insulating film 83, and the first conductive member 40 are, for example, a sputtering method, a vapor deposition method, or the like. Can be formed using. The second conductive member 50 and the third conductive member 60 can be formed in the same process. The p-side conductive portion 50a of the second conductive member 50 is in contact with the reflective electrode 30, and the n-side conductive portion 40a of the first conductive member 40 is in contact with the second surface 12b of the first conductive semiconductor layer 10.

この後、図６に示すように、第１導電部材４０を接合層１０１を介して支持基板１００に接合する。なお、図６は、上下関係が図５と反対になっている。基板２００に支持された状態で、半導体積層体２０は支持基板１００に接合される。 After that, as shown in FIG. 6, the first conductive member 40 is bonded to the support substrate 100 via the bonding layer 101. In FIG. 6, the hierarchical relationship is opposite to that in FIG. The semiconductor laminate 20 is bonded to the support substrate 100 while being supported by the substrate 200.

半導体積層体２０と支持基板１００とを接合した後、基板２００を除去し、さらに下地層２０１も除去する。これにより、図７に示すように、第１導電型半導体層１０の第１層１１の表面が露出する。 After joining the semiconductor laminate 20 and the support substrate 100, the substrate 200 is removed, and the base layer 201 is also removed. As a result, as shown in FIG. 7, the surface of the first layer 11 of the first conductive semiconductor layer 10 is exposed.

図８に示すように、露出した第１層１１の表面上にマスク９１を形成し、例えばＲＩＥ法で第１導電型半導体層１０を選択的に除去する。第１導電型半導体層１０において活性層１４および第２導電型半導体層１５が積層された第１領域ａ１の第１層１１上にはマスク９１は形成されない。その第１領域ａ１に設けられた第１層１１は除去され、第１領域ａ１に設けられた第２層１２が第１層１１から露出する。この例では、第１領域ａ１に設けられた第１層１１のすべてを除去する。 As shown in FIG. 8, a mask 91 is formed on the surface of the exposed first layer 11, and the first conductive semiconductor layer 10 is selectively removed by, for example, the RIE method. The mask 91 is not formed on the first layer 11 of the first region a1 in which the active layer 14 and the second conductive semiconductor layer 15 are laminated in the first conductive semiconductor layer 10. The first layer 11 provided in the first region a1 is removed, and the second layer 12 provided in the first region a1 is exposed from the first layer 11. In this example, all of the first layer 11 provided in the first region a1 is removed.

第１導電部材４０のｎ側導通部４０ａが接続する第２面１２ｂを含む第２領域ａ２の第１層１１はマスク９１で覆われ除去されず、第２領域ａ２には第２層１２と、第２層１２よりも厚く、且つ第２層１２よりもＡｌ組成比が低い第１層１１とが残される。 The first layer 11 of the second region a2 including the second surface 12b to which the n-side conductive portion 40a of the first conductive member 40 is connected is covered with the mask 91 and is not removed, and the second region a2 is covered with the second layer 12. , The first layer 11 which is thicker than the second layer 12 and has a lower Al composition ratio than the second layer 12 is left.

マスク９１は、第１導電型半導体層１０において第１領域ａ１よりも外側の領域にも設けられ、第１領域ａ１よりも外側の領域の第１層１１も除去されずに、残される。 The mask 91 is also provided in the region outside the first region a1 in the first conductive semiconductor layer 10, and the first layer 11 in the region outside the first region a1 is also left without being removed.

第１層１１を選択的に除去した後、マスク９１は除去される。マスク９１を除去した後、図９に示すように、第１領域ａ１よりも外側の領域の第１層１１および第２層１２を除去する。第１領域ａ１よりも外側の領域の一部には、第１層１１と第２層１２との積層部が第１導電型半導体層１０の外周部として残される。この外周部よりも外側の領域においては、第２絶縁膜８２が第１層１１および第２層１２から露出する。 After selectively removing the first layer 11, the mask 91 is removed. After removing the mask 91, as shown in FIG. 9, the first layer 11 and the second layer 12 in the region outside the first region a1 are removed. A laminated portion of the first layer 11 and the second layer 12 is left as an outer peripheral portion of the first conductive semiconductor layer 10 in a part of the region outside the first region a1. In the region outside the outer peripheral portion, the second insulating film 82 is exposed from the first layer 11 and the second layer 12.

これまでの工程により、図９に示すように、第１領域ａ１においては第２層１２の表面が第１面１２ａとして露出し、第２領域ａ２においては第１層１１の表面が第３面１１ａとして露出し、外周部においては第１層１１の表面が第５面１１ｂとして露出する。この後、それら表面は粗面化される。例えば、ＴＭＡＨ（水酸化テトラメチルアンモニウム）を使って、それら表面を粗面化する。粗面化工程後における第１層１１の厚さは、例えば、０．３μｍ以上３μｍ以下とすることが好ましく、１μｍ以上２．５μｍ以下とすることがさらに好ましい。また、粗面化工程後における第２層１２の厚さは、例えば、０．３μｍ以上１．５μｍ以下とすることが好ましく、０．５μｍ以上１．２μｍ以下とすることがさらに好ましい。 By the steps so far, as shown in FIG. 9, the surface of the second layer 12 is exposed as the first surface 12a in the first region a1, and the surface of the first layer 11 is the third surface in the second region a2. It is exposed as 11a, and the surface of the first layer 11 is exposed as the fifth surface 11b on the outer peripheral portion. After this, their surfaces are roughened. For example, TMAH (tetramethylammonium hydroxide) is used to roughen their surfaces. The thickness of the first layer 11 after the roughening step is preferably, for example, 0.3 μm or more and 3 μm or less, and more preferably 1 μm or more and 2.5 μm or less. The thickness of the second layer 12 after the roughening step is preferably, for example, 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.2 μm or less.

図１０に示すように、第１領域ａ１の第２層１２の第１面１２ａに複数の第１凸部１０ａが形成され、第２領域ａ２の第１層１１の第３面１１ａ、および外周部の第１層１１の第５面１１ｂに複数の第２凸部１０ｂが形成される。 As shown in FIG. 10, a plurality of first convex portions 10a are formed on the first surface 12a of the second layer 12 of the first region a1, the third surface 11a of the first layer 11 of the second region a2, and the outer periphery thereof. A plurality of second convex portions 10b are formed on the fifth surface 11b of the first layer 11 of the portion.

ＡｌとＧａを含む窒化物半導体層に対するＴＭＡＨを使ったウェットエッチングにおいて、Ａｌ組成比が高いほどエッチングレートが高くなり、表面粗さが大きくなる傾向がある。第２層１２のＡｌ組成比は第１層１１のＡｌ組成比よりも高いため、第２層１２の第１面１２ａに形成される第１凸部１０ａの算術平均高さは、第１層１１の第３面１１ａおよび第５面１１ｂに形成される第２凸部１０ｂの算術平均高さよりも高くなる。活性層１４が積層され、光の取り出し効率に大きく寄与する第１領域ａ１の第１面１２ａの第１凸部１０ａを高くすることで、光取り出し効率を向上できる。 In wet etching using TMAH on a nitride semiconductor layer containing Al and Ga, the higher the Al composition ratio, the higher the etching rate and the larger the surface roughness tends to be. Since the Al composition ratio of the second layer 12 is higher than the Al composition ratio of the first layer 11, the arithmetic mean height of the first convex portion 10a formed on the first surface 12a of the second layer 12 is the first layer. It is higher than the arithmetic mean height of the second convex portion 10b formed on the third surface 11a and the fifth surface 11b of 11. The light extraction efficiency can be improved by increasing the first convex portion 10a of the first surface 12a of the first region a1 in which the active layers 14 are laminated and which greatly contributes to the light extraction efficiency.

一方で、第１層１１のＡｌ組成比は第２層１２のＡｌ組成比よりも低いため、ウェットエッチングにおける第１層１１のエッチングレートは、第２層１２よりも小さい傾向にある。第２領域ａ２の第３面１１ａのエッチング量を抑えることで、第２領域ａ２の第１層１１の膜厚の低減を抑えることができる。第１層１１は第２層１２よりもＡｌ組成比が低いため、第１導電部材４０のｎ側導通部４０ａが接続する第２領域ａ２の第１層１１の膜厚の低減を抑えることにより、前述したように、順方向電圧（駆動電圧）Ｖｆを低減することができる。 On the other hand, since the Al composition ratio of the first layer 11 is lower than the Al composition ratio of the second layer 12, the etching rate of the first layer 11 in wet etching tends to be smaller than that of the second layer 12. By suppressing the etching amount of the third surface 11a of the second region a2, it is possible to suppress the reduction of the film thickness of the first layer 11 of the second region a2. Since the first layer 11 has a lower Al composition ratio than the second layer 12, the reduction in the film thickness of the first layer 11 in the second region a2 to which the n-side conductive portion 40a of the first conductive member 40 is connected is suppressed. As described above, the forward voltage (driving voltage) Vf can be reduced.

第１導電型半導体層１０の表面を粗面化した後、第１導電型半導体層１０及び第２絶縁膜８２を覆う第４絶縁膜８４を形成する。その後、第１導電型半導体層１０より外側の領域に位置する第２絶縁膜８２の一部及び第４絶縁膜８４の一部を除去する。これにより、図２に示すように、第２絶縁膜８２から第２導電部材５０の一部がパッド接続部５０ｂとして露出され、パッド接続部５０ｂ上に第２パッド電極７２が形成される。また、第２絶縁膜８２から第３導電部材６０の一部が露出され、第３導電部材６０に第１パッド電極７１が形成される。 After roughening the surface of the first conductive semiconductor layer 10, a fourth insulating film 84 that covers the first conductive semiconductor layer 10 and the second insulating film 82 is formed. After that, a part of the second insulating film 82 and a part of the fourth insulating film 84 located in the region outside the first conductive semiconductor layer 10 are removed. As a result, as shown in FIG. 2, a part of the second conductive member 50 is exposed from the second insulating film 82 as the pad connecting portion 50b, and the second pad electrode 72 is formed on the pad connecting portion 50b. Further, a part of the third conductive member 60 is exposed from the second insulating film 82, and the first pad electrode 71 is formed on the third conductive member 60.

前述した図８に示す工程において、マスク９１を使って第１領域ａ１の第１層１１を除去して、第１領域ａ１の第２層１２の第１面１２ａを第１層１１から露出させた後、そのままマスク９１を用いて第２領域ａ２の第１層１１の第３面１１ａを覆った状態で、第１領域ａ１の第２層１２の第１面１２ａを例えばＴＭＡＨでエッチングすることで粗面化してもよい。 In the step shown in FIG. 8 described above, the mask 91 is used to remove the first layer 11 of the first region a1 to expose the first surface 12a of the second layer 12 of the first region a1 from the first layer 11. After that, the first surface 12a of the second layer 12 of the first region a1 is etched with, for example, TMAH while the mask 91 is used as it is to cover the third surface 11a of the first layer 11 of the second region a2. May be roughened with.

図１１に示すように、マスク９１で第２領域ａ２の第１層１１の第３面１１ａを覆った状態で粗面化することで、第１領域ａ１の第２層１２の第１面１２ａに複数の第１凸部１０ａが形成され、マスク９１で覆われている第２領域ａ２の第１層１１の第３面１１ａには凹凸が形成されない。第１領域ａ１の第１層１１の除去工程で使用するマスク９１を、第１領域ａ１の第２層１２の第１面１２ａの粗面化にも利用でき、工程を簡略化できる。また、このような工程により粗面化することで、図１２に示すように、第２領域ａ２の第１層１１の第３面１１ａがエッチングされず平坦面として残る。これにより、第２領域ａ２の第１層１１をより厚膜にでき、Ｖｆを低減することができる。 As shown in FIG. 11, by roughening the surface with the mask 91 covering the third surface 11a of the first layer 11 of the second region a2, the first surface 12a of the second layer 12 of the first region a1 is roughened. A plurality of first convex portions 10a are formed on the surface, and unevenness is not formed on the third surface 11a of the first layer 11 of the second region a2 covered with the mask 91. The mask 91 used in the removal step of the first layer 11 of the first region a1 can also be used for roughening the first surface 12a of the second layer 12 of the first region a1, and the step can be simplified. Further, by roughening the surface by such a step, as shown in FIG. 12, the third surface 11a of the first layer 11 of the second region a2 is not etched and remains as a flat surface. As a result, the first layer 11 of the second region a2 can be made thicker, and Vf can be reduced.

［第２実施形態］
図１３は、本発明の第２実施形態の発光素子の模式断面図である。第２実施形態の発光素子は、以下に説明する事項以外は図２に示す第１実施形態と同じ構造を備える。以下の説明においては、原則として第１実施形態との相違点のみを説明する。 [Second Embodiment]
FIG. 13 is a schematic cross-sectional view of the light emitting device according to the second embodiment of the present invention. The light emitting device of the second embodiment has the same structure as that of the first embodiment shown in FIG. 2 except for the matters described below. In the following description, in principle, only the differences from the first embodiment will be described.

本実施形態では、第１導電型半導体層１０は、第１層１１と第２層１２に加えて、さらに第３層１３を有する。第３層１３も、ＡｌとＧａを含む窒化物半導体層であり、例えばＡｌＧａＮ層である。第２層１２のＡｌ組成比は第１層１１のＡｌ組成比よりも高く、第３層１３のＡｌ組成比は第２層１２のＡｌ組成比よりも高い。第１層１１のＡｌ組成比と第２層１２のＡｌ組成比の差は１％以上４％以下であることが好ましい。第２層１２のＡｌ組成比と第３層１３のＡｌ組成比の差は０％より大きく４％以下であることが好ましい。例えば、第１層１１のＡｌ組成比は３％であり、第２層１２のＡｌ組成比は４％であり、第３層１３のＡｌ組成比は５％である。第１導電型半導体層１０による光吸収を抑制する観点から、第１層１１のＡｌ組成比と第２層１２のＡｌ組成比の差は２％以上であることが好ましい。例えば、第１層１１のＡｌ組成比は３％とし、第２層１２のＡｌ組成比は５％とし、第３層１３のＡｌ組成比は６％とする。 In the present embodiment, the first conductive semiconductor layer 10 further includes a third layer 13 in addition to the first layer 11 and the second layer 12. The third layer 13 is also a nitride semiconductor layer containing Al and Ga, for example, an AlGaN layer. The Al composition ratio of the second layer 12 is higher than the Al composition ratio of the first layer 11, and the Al composition ratio of the third layer 13 is higher than the Al composition ratio of the second layer 12. The difference between the Al composition ratio of the first layer 11 and the Al composition ratio of the second layer 12 is preferably 1% or more and 4% or less. The difference between the Al composition ratio of the second layer 12 and the Al composition ratio of the third layer 13 is preferably larger than 0% and 4% or less. For example, the Al composition ratio of the first layer 11 is 3%, the Al composition ratio of the second layer 12 is 4%, and the Al composition ratio of the third layer 13 is 5%. From the viewpoint of suppressing light absorption by the first conductive semiconductor layer 10, the difference between the Al composition ratio of the first layer 11 and the Al composition ratio of the second layer 12 is preferably 2% or more. For example, the Al composition ratio of the first layer 11 is 3%, the Al composition ratio of the second layer 12 is 5%, and the Al composition ratio of the third layer 13 is 6%.

本実施形態では、基板２００上に、例えば下地層２０１を介して、第１層１１、第２層１２、および第３層１３が順に形成される。第３層１３上に活性層１４が形成され、活性層１４上に第２導電型半導体層１５が形成される。 In the present embodiment, the first layer 11, the second layer 12, and the third layer 13 are sequentially formed on the substrate 200, for example, via the base layer 201. The active layer 14 is formed on the third layer 13, and the second conductive semiconductor layer 15 is formed on the active layer 14.

第１領域ａ１には、第１層１１が設けられず、第１層１１よりもＡｌ組成比が高い第２層１２と、第２層１２よりもＡｌ組成比が高い第３層１３が設けられている。第１領域ａ１に、第２層１２および第３層１３よりもＡｌ組成比が低く光吸収率が高い第１層１１を設けないことで、第１領域ａ１に第１層１１を設けた場合よりも光の取り出し効率を向上させることができる。さらに、第２層１２よりも活性層１４に近い層に、第２層１２よりもＡｌ組成比が高く光吸収率が低い第３層１３を設けることで、第１領域ａ１における光の吸収をより抑制することができる。 In the first region a1, the first layer 11 is not provided, and the second layer 12 having a higher Al composition ratio than the first layer 11 and the third layer 13 having a higher Al composition ratio than the second layer 12 are provided. Has been done. When the first layer 11 is provided in the first region a1 by not providing the first layer 11 having a lower Al composition ratio and a higher light absorption rate than the second layer 12 and the third layer 13 in the first region a1. It is possible to improve the light extraction efficiency. Further, by providing the third layer 13 having a higher Al composition ratio and a lower light absorption rate than the second layer 12 in the layer closer to the active layer 14 than the second layer 12, light absorption in the first region a1 can be achieved. It can be more suppressed.

また、第１領域ａ１に第１層１１を設けないため、第１領域ａ１の第１導電型半導体層１０の厚さは、第２領域ａ２の第１導電型半導体層１０の厚さよりも薄い。光取り出し効率に大きく影響する第１領域ａ１の第１導電型半導体層１０の薄膜化により、第１領域ａ１における光吸収を抑制し、光取り出し効率を向上させることができる。 Further, since the first layer 11 is not provided in the first region a1, the thickness of the first conductive semiconductor layer 10 in the first region a1 is thinner than the thickness of the first conductive semiconductor layer 10 in the second region a2. .. By thinning the first conductive semiconductor layer 10 in the first region a1 that greatly affects the light extraction efficiency, it is possible to suppress light absorption in the first region a1 and improve the light extraction efficiency.

第２領域ａ２には、第１層１１、第２層１２、および第３層１３が積層されている。第２領域ａ２には活性層１４および第２導電型半導体層１５が積層されていない。第２領域ａ２の第３層１３における支持基板１００側の面（第６面）１３ａは、第２導電型半導体層１５および活性層１４から露出している。第６面１３ａに、第１導電部材４０のｎ側導通部４０ａが接している。 The first layer 11, the second layer 12, and the third layer 13 are laminated on the second region a2. The active layer 14 and the second conductive semiconductor layer 15 are not laminated on the second region a2. The surface (sixth surface) 13a on the support substrate 100 side in the third layer 13 of the second region a2 is exposed from the second conductive semiconductor layer 15 and the active layer 14. The n-side conductive portion 40a of the first conductive member 40 is in contact with the sixth surface 13a.

第２領域ａ２においては、第２層１２および第３層１３よりもＡｌ組成比が低い第１層１１も設けることで、第２領域ａ２に第１層１１を設けない場合に比べて、順方向電圧（駆動電圧）Ｖｆを低減することができ、また、第２領域ａ２における電流集中を抑制できる。さらに、第２領域ａ２の第１導電型半導体層１０の厚さを、第１領域ａ１の第１導電型半導体層１０の厚さより厚くすることで、第２領域ａ２の抵抗を低減し、Ｖｆを低減できる。 In the second region a2, the first layer 11 having a lower Al composition ratio than the second layer 12 and the third layer 13 is also provided, so that the order is different from the case where the first layer 11 is not provided in the second region a2. The directional voltage (drive voltage) Vf can be reduced, and the current concentration in the second region a2 can be suppressed. Further, by making the thickness of the first conductive semiconductor layer 10 in the second region a2 thicker than the thickness of the first conductive semiconductor layer 10 in the first region a1, the resistance of the second region a2 is reduced and Vf. Can be reduced.

［第３実施形態］
図１４は、本発明の第３実施形態の発光素子の模式断面図である。図１４は、上述した図３と同様に、半導体積層体２０の一部を拡大した模式断面図である。 [Third Embodiment]
FIG. 14 is a schematic cross-sectional view of the light emitting device according to the third embodiment of the present invention. FIG. 14 is an enlarged schematic cross-sectional view of a part of the semiconductor laminate 20 as in FIG. 3 described above.

第３実施形態によれば、第１領域ａ１に第１層１１の一部１１ｃを設けている。第１領域ａ１に設けられた第１層１１の一部１１ｃの厚さは、第１領域ａ１に設けられた第２層１２の厚さよりも薄く、第２領域ａ２に設けられた第１層１１の厚さよりも薄い。第１領域ａ１に設けられた第１層１１の一部１１ｃの厚さとは、第１領域ａ１に設けられた第１層１１の一部１１ｃの最大厚さを意味する。 According to the third embodiment, a part 11c of the first layer 11 is provided in the first region a1. The thickness of a part 11c of the first layer 11 provided in the first region a1 is thinner than the thickness of the second layer 12 provided in the first region a1, and the thickness of the first layer provided in the second region a2. It is thinner than the thickness of 11. The thickness of the part 11c of the first layer 11 provided in the first region a1 means the maximum thickness of the part 11c of the first layer 11 provided in the first region a1.

第３実施形態では、前述した図７に示す工程において、第１層１１の表面を露出させた後、第１領域ａ１に設けられた第１層１１のすべてを除去するのではなく、第１領域ａ１に設けられた第１層１１の一部を除去する。そして、第２領域ａ２には第１領域ａ１に設けられた第１層１１よりも厚い第１層１１を残すようにする。第１層１１の一部を除去する工程において、第１領域ａ１に設けられた第１層１１をすべて除去せず、第１領域ａ１に第２領域ａ２よりも薄い第１層１１と第２層１２を残す。その後、第１領域ａ１及び第２領域ａ２を例えばＴＭＡＨでエッチングすることで粗面化する。 In the third embodiment, in the step shown in FIG. 7 described above, after the surface of the first layer 11 is exposed, the first layer 11 provided in the first region a1 is not completely removed. A part of the first layer 11 provided in the region a1 is removed. Then, the first layer 11 thicker than the first layer 11 provided in the first region a1 is left in the second region a2. In the step of removing a part of the first layer 11, the first layer 11 and the second layer 11 provided in the first region a1 are not completely removed, and the first region a1 is thinner than the second region a2. Leave layer 12. Then, the first region a1 and the second region a2 are roughened by etching with, for example, TMAH.

図１４に示す例では、第１領域ａ１の第２層１２の表面に設けられた錐体形状の第１凸部１０ａの頂部に第１層１１の一部１１ｃが設けられている。第１層１１の一部１１ｃの厚さは、第２層１２の第１凸部１０ａの高さよりも小さい。第３実施形態において、第１凸部１０ａは図１４の断面視において台形で表され、第１凸部１０ａの高さは、その台形の高さを表す。第１層１１の一部１１ｃは図１４の断面視において三角形で表され、第１層１１の一部１１ｃの厚さは、その三角形の高さを表す。 In the example shown in FIG. 14, a part 11c of the first layer 11 is provided on the top of the cone-shaped first convex portion 10a provided on the surface of the second layer 12 of the first region a1. The thickness of the part 11c of the first layer 11 is smaller than the height of the first convex portion 10a of the second layer 12. In the third embodiment, the first convex portion 10a is represented by a trapezoid in the cross-sectional view of FIG. 14, and the height of the first convex portion 10a represents the height of the trapezoid. The part 11c of the first layer 11 is represented by a triangle in the cross-sectional view of FIG. 14, and the thickness of the part 11c of the first layer 11 represents the height of the triangle.

第１層１１は第２層１２よりもＡｌ組成比が低く光吸収率が高いが、第１領域ａ１に設ける第１層１１を、第２層１２よりも薄く、且つ第２領域ａ２の第１層１１よりも薄い一部１１ｃに制限することで、第１領域ａ１の第１層１１による光吸収が光取り出し効率にほとんど影響しないようにできる。 The first layer 11 has a lower Al composition ratio and a higher light absorption rate than the second layer 12, but the first layer 11 provided in the first region a1 is thinner than the second layer 12 and is the second layer of the second region a2. By limiting to a part 11c thinner than the first layer 11, it is possible to prevent the light absorption by the first layer 11 of the first region a1 from affecting the light extraction efficiency.

次に、図１６～図１８を参照して、第１実施形態の他の変形例の発光素子の製造方法について説明する。なお、この変形例は、第２実施形態及び第３実施形態にも適用することができる。 Next, with reference to FIGS. 16 to 18, a method for manufacturing a light emitting element according to another modification of the first embodiment will be described. It should be noted that this modification can also be applied to the second embodiment and the third embodiment.

図４を参照して前述したように基板２００上に半導体積層２０を形成した後、図１６に示すように、第２導電型半導体層１５の表面の一部を改質させる工程を行ってもよい。図１６及び以降の図において、第２導電型半導体層１５のドットハッチングで表される領域の表面を改質させる。例えば、第２導電型半導体層１５の表面のうち、前述した第１導電型半導体層１０の第１領域ａ１上に位置することになる第２導電型半導体層１５の表面の一部にマスク５００を形成する。そして、例えば、酸素を含む雰囲気において、マスク５００から露出する第２導電型半導体層１５の表面をプラズマ処理する。 After forming the semiconductor laminate 20 on the substrate 200 as described above with reference to FIG. 4, a step of modifying a part of the surface of the second conductive semiconductor layer 15 may be performed as shown in FIG. good. In FIG. 16 and the following figures, the surface of the region represented by dot hatching of the second conductive semiconductor layer 15 is modified. For example, of the surface of the second conductive semiconductor layer 15, a mask 500 is applied to a part of the surface of the second conductive semiconductor layer 15 which is located on the first region a1 of the first conductive semiconductor layer 10 described above. To form. Then, for example, in an atmosphere containing oxygen, the surface of the second conductive semiconductor layer 15 exposed from the mask 500 is plasma-treated.

第２導電型半導体層１５の表面のうち改質された第２導電型半導体層１５の表面は、改質されていない第２導電型半導体層１５の表面よりも抵抗が高くなる。すなわち、第２導電型半導体層１５の表面に、低抵抗部（非改質部）１５ａと、低抵抗部１５ａよりも抵抗率が高い高抵抗部（改質部）１５ｂとが形成される。 Of the surfaces of the second conductive semiconductor layer 15, the surface of the modified second conductive semiconductor layer 15 has higher resistance than the surface of the unmodified second conductive semiconductor layer 15. That is, a low resistance portion (non-modifying portion) 15a and a high resistance portion (modified portion) 15b having a resistivity higher than that of the low resistance portion 15a are formed on the surface of the second conductive semiconductor layer 15.

その後、図１７に示すように、低抵抗部１５ａと高抵抗部１５ｂに跨がるように、第２導電型半導体層１５の表面上に反射電極３０を形成する。反射電極３０は、低抵抗部１５ａの全面に接する。反射電極３０は、高抵抗部１５ｂの一部に接する。反射電極３０が低抵抗部１５ａに接する面積は、反射電極３０が高抵抗部１５ｂに接する面積よりも大きい。反射電極３０を形成した後、反射電極３０及び第２導電型半導体層１５の表面を覆うように、第１絶縁膜８１を形成する。 After that, as shown in FIG. 17, the reflective electrode 30 is formed on the surface of the second conductive semiconductor layer 15 so as to straddle the low resistance portion 15a and the high resistance portion 15b. The reflective electrode 30 is in contact with the entire surface of the low resistance portion 15a. The reflective electrode 30 is in contact with a part of the high resistance portion 15b. The area where the reflective electrode 30 is in contact with the low resistance portion 15a is larger than the area where the reflective electrode 30 is in contact with the high resistance portion 15b. After forming the reflective electrode 30, the first insulating film 81 is formed so as to cover the surfaces of the reflective electrode 30 and the second conductive semiconductor layer 15.

その後、図１８に示すように、第１絶縁膜８１の一部、第２導電型半導体層１５の一部、及び活性層１４の一部を除去する。これにより、第２導電型半導体層１５及び活性層１４から、第１導電型半導体層１０の第２層１２の一部が露出される。除去されずに残った第２導電型半導体層１５の表面は、低抵抗部１５ａと高抵抗部１５ｂとを含む。 After that, as shown in FIG. 18, a part of the first insulating film 81, a part of the second conductive semiconductor layer 15, and a part of the active layer 14 are removed. As a result, a part of the second layer 12 of the first conductive semiconductor layer 10 is exposed from the second conductive semiconductor layer 15 and the active layer 14. The surface of the second conductive semiconductor layer 15 that remains without being removed includes a low resistance portion 15a and a high resistance portion 15b.

その後、前述した図６以降の工程が続けられ、図１９に示す発光素子が得られる。第１導電型半導体層１０の第１領域ａ１に積層された第２導電型半導体層１５の表面は、低抵抗部１５ａと高抵抗部１５ｂとを含む。高抵抗部１５ｂは、低抵抗部１５ａよりも第２領域ａ２の近くに位置する高抵抗部１５ｂｃを含む。また、高抵抗部１５ｂは、低抵抗部１５ａよりも、第１導電型半導体層１０の外周部の近くに位置する高抵抗部１５ｂａを含む。高抵抗部１５ｂの電流密度は低抵抗部１５ａの電流密度よりも低くなり、高抵抗部１５ｂが設けられた領域の活性層１４よりも低抵抗部１５ａが設けられた領域の活性層１４が強く発光しやすくなる。 After that, the steps after FIG. 6 described above are continued, and the light emitting element shown in FIG. 19 is obtained. The surface of the second conductive semiconductor layer 15 laminated on the first region a1 of the first conductive semiconductor layer 10 includes a low resistance portion 15a and a high resistance portion 15b. The high resistance portion 15b includes a high resistance portion 15bc located closer to the second region a2 than the low resistance portion 15a. Further, the high resistance portion 15b includes a high resistance portion 15ba located closer to the outer peripheral portion of the first conductive semiconductor layer 10 than the low resistance portion 15a. The current density of the high resistance portion 15b is lower than the current density of the low resistance portion 15a, and the active layer 14 in the region provided with the low resistance portion 15a is stronger than the active layer 14 in the region provided with the high resistance portion 15b. It becomes easier to emit light.

第１導電型半導体層１０において第２層１２よりも光吸収率が高い第１層１１が設けられた第２領域１１ａ及び外周部に近い位置に高抵抗部１５ｂを位置させることで、第１層１１に近い領域の発光を少なくして、第１層１１による光吸収を抑制することができる。反射電極３０は高抵抗部１５ｂにも接しているため、反射電極３０の面積を維持しつつ、第１層１１による光吸収を抑制し、光取り出し効率を向上させることができる。 By locating the high resistance portion 15b at a position close to the second region 11a and the outer peripheral portion provided with the first layer 11 having a higher light absorption rate than the second layer 12 in the first conductive semiconductor layer 10, the first layer is formed. It is possible to reduce the light emission in the region close to the layer 11 and suppress the light absorption by the first layer 11. Since the reflective electrode 30 is also in contact with the high resistance portion 15b, it is possible to suppress light absorption by the first layer 11 and improve the light extraction efficiency while maintaining the area of the reflective electrode 30.

図１９の断面において、反射電極３０が高抵抗部１５ｂに接する幅は、例えば、３μｍ以上２５μｍ以下であることが好ましく、５μｍ以上２０μｍ以下であることがより好ましい。 In the cross section of FIG. 19, the width of the reflective electrode 30 in contact with the high resistance portion 15b is preferably, for example, 3 μm or more and 25 μm or less, and more preferably 5 μm or more and 20 μm or less.

図１９の断面において、高抵抗部１５ｂのうち、第１導電型半導体層１０の外周部に近い側に位置する高抵抗部１５ｂａの幅は、第２領域ａ２に近い側に位置する高抵抗部１５ｂｃの幅より大きいことが好ましい。第２領域ａ２よりも第１層１１が広範囲に配置されている外周部側の高抵抗部ｂａの幅を高抵抗部１５ｂｃよりも大きくすることで、第１層１１による光吸収の抑制効果を高くできる。 In the cross section of FIG. 19, the width of the high resistance portion 15ba located on the side close to the outer peripheral portion of the first conductive semiconductor layer 10 among the high resistance portions 15b is the high resistance portion located on the side close to the second region a2. It is preferably larger than the width of 15 bc. By making the width of the high resistance portion ba on the outer peripheral side where the first layer 11 is arranged in a wider range than the second region a2 than the high resistance portion 15bc, the effect of suppressing light absorption by the first layer 11 can be obtained. Can be high.

以上、具体例を参照しつつ、本発明の実施形態について説明した。しかし、本発明は、これらの具体例に限定されるものではない。本発明の上述した実施形態を基にして、当業者が適宜設計変更して実施し得る全ての形態も、本発明の要旨を包含する限り、本発明の範囲に属する。その他、本発明の思想の範疇において、当業者であれば、各種の変更例及び修正例に想到し得るものであり、それら変更例及び修正例についても本発明の範囲に属するものである。 The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. All embodiments that can be implemented by those skilled in the art with appropriate design changes based on the above-described embodiments of the present invention also belong to the scope of the present invention as long as the gist of the present invention is included. In addition, in the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and these modified examples and modified examples also belong to the scope of the present invention.

１…発光素子、１０…第１導電型半導体層、１０ａ…第１凸部、１０ｂ…第２凸部、１１…第１層、１１ａ…第３面、１１ｂ…第５面、１２…第２層、１２ａ…第１面、１２ｂ…第２面、１２ｃ…第４面、１３…第３層、１３ａ…第６面、１４…活性層、１５…第２導電型半導体層、２０…半導体積層体、３０…反射電極、４０…第１導電部材、５０…第２導電部材、６０…第３導電部材、７１…第１パッド電極、７２…第２パッド電極、８１…第１絶縁膜、８２…第２絶縁膜、８３…第３絶縁膜、８４…第４絶縁膜、１００…支持基板、１０１…接合層、２００…基板、ａ１…第１領域、ａ２…第２領域 1 ... light emitting element, 10 ... first conductive semiconductor layer, 10a ... first convex portion, 10b ... second convex portion, 11 ... first layer, 11a ... third surface, 11b ... fifth surface, 12 ... second surface. Layers, 12a ... 1st surface, 12b ... 2nd surface, 12c ... 4th surface, 13 ... 3rd layer, 13a ... 6th surface, 14 ... active layer, 15 ... 2nd conductive semiconductor layer, 20 ... semiconductor lamination Body, 30 ... Reflective electrode, 40 ... First conductive member, 50 ... Second conductive member, 60 ... Third conductive member, 71 ... First pad electrode, 72 ... Second pad electrode, 81 ... First insulating film, 82 ... 2nd insulating film, 83 ... 3rd insulating film, 84 ... 4th insulating film, 100 ... Support substrate, 101 ... Bonding layer, 200 ... Substrate, a1 ... 1st region, a2 ... 2nd region

Claims (14)

第１導電型半導体層と、第２導電型半導体層と、前記第１導電型半導体層と前記第２導電型半導体層との間に設けられた活性層とを有する半導体積層体と、
前記第１導電型半導体層と電気的に接続された第１導電部材と、
前記第２導電型半導体層と電気的に接続された第２導電部材と、
を備え、
第１導電型半導体層は、ＡｌとＧａを含む窒化物半導体層であり、第１層と第２層とを有し、前記第１層のＡｌ組成比は前記第２層のＡｌ組成比よりも低く、
前記第１導電型半導体層は、前記第２導電型半導体層および前記活性層が積層された第１領域と、前記第２導電型半導体層および前記活性層から露出し、前記第１導電部材と接続される第２領域とを有し、
前記第１領域に設けられた前記第１層の厚さは、前記第２領域に設けられた前記第１層の厚さよりも薄い、または、前記第１領域には前記第１層が設けられていない発光素子。 A semiconductor laminate having a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer provided between the first conductive semiconductor layer and the second conductive semiconductor layer.
A first conductive member electrically connected to the first conductive semiconductor layer,
A second conductive member electrically connected to the second conductive semiconductor layer,
Equipped with
The first conductive semiconductor layer is a nitride semiconductor layer containing Al and Ga, has a first layer and a second layer, and the Al composition ratio of the first layer is higher than the Al composition ratio of the second layer. Also low,
The first conductive semiconductor layer is exposed from the first region in which the second conductive semiconductor layer and the active layer are laminated, the second conductive semiconductor layer and the active layer, and the first conductive member. Has a second area to be connected
The thickness of the first layer provided in the first region is thinner than the thickness of the first layer provided in the second region, or the first layer is provided in the first region. Light emitting element that is not. 前記第２領域に設けられた前記第２層の厚さは、前記第２領域に設けられた前記第１層の厚さよりも薄い請求項１記載の発光素子。 The light emitting device according to claim 1, wherein the thickness of the second layer provided in the second region is thinner than the thickness of the first layer provided in the second region. 前記第２領域に設けられた前記第２層の厚さは、前記第２領域に設けられた前記第１層の厚さの８０％以下である請求項１または２に記載の発光素子。 The light emitting device according to claim 1 or 2, wherein the thickness of the second layer provided in the second region is 80% or less of the thickness of the first layer provided in the second region. 前記第１領域の前記第２層の表面に複数の第１凸部が形成され、前記第２領域の前記第１層の表面に複数の第２凸部が形成され、
前記第１凸部の算術平均高さは、前記第２凸部の算術平均高さよりも高い請求項１～３のいずれか１つに記載の発光素子。 A plurality of first convex portions are formed on the surface of the second layer of the first region, and a plurality of second convex portions are formed on the surface of the first layer of the second region.
The light emitting element according to any one of claims 1 to 3, wherein the arithmetic average height of the first convex portion is higher than the arithmetic average height of the second convex portion. 前記活性層からの光のピーク波長は、４００ｎｍ以下である請求項１～４のいずれか１つに記載の発光素子。 The light emitting device according to any one of claims 1 to 4, wherein the peak wavelength of the light from the active layer is 400 nm or less. 前記第２導電部材は、前記第１領域に積層された前記第２導電型半導体層に接している請求項１～５のいずれか１つに記載の発光素子。 The light emitting device according to any one of claims 1 to 5, wherein the second conductive member is in contact with the second conductive semiconductor layer laminated in the first region. 基板上に、第１導電型半導体層と、前記第１導電型半導体層上に設けられた活性層と、前記活性層上に設けられた第２導電型半導体層とを含む半導体積層体を形成する工程であって、前記第１導電型半導体層は、ＡｌとＧａを含む窒化物半導体層であり、前記基板上に設けられた第１層と、前記第１層上に設けられた第２層とを有し、前記第１層のＡｌ組成比は前記第２層のＡｌ組成比よりも低い、前記半導体積層体を形成する工程と、
前記第２導電型半導体層の一部および前記活性層の一部を除去し、前記第２導電型半導体層および前記活性層から前記第１導電型半導体層の一部を露出させ、前記第１導電型半導体層に、前記第２導電型半導体層および前記活性層が除去されずに残っている第１領域と、前記第２導電型半導体層および前記活性層から露出された前記第１導電型半導体層の前記一部を含む第２領域とを形成する工程と、
前記第１領域と前記第２領域を形成した後、前記基板を除去し、前記第１導電型半導体層の前記第１層の表面を露出させる工程と、
前記第１層の表面を露出させた後、前記第１領域に設けられた前記第１層の少なくとも一部を除去し、前記第２領域に、前記第１領域に設けられた第１層よりも厚い第１層を残す、または、前記第１領域に設けられた第２層を前記第１層から露出させる工程と、
を備える発光素子の製造方法。 A semiconductor laminate including a first conductive semiconductor layer, an active layer provided on the first conductive semiconductor layer, and a second conductive semiconductor layer provided on the active layer is formed on a substrate. The first conductive semiconductor layer is a nitride semiconductor layer containing Al and Ga, and is a first layer provided on the substrate and a second layer provided on the first layer. A step of forming the semiconductor laminate, which has a layer and the Al composition ratio of the first layer is lower than the Al composition ratio of the second layer.
A part of the second conductive semiconductor layer and a part of the active layer are removed, and a part of the first conductive semiconductor layer is exposed from the second conductive semiconductor layer and the active layer to expose the first conductive semiconductor layer. The first region in which the second conductive semiconductor layer and the active layer remain without being removed from the conductive semiconductor layer, and the first conductive type exposed from the second conductive semiconductor layer and the active layer. The step of forming the second region including the part of the semiconductor layer, and
After forming the first region and the second region, the substrate is removed to expose the surface of the first layer of the first conductive semiconductor layer.
After exposing the surface of the first layer, at least a part of the first layer provided in the first region is removed, and the second region is formed from the first layer provided in the first region. A step of leaving a thick first layer or exposing a second layer provided in the first region from the first layer.
A method for manufacturing a light emitting device. 前記第１領域に設けられた前記第１層の少なくとも一部を除去した後、前記第１領域の前記第２層の表面に複数の第１凸部を形成し、前記第２領域の前記第１層の表面に複数の第２凸部を形成する工程をさらに備え、
前記第１凸部の算術平均高さは、前記第２凸部の算術平均高さよりも高い請求項７記載の発光素子の製造方法。 After removing at least a part of the first layer provided in the first region, a plurality of first convex portions are formed on the surface of the second layer of the first region, and the first convex portion of the second region is formed. Further provided with a step of forming a plurality of second convex portions on the surface of one layer,
The method for manufacturing a light emitting element according to claim 7, wherein the arithmetic average height of the first convex portion is higher than the arithmetic average height of the second convex portion. 前記第１領域に設けられた前記第１層の少なくとも一部を除去した後、前記第１領域の前記第２層の表面に複数の第１凸部を形成する工程をさらに備え、
前記第１領域に設けられた前記第１層の少なくとも一部を除去する工程において、前記第２領域の前記第１層の表面をマスクで覆った状態で、前記第１領域の前記第１層の少なくとも一部を除去し、
前記マスクを用いて、前記第１領域をエッチングして、複数の前記第１凸部を形成する請求項７記載の発光素子の製造方法。 A step of forming a plurality of first convex portions on the surface of the second layer of the first region after removing at least a part of the first layer provided in the first region is further provided.
In the step of removing at least a part of the first layer provided in the first region, the first layer of the first region is covered with a mask while the surface of the first layer of the second region is covered with a mask. Remove at least part of
The method for manufacturing a light emitting element according to claim 7, wherein the first region is etched by using the mask to form a plurality of the first convex portions. 前記半導体積層体を形成する工程において、前記第２層を、前記第１層よりも薄く形成する請求項７～９のいずれか１つに記載の発光素子の製造方法。 The method for manufacturing a light emitting device according to any one of claims 7 to 9, wherein in the step of forming the semiconductor laminate, the second layer is formed thinner than the first layer. 前記半導体積層体を形成する工程において、前記第２層の厚さを、前記第１層の厚さの５０％以下として形成する請求項７～１０のいずれか１つに記載の発光素子の製造方法。 The manufacture of a light emitting device according to any one of claims 7 to 10, wherein in the step of forming the semiconductor laminate, the thickness of the second layer is 50% or less of the thickness of the first layer. Method. 前記活性層からの光のピーク波長は、４００ｎｍ以下である請求項７～１１のいずれか１つに記載の発光素子の製造方法。 The method for manufacturing a light emitting device according to any one of claims 7 to 11, wherein the peak wavelength of light from the active layer is 400 nm or less. 前記第１導電型半導体層の前記第１領域上の第２導電型半導体層の表面に、低抵抗部と、前記低抵抗部よりも抵抗率が高く、前記低抵抗部よりも前記第２領域の近くに位置する高抵抗部とを形成する工程と、
前記低抵抗部に接する面積が前記高抵抗部に接する面積よりも大きくなるように、前記第２導電型半導体層の前記表面上に電極を形成する工程と、
を備える請求項７～１２のいずれか１つに記載の発光素子の製造方法。 On the surface of the second conductive semiconductor layer on the first region of the first conductive semiconductor layer, a low resistance portion, a resistivity higher than the low resistance portion, and the second region higher than the low resistance portion. The process of forming a high resistance part located near the
A step of forming an electrode on the surface of the second conductive semiconductor layer so that the area in contact with the low resistance portion is larger than the area in contact with the high resistance portion.
The method for manufacturing a light emitting element according to any one of claims 7 to 12. 前記第２導電型半導体層の前記表面をプラズマ処理することで、前記高抵抗部を形成する請求項１３記載の発光素子の製造方法。 The method for manufacturing a light emitting device according to claim 13, wherein the high resistance portion is formed by plasma-treating the surface of the second conductive semiconductor layer.
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