JP2021524158A - 三次元メモリ素子 - Google Patents
三次元メモリ素子 Download PDFInfo
- Publication number
- JP2021524158A JP2021524158A JP2020564140A JP2020564140A JP2021524158A JP 2021524158 A JP2021524158 A JP 2021524158A JP 2020564140 A JP2020564140 A JP 2020564140A JP 2020564140 A JP2020564140 A JP 2020564140A JP 2021524158 A JP2021524158 A JP 2021524158A
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- Prior art keywords
- memory
- layer
- contact
- conductor
- interconnect layer
- Prior art date
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- 230000015654 memory Effects 0.000 title claims abstract description 329
- 239000004020 conductor Substances 0.000 claims abstract description 104
- 230000002093 peripheral effect Effects 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 239000004065 semiconductor Substances 0.000 claims description 86
- 230000005641 tunneling Effects 0.000 claims description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 17
- 238000003860 storage Methods 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 369
- 238000000034 method Methods 0.000 description 61
- 229910052710 silicon Inorganic materials 0.000 description 59
- 239000010703 silicon Substances 0.000 description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 48
- 230000008569 process Effects 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 27
- 239000003989 dielectric material Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- -1 silicon nitrides Chemical class 0.000 description 12
- 238000000427 thin-film deposition Methods 0.000 description 12
- 238000001312 dry etching Methods 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 238000001039 wet etching Methods 0.000 description 11
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 238000000926 separation method Methods 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C13/0069—Writing or programming circuits or methods
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
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- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- H10N70/011—Manufacture or treatment of multistable switching devices
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- Non-Volatile Memory (AREA)
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Abstract
Description
102 基板
104 トランジスタ
106 周辺相互接続層
108 横方向相互接続線
110 垂直方向相互接続アクセス(ビア)コンタクト
112 ボンディングコンタクト
114 NANDメモリストリング
116 導体層
118 誘電体層
120 メモリスタック
122 階段構造
124 半導体チャネル
126 トンネリング層
128 貯蔵層
130 半導体層
132 半導体プラグ
134 ゲート線スリット(GLS)
136 ワード線ビアコンタクト
138 ビット線ビアコンタクト
140 ソース線ビアコンタクト
142 アレイ相互接続層
144 相互接続線
146 ビアコンタクト
148 ボンディングコンタクト
150 BEOL相互接続層
152 相互接続線
154 ビアコンタクト
156 コンタクトパッド
158 ボンディング界面
160 メモリアレイ素子チップ
162 周辺素子チップ
202 シリコン基板
204 トランジスタ
206 周辺相互接続層
208 相互接続線
210 ビアコンタクト
212 ボンディングコンタクト
214 ボンディングコンタクト
302 シリコン基板
304 分離領域
306 シリコンプラグ
308 誘電体スタック
310 第1の誘電体層
312 第2の誘電体層、犠牲層
314 NANDメモリストリング
316 半導体チャネル
318 トンネリング層
320 貯蔵層
321 ビット線ビアコンタクト
322 アレイ相互接続層
324 相互接続線
326 ビアコンタクト
328 ボンディングコンタクト
402 ボンディング界面
404 単結晶シリコン層
406 階段構造
408 GLS
410 導体層
412 メモリスタック
414 階段構造
416 ILD層
418 ソース線ビアコンタクト
420 ワード線ビアコンタクト
422 BEOL相互接続層
424 相互接続線
426 ビアコンタクト
428 コンタクトパッド
500、600、700 方法
Claims (25)
- 基板と、
前記基板に接して配設される周辺素子と、
前記周辺素子の上に配設され、複数の導体/誘電体層ペアを含むメモリスタックと、
複数のメモリストリングであって、前記メモリストリングがそれぞれ、前記メモリスタックの中を垂直に延び、ドレイン選択ゲート、および前記ドレイン選択ゲートの上にソース選択ゲートを含む、複数のメモリストリングと
を備え、
前記基板から離れる垂直方向に沿う前記メモリスタックの階段構造における前記導体/誘電体層ペアの縁部が、前記メモリストリングに向かって横方向にずらして配列される、
三次元(3D)メモリ素子。 - 前記メモリストリングの上に配設される第1の相互接続層をさらに備える、請求項1に記載の3Dメモリ素子。
- 前記メモリストリングと前記周辺素子との間にボンディング界面をさらに備える、請求項1または2に記載の3Dメモリ素子。
- 前記ボンディング界面と前記周辺素子との間に第2の相互接続層、および前記ボンディング界面と前記メモリストリングとの間に第3の相互接続層をさらに備える、請求項3に記載の3Dメモリ素子。
- 複数の第1のビアコンタクトをさらに備え、前記第1のビアコンタクトがそれぞれ、前記導体/誘電体層ペアのうちの1つの中の導体層と接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、請求項2に記載の3Dメモリ素子。
- それぞれ、前記複数のメモリストリングの下に、前記複数のメモリストリングと接触している複数の第2のビアコンタクトをさらに備える、請求項1から5のいずれか一項に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、前記メモリストリングの上側端部に半導体プラグを備える、請求項1から6のいずれか一項に記載の3Dメモリ素子。
- 前記半導体プラグが、単結晶シリコンを含む、請求項7に記載の3Dメモリ素子。
- 複数の第3のビアコンタクトをさらに備え、前記第3のビアコンタクトがそれぞれ、前記半導体プラグのうちの1つと接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、請求項7または8に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、
前記導体/誘電体層ペアの中を垂直に延びる半導体チャネル、
前記導体/誘電体層ペアと前記半導体チャネルとの間のトンネリング層、および
前記トンネリング層と前記導体/誘電体層ペアとの間の貯蔵層
を備える、請求項1から9のいずれか一項に記載の3Dメモリ素子。 - 基板と、
前記基板に接して配設される周辺素子と、
前記周辺素子の上に配設され、複数の導体/誘電体層ペアを含むメモリスタックと、
複数のメモリストリングであって、前記メモリストリングがそれぞれ、前記メモリスタックの中を垂直に延びている、複数のメモリストリングと、
前記メモリストリングの上に配設される第1の相互接続層、および前記メモリストリングの下に配設される第2の相互接続層と、
複数の第1のビアコンタクトであって、前記第1のビアコンタクトがそれぞれ、前記導体/誘電体層ペアのうちの1つの中の導体層と接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、複数の第1のビアコンタクトと、
複数の第2のビアコンタクトであって、前記第2のビアコンタクトがそれぞれ、前記第2の相互接続層と接触している下側端部、および前記メモリストリングのうちの1つと接触している上側端部を含む、複数の第2のビアコンタクトと
を備える、三次元(3D)メモリ素子。 - 前記基板から離れる垂直方向に沿う前記メモリスタックの階段構造における前記導体/誘電体層ペアの縁部が、前記メモリストリングに向かって横方向にずらして配列される、請求項11に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、ドレイン選択ゲート、および前記ドレイン選択ゲートの上にソース選択ゲートを備える、請求項11または12に記載の3Dメモリ素子。
- 前記第2の相互接続層と前記周辺素子との間にボンディング界面をさらに備える、請求項11から13のいずれか一項に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、前記メモリストリングの上側端部に半導体プラグを備える、請求項11から14のいずれか一項に記載の3Dメモリ素子。
- 前記半導体プラグが、単結晶シリコンを含む、請求項15に記載の3Dメモリ素子。
- 複数の第3のビアコンタクトをさらに備え、前記第3のビアコンタクトがそれぞれ、前記半導体プラグのうちの1つと接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、請求項15または16に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、
前記導体/誘電体層ペアの中を垂直に延びる半導体チャネル、
前記導体/誘電体層ペアと前記半導体チャネルとの間のトンネリング層、および
前記トンネリング層と前記導体/誘電体層ペアとの間の貯蔵層
を備える、請求項11から17のいずれか一項に記載の3Dメモリ素子。 - 第1の半導体構造であって、
複数のメモリストリングであって、前記メモリストリングがそれぞれ、垂直に延び、前記メモリストリングの上側端部に半導体プラグを含む、複数のメモリストリング、
前記メモリストリングの上に配設される第1の相互接続層、および前記メモリストリングの下に配設される第2の相互接続層、ならびに
複数の第1のビアコンタクトであって、前記第1のビアコンタクトがそれぞれ、前記半導体プラグのうちの1つと接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、複数の第1のビアコンタクト
を含む、第1の半導体構造と、
第2の半導体構造であって、
基板、
前記基板に接して配設される周辺素子、および
前記周辺素子の上に配設される第3の相互接続層
を含む、第2の半導体構造と、
前記第1の半導体構造と前記第2の半導体構造との間のボンディング界面であって、前記第2の相互接続層が、前記ボンディング界面において前記第3の相互接続層に接触する、ボンディング界面と
を備える、三次元(3D)メモリ素子。 - 前記半導体プラグが、単結晶シリコンを含む、請求項19に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、ドレイン選択ゲート、および前記ドレイン選択ゲートの上にソース選択ゲートをさらに備える、請求項19または20に記載の3Dメモリ素子。
- 前記メモリストリングが内部を垂直に延びるメモリスタックと、複数の導体/誘電体層ペアとをさらに備え、前記基板から離れる垂直方向に沿う前記メモリスタックの階段構造における前記導体/誘電体層ペアの縁部が、前記メモリストリングに向かって横方向にずらして配列される、請求項19から21のいずれか一項に記載の3Dメモリ素子。
- 前記メモリストリングがそれぞれ、
前記導体/誘電体層ペアの中を垂直に延びる半導体チャネル、
前記導体/誘電体層ペアと前記半導体チャネルとの間のトンネリング層、および
前記トンネリング層と前記導体/誘電体層ペアとの間の貯蔵層
を備える、請求項22に記載の3Dメモリ素子。 - 複数の第2のビアコンタクトをさらに備え、前記第2のビアコンタクトがそれぞれ、前記導体/誘電体層ペアのうちの1つの中の導体層と接触している下側端部、および前記第1の相互接続層と接触している上側端部を含む、請求項22また23に記載の3Dメモリ素子。
- 複数の第3のビアコンタクトをさらに備え、前記第3のビアコンタクトがそれぞれ、前記第2の相互接続層と接触している下側端部、および前記メモリストリングのうちの1つと接触している上側端部を含む、請求項19から24のいずれか一項に記載の3Dメモリ素子。
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