JP2021009869A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2021009869A JP2021009869A JP2019121501A JP2019121501A JP2021009869A JP 2021009869 A JP2021009869 A JP 2021009869A JP 2019121501 A JP2019121501 A JP 2019121501A JP 2019121501 A JP2019121501 A JP 2019121501A JP 2021009869 A JP2021009869 A JP 2021009869A
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- semiconductor device
- insulating layer
- conductor
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- semiconductor
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Abstract
Description
本発明の第二の態様によると、半導体装置は、開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する複数の半導体素子と、前記各半導体素子の前記表面電極に接合された中継導体と、前記各表面電極と前記各中継導体を接合する接合層と、前記各第一絶縁層の少なくとも一部を覆い、少なくとも前記各接合層の周囲に接して設けられた第二絶縁層と、前記各中継導体を接続する導体と、を備える。
本発明の第三の態様によると、半導体装置の製造方法は、開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子を準備することと、前記表面電極と中継導体とを接合層により接合することと、前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接する第二絶縁層を設けることと、前記中継導体に導体を接続することと、前記導体と前記第二絶縁層との間に封止樹脂を充填することと、を含む。
図面において示す各構成要素の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面に開示された位置、大きさ、形状、範囲などに限定されない。
以下、図1〜図3を参照して、本発明の第1の実施形態を説明する。
図1は、本発明の半導体装置の第1の実施形態の断面図である。
半導体装置100は、半導体素子10を備えている。半導体素子10は、例えば、SiC(シリコンカーバイト)MOS FET(Metal-Oxide-Semiconductor Field effect
transistor)である。半導体素子10は、半導体基板11と、ソース電極12と、ドレイン電極13と、内部配線14と、第一絶縁層15を有する。なお、図1には、図示しないが、半導体素子10は、ゲート電極17(図7参照)を有する。半導体装置100は、半導体素子10と、中継導体21と、表面側導体22と、裏面側導体23と、第二絶縁層31と、封止樹脂32を有する。
封止樹脂32としては、エポキシ樹脂等を用いることができる。封止樹脂32による封止は、トランスファーモールド等のモールド法等が適しているが、ポッティング法や、シルク印刷、シーリング印刷、インクジェット印刷、熱転写印刷等の印刷法を用いてもよい。
次に、上記実施形態の半導体装置100における、ボイドの存在に伴う封止樹脂の劣化抑制作用について説明する。
図5(A)に図示される比較例の半導体装置100Rは、本実施形態の半導体装置100の中継導体21を有していない。
半導体装置100Rでは、表面側導体22Rは、ソース電極12の、第一絶縁層15の開口部15aから露出した部分に対向する突出部25を有している。突出部25は、表面側導体22Rと一体成形されている。すなわち、突出部25とソース電極12とを接合層41により接合した後では、第一絶縁層15の開口部15aの内周縁部と接合層41との間の隙間Gの周辺領域は、封止樹脂32を介して表面側導体22Rにより覆われている。
なお、図5(A)において、表面側導体22Rをソース電極12に接合する前に第2絶縁層31Rを充填する場合、ソース電極12の表面側導体22Rを接合する領域(表面側導体接合領域に第2絶縁層31R)が侵入しないようにする工程が必要である。また、この工程では、ソース電極12の表面側導体接合領域と第1絶縁層15の開口15aの内周縁部との間に僅かな隙間Gを設ける必要があり、この僅かな隙間Gに絶縁材が十分に充填できず、ボイドAVの高電界による封止樹脂劣化は避けられない。
特に、突出部25がソース電極12に接合されているような狭い空間には、モールド法による封止樹脂は充填され難く、ボイドAVが発生する確率が高い。
次に、半導体装置100の製造方法を説明する。
先ず、半導体素子10を準備する。 上述したように、半導体素子10は、半導体基板11と、ソース電極12と、ドレイン電極13と、内部配線14と、第一絶縁層15とを有する。
そして、図2(A)に図示するように、半導体素子10のドレイン電極13と裏面側導体23とを接合層43により接合する。接合層43として、上述したように、はんだ、または焼結金属材料を用いることができる。焼結金属材料は、粉末やペースト状を有しており、加熱により焼結金属となる。焼結金属材料としては、銅や銀を含む焼結金属接合ペーストを用いることが好ましい。半導体素子10のドレイン電極13と裏面側導体23との間に接合層43を介在させ、熱圧着することにより接合する。
(1)半導体装置100は、開口部15aを有する第一絶縁層15および第一絶縁層15の開口部15aから露出するソース電極(表面電極)12を有する半導体素子10と、ソース電極12に接合された中継導体21と、ソース電極12と中継導体21とを接合する接合層41と、第一絶縁層15の少なくとも一部を覆い、少なくとも接合層41の周囲に接して設けられた第二絶縁層31と、中継導体21に接続された表面側導体(導体)22と、表面側導体22と第二絶縁層31との間に充填された封止樹脂32と、を備える。このように、第一絶縁層15の開口部15aから露出するソース電極12は、接合層41の周囲に接して設けられた第二絶縁層31により覆われている。このため、封止樹脂32にボイドAVが存在しても、部分放電の発生が抑制され、封止樹脂32の劣化を抑制することができる。
図4は、本発明の半導体装置の第2の実施形態の断面図である。
第2の実施形態の半導体装置100は、第二絶縁層31aが、半導体素子10の外周側面に延在され、裏面側導体23に接する構造を有する。
第1の実施形態では、第二絶縁層31は、半導体素子10の表面側にのみに形成されており、裏面側導体23に接するように延在されているものではなかった。このような構造では、接合層42により、中継導体21に表面側導体22を接合する際、熱圧着時の加熱により接合層41が溶融し、中継導体21が位置ずれを起こす可能性がある。第二の実施形態では、第二絶縁層31aが裏面側導体23に接する位置まで延在されている。第二絶縁層31aは中継導体21に接しているので、熱圧着時の加熱により接合層41が溶融しても、中継導体21の移動は、裏面側導体23に接する第二絶縁層31aにより規制される。
第2の実施形態においても、第1の実施形態と同様な効果を奏する。
また、第2の実施形態によれば、中継導体21に表面側導体22を接合する際の中継導体21の位置ずれを抑制することができる。
図6〜図8を参照して、本発明の第3の実施形態を説明する。
図6は、本発明の半導体装置の第3の実施形態の分解斜視図である。
半導体装置200は、4つの半導体装置300と、外側表面側導体222と、外側裏面側導体223とを備える。4つの半導体装置300は、相互に離間して、左右方向に2行、上下方向に2列、マトリクス状に配列されている。外側表面側導体222と外側裏面側導体223は、それぞれ、マトリクス状に配列された4つの半導体装置300の全領域を覆う大きさを有する。4つの半導体装置300は、いずれも同一の構造を有する。
2つの半導体装置300は、それぞれ、上アーム回路を有し、残りの2つの半導体装置300は、それぞれ、下アーム回路を有する。また、上アーム回路を有する半導体装置300と下アーム回路を有する半導体装置300は、直列に接続され、上下アーム直列回路を構成する。上アーム回路と下アーム回路の接続部から、位相の異なる交流出力が得られる電力変換装置を構成することができる。
半導体装置300は、4つの半導体素子10と、表面側導体122と、裏面側導体123とを備えている。4つの半導体素子10は、相互に離間して、左右方向に2行、上下方向に2列、マトリクス状に配列されている。すなわち、半導体装置300は、4in1パッケージとして構成されている。表面側導体122と裏面側導体123は、それぞれ、マトリクス状に配列された4つの半導体素子10の全領域を覆う大きさを有する。
不図示の制御部は、センス配線153を介した半導体素子10のソース電極12との接続をグランド、すなわち、基準電位として、ゲート配線152を介して半導体素子10のソース電極12に電圧を印加する。センス接続部131の断面積を大きくする理由としてインダクタンスを小さくすることを挙げたが、正確には、センス配線153を介した半導体素子10のソース電極12との接続におけるインダクタンスを小さくするためである。
各半導体装置300の表面側導体122は、接合層44により、外側表面側導体222に接合されている。各半導体装置300の裏面側導体123は、接合層45により、外側裏面側導体223に接合されている。接合層44、45は、接合層41〜43と同一の材料を用いて形成することができる。
高電界印加試験は、図8(b)の状態で行ってもよいし、図8(a)の状態で行って、再度、図8(b)の状態で行ってもよい。
12 ソース電極(表面電極)
13 ドレイン電極(裏面電極)
15 第一絶縁層
15a 開口部
21 中継導体
22 表面側導体(導体)
23 裏面側導体(対向導体)
31、31a 第二絶縁層
32 封止樹脂
41〜45 接合層
100 半導体装置
122 表面側導体(導体)
123 裏面側導体
200 半導体装置
222 外側表面側導体(外側導体)
223 外側裏面側導体
300 半導体装置
AV ボイド
G 隙間
Claims (14)
- 開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子と、
前記表面電極に接合された中継導体と、
前記表面電極と前記中継導体とを接合する接合層と、
前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接して設けられた第二絶縁層と、
前記中継導体に接続された導体と、
前記導体と前記第二絶縁層との間に充填された封止樹脂と、を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記開口部の周縁部と前記接合層の周囲との間に隙間が設けられ、
前記第二絶縁層は、前記隙間内に充填されている半導体装置。 - 請求項1に記載の半導体装置において、
前記第二絶縁層は、前記中継導体の少なくとも前記接合層側の周囲に接している半導体装置。 - 請求項1に記載の半導体装置において、
前記導体と前記中継導体とを接合する接合層をさらに備える半導体装置。 - 請求項1に記載の半導体装置において、
前記導体は、前記半導体素子の前記第一絶縁層全体を覆う面積を有し、
前記封止樹脂は、前記半導体素子の周囲を封止する半導体装置。 - 請求項1に記載の半導体装置において、
前記第二絶縁層は、前記第一絶縁層よりも厚く設けられている半導体装置。 - 請求項1に記載の半導体装置において、
前記中継導体は、インバーを含む半導体装置。 - 請求項1に記載の半導体装置において、
前記接合層は、金属接合ペーストが焼結された焼結金属である半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体素子は、前記表面電極の対向面側に裏面電極を有し、
さらに、前記裏面電極に接続された対向導体を有し、
前記第二絶縁層は、前記対向導体に接している半導体装置。 - 請求項1から請求項9までのいずれか一項に記載の半導体装置において、
前記半導体素子は、炭化ケイ素、窒化ガリウム、酸化ガリウム、ダイヤモンドのいずれかを母材とする半導体装置。 - 開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する複数の半導体素子と、
前記各半導体素子の前記表面電極に接合された中継導体と、
前記各表面電極と前記各中継導体とを接合する接合層と、
前記各第一絶縁層の少なくとも一部を覆い、少なくとも前記各接合層の周囲に接して設けられた第二絶縁層と、
前記各中継導体を接続する導体と、を備える半導体装置。 - 請求項11に記載の半導体装置において、
前記導体と前記第二絶縁層との間に充填された封止樹脂と、を備える半導体装置。 - 請求項11に記載の半導体装置を複数有し、
前記各半導体装置の前記導体を接続する外側導体を、さらに有する半導体装置。 - 開口部を有する第一絶縁層および前記第一絶縁層の前記開口部から露出する表面電極を有する半導体素子を準備することと、
前記表面電極と中継導体とを接合層により接合することと、
前記第一絶縁層の少なくとも一部を覆い、少なくとも前記接合層の周囲に接する第二絶縁層を設けることと、
前記中継導体に導体を接続することと、
前記導体と前記第二絶縁層との間に封止樹脂を充填することと、を含む半導体装置の製造方法。
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