JP2020202302A - Semiconductor growth substrate, semiconductor element, semiconductor light-emitting element, and manufacturing method of semiconductor element - Google Patents

Semiconductor growth substrate, semiconductor element, semiconductor light-emitting element, and manufacturing method of semiconductor element Download PDF

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JP2020202302A
JP2020202302A JP2019108460A JP2019108460A JP2020202302A JP 2020202302 A JP2020202302 A JP 2020202302A JP 2019108460 A JP2019108460 A JP 2019108460A JP 2019108460 A JP2019108460 A JP 2019108460A JP 2020202302 A JP2020202302 A JP 2020202302A
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JP7345286B2 (en
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大長　久芳
Hisayoshi Daicho
久芳 大長
大樹 神野
Daiki Kamino
大樹 神野
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Koito Manufacturing Co Ltd
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Abstract

To provide a semiconductor growth substrate capable of reducing the defect density and growing a nitride semiconductor layer having a high-quality a-plane as a main surface, a semiconductor element, a semiconductor light-emitting element, and a manufacturing method of a semiconductor element.SOLUTION: A semiconductor growth substrate (10) includes an r-plane sapphire substrate (11) having an r-plane as a main surface, a buffer layer (12) formed on the main surface, a plurality of dielectric masks (13) formed on the buffer layer (12), and a nitride semiconductor layer (14) having an a-plane as a main surface formed over the buffer layer (12) and the dielectric masks (13).SELECTED DRAWING: Figure 1

Description

本発明は、半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関し、特にａ面を主面とする窒化物半導体層を成長させる半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関する。 The present invention relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method, and particularly relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor for growing a nitride semiconductor layer having the a-plane as a main surface. The present invention relates to an element manufacturing method.

近年になって、照明用途に用いられる紫色から青色を発光するＬＥＤとして、非極性や半極性の面方位を主面としたＧａＮ系材料で活性層を形成するものが提案されている。ＧａＮ系半導体層では、ａ面やｍ面が非極性面であり、半極性面の代表例としてｒ面がある。非極性面や半極性面を用いたＧａＮ系半導体層では、積層方向へのピエゾ電界の影響を低減してドループ特性を改善することができる。 In recent years, as an LED that emits purple to blue light used for lighting applications, an LED that forms an active layer with a GaN-based material having a non-polar or semi-polar plane orientation as a main surface has been proposed. In the GaN-based semiconductor layer, the a-plane and the m-plane are non-polar planes, and the r-plane is a typical example of the semi-polar plane. In the GaN-based semiconductor layer using the non-polar surface or the semi-polar surface, the influence of the piezo electric field in the stacking direction can be reduced and the droop characteristics can be improved.

特許文献１には、ｒ面サファイア基板の主面にナノサイズの凸形状を形成し、バッファ層を介してａ面ＧａＮ層を成長させることで、横方向に成長するａ面ＧａＮ層中で転位を屈曲させ、半導体層の表面にまで継続する転位や欠陥を減少させる技術が提案されている。 In Patent Document 1, a nano-sized convex shape is formed on the main surface of the r-plane sapphire substrate, and the a-plane GaN layer is grown via the buffer layer to dislocate in the laterally growing a-plane GaN layer. Has been proposed to reduce dislocations and defects that continue to the surface of the semiconductor layer.

特開２０１９−０４０８９８号公報Japanese Unexamined Patent Publication No. 2019-040898

しかし、ｒ面サファイア基板上に形成されるａ面ＧａＮ層では、成長面内に±ｃ軸方向やｍ軸方向が存在するため、面内異方性により異常成長が生じやすく、ａ面ＧａＮ層の欠陥密度の低減にも限界があった。 However, in the a-plane GaN layer formed on the r-plane sapphire substrate, since the ± c-axis direction and the m-axis direction exist in the growth plane, abnormal growth is likely to occur due to in-plane anisotropy, and the a-plane GaN layer There was also a limit to the reduction of defect density.

そこで本発明は、上記従来の問題点に鑑みなされたものであり、欠陥密度を低減して高品質なａ面を主面とする窒化物半導体層を成長させることが可能な半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法を提供することを目的とする。 Therefore, the present invention has been made in view of the above-mentioned conventional problems, and is a semiconductor growth substrate capable of reducing the defect density and growing a nitride semiconductor layer having a high-quality a-plane as a main surface. An object of the present invention is to provide a semiconductor element, a semiconductor light emitting element, and a method for manufacturing a semiconductor element.

上記課題を解決するために、本発明の半導体成長用基板は、ｒ面を主面とするｒ面サファイア基板と、前記主面上に形成されたバッファ層と、前記バッファ層上に形成された複数の誘電体マスクと、前記バッファ層および前記誘電体マスクを覆って形成されたａ面を主面とする窒化物半導体層を備えることを特徴とする。 In order to solve the above problems, the semiconductor growth substrate of the present invention is formed on an r-plane sapphire substrate having an r-plane as a main surface, a buffer layer formed on the main surface, and the buffer layer. It is characterized by comprising a plurality of dielectric masks and a nitride semiconductor layer having the buffer layer and the a-plane formed over the dielectric mask as a main surface.

このような本発明の半導体成長用基板では、バッファ層上に誘電体マスクが形成されており、誘電体マスクの間から露出したバッファ層表面からのみ窒化物半導体層の成長が始まる。これにより、ａ面を主面とする窒化物半導体層の横方向成長を促進することができ、欠陥密度を低減して高品質なａ面を主面とする窒化物半導体層を成長させることが可能となる。 In such a semiconductor growth substrate of the present invention, a dielectric mask is formed on the buffer layer, and the nitride semiconductor layer starts to grow only from the surface of the buffer layer exposed between the dielectric masks. As a result, the lateral growth of the nitride semiconductor layer having the a-plane as the main surface can be promoted, the defect density can be reduced, and the nitride semiconductor layer having the a-plane as the main surface can be grown. It will be possible.

また本発明の一態様では、前記誘電体マスクは、前記主面の面内方向における最大寸法が１．２μｍ未満、高さ方向の最大寸法が２μｍ未満である。 Further, in one aspect of the present invention, the dielectric mask has a maximum dimension of less than 1.2 μm in the in-plane direction of the main surface and a maximum dimension of less than 2 μm in the height direction.

また本発明の一態様では、前記誘電体マスクは、ＳｉＯ２で構成されている。 Further, in one aspect of the present invention, the dielectric mask is made of SiO 2 .

また本発明の一態様では、前記バッファ層は、ＡｌＮで構成されている。 Further, in one aspect of the present invention, the buffer layer is composed of AlN.

また本発明の一態様では、前記窒化物半導体層は、ＧａＮで構成されている。 Further, in one aspect of the present invention, the nitride semiconductor layer is made of GaN.

また上記課題を解決するために本発明の半導体素子は、上記何れか一つに記載の半導体成長用基板を用い、前記半導体成長用基板上に機能層を備えることを特徴とする。 Further, in order to solve the above problems, the semiconductor device of the present invention is characterized in that the semiconductor growth substrate according to any one of the above is used and a functional layer is provided on the semiconductor growth substrate.

また上記課題を解決するために本発明の半導体発光素子は、上記何れか一つに記載の半導体成長用基板を用い、前記半導体成長用基板上に活性層を備えることを特徴とする。 Further, in order to solve the above problems, the semiconductor light emitting device of the present invention is characterized in that the semiconductor growth substrate according to any one of the above is used and an active layer is provided on the semiconductor growth substrate.

また上記課題を解決するために本発明の半導体素子製造方法は、ｒ面を主面とするｒ面サファイア基板の前記主面上にバッファ層を形成するバッファ層形成工程と、前記バッファ層上に誘電体マスクを形成するマスク形成工程と、前記誘電体マスクの間から露出する前記バッファ層からａ面を主面とする窒化物半導体層を成長させる下地層成長工程を備えることを特徴とする。 Further, in order to solve the above problems, the semiconductor device manufacturing method of the present invention includes a buffer layer forming step of forming a buffer layer on the main surface of an r-plane sapphire substrate having an r-plane as a main surface, and a buffer layer forming step on the buffer layer. It is characterized by including a mask forming step of forming a dielectric mask and a base layer growing step of growing a nitride semiconductor layer having a plane a as a main surface from the buffer layer exposed between the dielectric masks.

このような本発明の半導体素子製造方法では、バッファ層上に誘電体マスクが形成されており、誘電体マスクの間から露出したバッファ層表面からのみ窒化物半導体層の成長が始まる。これにより、ａ面を主面とする窒化物半導体層の横方向成長を促進することができ、欠陥密度を低減して高品質なａ面を主面とする窒化物半導体層を成長させることが可能となる。 In such a semiconductor device manufacturing method of the present invention, a dielectric mask is formed on the buffer layer, and the nitride semiconductor layer starts to grow only from the surface of the buffer layer exposed between the dielectric masks. As a result, the lateral growth of the nitride semiconductor layer having the a-plane as the main surface can be promoted, the defect density can be reduced, and the nitride semiconductor layer having the a-plane as the main surface can be grown. It will be possible.

また本発明の一態様では、前記バッファ層形成工程では、スパッタ法を用いてＡｌＮで前記バッファ層を形成する。 Further, in one aspect of the present invention, in the buffer layer forming step, the buffer layer is formed with AlN by using a sputtering method.

本発明では、欠陥密度を低減して高品質なａ面を主面とする窒化物半導体層を成長させることが可能な半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法を提供することができる。 The present invention provides a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method capable of reducing the defect density and growing a nitride semiconductor layer having a high-quality a-plane as a main surface. be able to.

第１実施形態における半導体成長用基板１０を示す模式断面図である。It is a schematic cross-sectional view which shows the semiconductor growth substrate 10 in 1st Embodiment. 半導体成長用基板１０の製造方法を模式的に示す工程図である。It is a process drawing which shows typically the manufacturing method of the semiconductor growth substrate 10. 半導体成長用基板１０の製造方法を模式的に示す工程図である。It is a process drawing which shows typically the manufacturing method of the semiconductor growth substrate 10. 比較対象の半導体成長用基板２０を示す模式断面図である。It is a schematic cross-sectional view which shows the semiconductor growth substrate 20 to be compared. 第２実施形態の半導体装置であるＬＥＤを示す模式断面図である。It is a schematic cross-sectional view which shows LED which is the semiconductor device of 2nd Embodiment.

（第１実施形態）
以下、本発明の実施の形態について、図面を参照して詳細に説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付すものとし、適宜重複した説明は省略する。図１は、本発明の第１実施形態における半導体成長用基板１０を示す模式断面図である。図１に示すように、本実施形態の半導体成長用基板は、ｒ面サファイア基板１１と、バッファ層１２と、誘電体マスク１３と、窒化物半導体層１４を備えている。 (First Embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. FIG. 1 is a schematic cross-sectional view showing a semiconductor growth substrate 10 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor growth substrate of this embodiment includes an r-plane sapphire substrate 11, a buffer layer 12, a dielectric mask 13, and a nitride semiconductor layer 14.

ｒ面サファイア基板１１は、サファイアの単結晶で構成された基板であり、六方晶のｒ面を主面としている。ここではｒ面サファイア基板１１として傾斜角度が０度のジャスト基板を示したが、ｒ面を所定の面方位に数度傾斜させたオフ基板としてもよい。 The r-plane sapphire substrate 11 is a substrate composed of a single crystal of sapphire, and has a hexagonal r-plane as a main surface. Here, the just substrate having an inclination angle of 0 degrees is shown as the r-plane sapphire substrate 11, but an off-board substrate in which the r-plane is inclined by several degrees in a predetermined plane direction may be used.

バッファ層１２は、ｒ面サファイア基板１１と窒化物半導体層１４との間での格子不整合を緩和するために形成された層である。バッファ層１２を構成する材料としては、ＡｌＮ，ＧａＮ，ＩｎＧａＮ，ＡｌＧａＮ等が挙げられるが、ＡｌＮを用いることが好ましい。また、バッファ層１２を形成する方法としては、スパッタ法や有機金属気相成長法（ＭＯＣＶＤ法：ＭｅｔａｌＯｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）等を用いることができ、スパッタ法を用いることが好ましい。バッファ層１２の厚みとしては、厚くしすぎると窒化物半導体層１４の結晶品質が低下するため５〜３００ｎｍの範囲が好ましく、５〜９０ｎｍの範囲がより好ましく、５〜３０ｎｍの範囲がさらに好ましい。 The buffer layer 12 is a layer formed to alleviate the lattice mismatch between the r-plane sapphire substrate 11 and the nitride semiconductor layer 14. Examples of the material constituting the buffer layer 12 include AlN, GaN, InGaN, AlGaN, and the like, but it is preferable to use AlN. Further, as a method for forming the buffer layer 12, a sputtering method, a metalorganic vapor phase growth method (MOCVD method: Metalorganic Chemical Vapor Deposition), or the like can be used, and it is preferable to use the sputtering method. The thickness of the buffer layer 12 is preferably in the range of 5 to 300 nm, more preferably in the range of 5 to 90 nm, and even more preferably in the range of 5 to 30 nm because the crystal quality of the nitride semiconductor layer 14 deteriorates if it is made too thick.

誘電体マスク１３は、バッファ層１２上に誘電体材料で形成されたパターンであり、バッファ層１２を部分的に覆う層である。誘電体マスク１３を構成する材料は、表面から窒化物半導体層が結晶成長しないものであれば限定されず、例えばＳｉＯ２やＳｉＮ、ＳｉＯＮ、ＴｉＯ２等を用いることができ、ＳｉＯ２を用いることが好ましい。図１では、誘電体マスク１３として断面が三角形状や円錐形状の場合を示したが、四角錐形状や三角錐形状であってもよく、断面が矩形状や曲面形状であってもよい。また、ｒ面サファイア基板１１上での誘電体マスク１３の配置は限定されず、例えば三角格子状や正方格子状に配置するとしてもよく、ストライプ状や井桁状などであってもよい。 The dielectric mask 13 is a pattern formed of a dielectric material on the buffer layer 12, and is a layer that partially covers the buffer layer 12. The material constituting the dielectric mask 13 is not limited as long as the nitride semiconductor layer does not crystal grow from the surface, and for example, SiO 2 , SiN, SiON, TiO 2 and the like can be used, and SiO 2 is used. Is preferable. Although FIG. 1 shows the case where the dielectric mask 13 has a triangular or conical cross section, it may have a quadrangular pyramid shape or a triangular pyramid shape, and the cross section may have a rectangular shape or a curved surface shape. Further, the arrangement of the dielectric mask 13 on the r-plane sapphire substrate 11 is not limited, and may be arranged in a triangular lattice shape or a square lattice shape, or may be in a striped shape or a grid shape.

また誘電体マスク１３は、ｒ面サファイア基板１１の面内方向における最大寸法が１．２μｍ未満の範囲であることが好ましく、高さ方向の最大寸法が２μｍ未満であることが好ましい。誘電体マスク１３のサイズが上記範囲を超える場合には、誘電体マスク１３を覆って平坦化するまでの窒化物半導体層１４の膜厚が大きくなりすぎて好ましくない。 Further, the dielectric mask 13 preferably has a maximum dimension of the r-plane sapphire substrate 11 in the in-plane direction of less than 1.2 μm, and preferably a maximum dimension of the height direction of less than 2 μm. When the size of the dielectric mask 13 exceeds the above range, the film thickness of the nitride semiconductor layer 14 until the dielectric mask 13 is covered and flattened becomes too large, which is not preferable.

窒化物半導体層１４は、主面がａ面となるように成長された下地層であり、その上に他の窒化物半導体からなる層をエピタキシャル成長するための層である。窒化物半導体層１４を構成する材料としては、ＧａＮ、ＩｎＧａＮ，ＡｌＧａＮ等が挙げられるが、ａ面ＧａＮで構成することが好ましい。窒化物半導体層１４の形成方法としては、ＭＯＣＶＤ法やＨＶＰＥ法（ハイドライド気相成長法：Ｈｙｄｒｉｄｅ Ｖａｐｏｒ Ｐｈａｓｅ Ｅｐｉｔａｘｙ）などの公知の方法を用いることができるが、ＭＯＣＶＤ法を用いることが好ましい。窒化物半導体層１４の膜厚は特に限定されないが、１μｍ以上形成することが好ましい。 The nitride semiconductor layer 14 is a base layer grown so that the main surface is the a-plane, and is a layer for epitaxially growing a layer made of another nitride semiconductor on the base layer. Examples of the material constituting the nitride semiconductor layer 14 include GaN, InGaN, AlGaN, etc., and it is preferable to use a-plane GaN. As a method for forming the nitride semiconductor layer 14, known methods such as a MOCVD method and an HVPE method (Hydride Vapor Phase Epitaxy) can be used, but it is preferable to use the MOCVD method. The film thickness of the nitride semiconductor layer 14 is not particularly limited, but it is preferably formed at 1 μm or more.

図１に示したように、本実施形態の半導体成長用基板１０では、窒化物半導体層１４中に欠陥１５ａ，１５ｂが含まれている。欠陥１５ａは、誘電体マスク１３の略中央から窒化物半導体層１４の表面まで伸びる貫通転位であり、窒化物半導体層１４の横方向成長によって誘電体マスク１５ａ上に集約されている。欠陥１５ｂは、誘電体マスク１３間のバッファ層１２から窒化物半導体層１４の表面まで伸びる貫通転位であり、横方向成長によって転移が曲げられずに継続している。 As shown in FIG. 1, in the semiconductor growth substrate 10 of the present embodiment, defects 15a and 15b are included in the nitride semiconductor layer 14. The defect 15a is a penetrating dislocation extending from substantially the center of the dielectric mask 13 to the surface of the nitride semiconductor layer 14, and is aggregated on the dielectric mask 15a by the lateral growth of the nitride semiconductor layer 14. The defect 15b is a through dislocation extending from the buffer layer 12 between the dielectric masks 13 to the surface of the nitride semiconductor layer 14, and the dislocation continues without being bent by the lateral growth.

次に、本実施形態における半導体成長用基板１０の製造方法について図２，図３を用いて説明する。図２および図３は、半導体成長用基板１０の製造方法を模式的に示す工程図である。 Next, the method of manufacturing the semiconductor growth substrate 10 in the present embodiment will be described with reference to FIGS. 2 and 3. 2 and 3 are process diagrams schematically showing a method for manufacturing the semiconductor growth substrate 10.

（基板準備工程）
まず、図２（ａ）に示すように、サファイア単結晶からｒ面を主面とする基板を形成し、表面を洗浄してｒ面サファイア基板１１を用意する。 (Board preparation process)
First, as shown in FIG. 2A, a substrate having an r-plane as a main surface is formed from a sapphire single crystal, and the surface is washed to prepare an r-plane sapphire substrate 11.

（バッファ層形成工程）
次に、図２（ｂ）に示すように、ｒ面サファイア基板１１の主面上に全域にわたって、膜厚が５ｎｍ〜６００ｎｍ程度のバッファ層１２を形成する。バッファ層１２の形成方法としては、スパッタ法、蒸着、エピタキシャル成長等の公知の方法を用いることができる。窒化物半導体層１４としてＧａＮを成長する場合には、スパッタ法を用いてＡｌＮからなるバッファ層１２を形成することが好ましい。バッファ層１２を形成するスパッタ法としては、ＡｌＮをターゲット材としてＡｒガスを用いることがより好ましい。ターゲット材となるＡｌＮとしては単結晶基板であっても粉末焼体であってもよく、その状態や形態は限定されない。 (Buffer layer forming process)
Next, as shown in FIG. 2B, a buffer layer 12 having a film thickness of about 5 nm to 600 nm is formed over the entire main surface of the r-plane sapphire substrate 11. As a method for forming the buffer layer 12, known methods such as a sputtering method, thin film deposition, and epitaxial growth can be used. When GaN is grown as the nitride semiconductor layer 14, it is preferable to form the buffer layer 12 made of AlN by using a sputtering method. As a sputtering method for forming the buffer layer 12, it is more preferable to use Ar gas with AlN as a target material. The AlN as the target material may be a single crystal substrate or a powder-fired body, and its state and form are not limited.

バッファ層１２を形成する反応性スパッタの条件としては、基板温度は２００℃以上５００℃未満の範囲が好ましい。基板温度を５００℃よりも高温にすると、成膜後にバッファ層１２に含まれる酸素や炭素の不純物濃度が高くなり、バッファ層１２上に窒化物半導体層１４をエピタキシャル成長できないため好ましくない。本実施形態の半導体素子成長方法では、高品質なＡｌＮ結晶が得られる１５００℃程度よりも低温の２００〜５００℃でスパッタ工程を実施するため、成膜直後のバッファ層１２はアモルファスライクな結晶性であると思われる。 As the condition of the reactive sputtering for forming the buffer layer 12, the substrate temperature is preferably in the range of 200 ° C. or higher and lower than 500 ° C. When the substrate temperature is higher than 500 ° C., the concentration of oxygen and carbon impurities contained in the buffer layer 12 increases after film formation, and the nitride semiconductor layer 14 cannot be epitaxially grown on the buffer layer 12, which is not preferable. In the semiconductor device growth method of the present embodiment, since the sputtering step is carried out at 200 to 500 ° C., which is lower than about 1500 ° C. at which high quality AlN crystals can be obtained, the buffer layer 12 immediately after film formation has amorphous-like crystallinity. It seems to be.

（アニール工程）
次に、バッファ層１２にアニール処理を実施し、バッファ層１２の再結晶化を促進して積層方向および面内方向に一軸配向性を持たせる。アニール処理としては、例えば高周波誘導加熱方式による熱処理装置を用いることができる。アニール条件としては、不活性ガス（例えば窒素やＡｒ）雰囲気中において１３００℃以上１７００℃未満の基板温度を０．５〜３．０時間継続することが好ましい。より好ましくは１３００℃以上１６００℃以下である。アニール温度が１７００℃以上であると、ｒ面サファイア基板１１が熱分解して劣化するため好ましくない。また、アニール温度が１３００℃未満であると、バッファ層１２の再結晶化が不十分であり、バッファ層１２の積層方向および面内方向における一軸配向性が不十分となる。 (Annealing process)
Next, the buffer layer 12 is annealed to promote recrystallization of the buffer layer 12 so that the buffer layer 12 has uniaxial orientation in the stacking direction and the in-plane direction. As the annealing treatment, for example, a heat treatment apparatus based on a high frequency induction heating method can be used. As the annealing condition, it is preferable to maintain the substrate temperature of 1300 ° C. or higher and lower than 1700 ° C. for 0.5 to 3.0 hours in an atmosphere of an inert gas (for example, nitrogen or Ar). More preferably, it is 1300 ° C. or higher and 1600 ° C. or lower. If the annealing temperature is 1700 ° C. or higher, the r-plane sapphire substrate 11 is thermally decomposed and deteriorated, which is not preferable. Further, if the annealing temperature is less than 1300 ° C., the recrystallization of the buffer layer 12 is insufficient, and the uniaxial orientation of the buffer layer 12 in the stacking direction and the in-plane direction is insufficient.

（マスク形成工程）
次に、図２（ｃ）に示すように、バッファ層１２上の全域にわたって誘電体材料を積層して、膜厚が８００ｎｍ〜２０００ｎｍ程度の誘電体マスク１３を形成する。誘電体材料の積層には、スパッタ法や蒸着、ゾル・ゲル法、プラズマＣＶＤ法、スピンコート法等の公知の方法を用いることができる。 (Mask forming process)
Next, as shown in FIG. 2C, the dielectric materials are laminated over the entire area on the buffer layer 12 to form the dielectric mask 13 having a film thickness of about 800 nm to 2000 nm. Known methods such as a sputtering method, a vapor deposition, a sol-gel method, a plasma CVD method, and a spin coating method can be used for laminating the dielectric material.

次に、図２（ｄ）に示すように、バッファ層１２上にレジスト膜１６をスピンコート等で塗布して、凸部１６ａと凹部１６ｂに対応したパターンが形成されたナノインプリント技術のモールドを用い、レジスト膜１６を硬化して凸部１６ａと凹部１６ｂを形成する。レジスト膜１６の材料は限定されず、熱硬化型であってもＵＶ硬化型であってもよい。 Next, as shown in FIG. 2D, a mold of nanoimprint technology was used in which a resist film 16 was applied onto the buffer layer 12 by spin coating or the like to form a pattern corresponding to the convex portion 16a and the concave portion 16b. , The resist film 16 is cured to form the convex portion 16a and the concave portion 16b. The material of the resist film 16 is not limited, and may be a thermosetting type or a UV curing type.

次に、図３（ａ）に示すように、レジスト膜１６および誘電体マスク１３をエッチングして誘電体マスク１３をパターニングし、誘電体マスク１３の間からバッファ層１２の表面を露出させる。このとき、パターニングされた誘電体マスク１３の高さは６００ｎｍ〜１２００ｎｍ程度とすることが好ましい。誘電体マスク１３をパターニングした後には、アセトン洗浄やオゾン洗浄等を用いて表面を洗浄し、レジスト膜１６の残渣を除去する。 Next, as shown in FIG. 3A, the resist film 16 and the dielectric mask 13 are etched to pattern the dielectric mask 13 so that the surface of the buffer layer 12 is exposed between the dielectric masks 13. At this time, the height of the patterned dielectric mask 13 is preferably about 600 nm to 1200 nm. After patterning the dielectric mask 13, the surface is washed with acetone washing, ozone washing, or the like to remove the residue of the resist film 16.

（下地層成長工程）
次に、誘電体マスク１３の間から露出するバッファ層１２上に、下地層である窒化物半導体層１４を成長させる。窒化物半導体層１４としてＭＯＣＶＤ法を用いてＧａＮを成長する場合には、キャリアガスとして水素、窒素を用い、Ｖ族原料としてアンモニア（ＮＨ３）を用い、ＩＩＩ族原料としてＴＭＧ（ＴｒｉｍｅｔｈｙｌＧａｌｌｉｕｍ）を用いる。このとき、成長シーケンスは２段階で構成し、昇温した後に成長温度を一定とし、リアクタ圧力とＶ／ＩＩＩ比および成長時間を変更している。例えば、昇温直後の第１ステップではＶ／ＩＩＩ比を４０００〜５０００程度とし、圧力を９００〜１０００ｈＰａとして１０〜２０分程度維持する。第２ステップでは例えばＶ／ＩＩＩ比を１００〜２００程度とし、圧力を１００〜１５０ｈＰａとして９０〜１２０分維持する。 (Underground layer growth process)
Next, the nitride semiconductor layer 14, which is a base layer, is grown on the buffer layer 12 exposed from between the dielectric masks 13. When GaN is grown as the nitride semiconductor layer 14 by the MOCVD method, hydrogen and nitrogen are used as carrier gases, ammonia (NH 3 ) is used as a group V raw material, and TMG (Trimethylgallium) is used as a group III raw material. .. At this time, the growth sequence is composed of two steps, the growth temperature is kept constant after the temperature is raised, and the reactor pressure, the V / III ratio, and the growth time are changed. For example, in the first step immediately after the temperature rise, the V / III ratio is set to about 4000 to 5000, the pressure is set to 900 to 1000 hPa, and the pressure is maintained for about 10 to 20 minutes. In the second step, for example, the V / III ratio is set to about 100 to 200, the pressure is set to 100 to 150 hPa, and the pressure is maintained for 90 to 120 minutes.

本実施形態は図３（ｂ）に示すように、成長の初期段階において誘電体マスク１３の間から露出したバッファ層１２の表面に窒化物半導体の成長核１７が生じ、成長核１７から窒化物半導体層１４のエピタキシャル成長が行われる。したがって窒化物半導体層１４は、誘電体マスク１３の表面や側面から成長せず、ｒ面サファイア基板１１の主面に対応したバッファ層１２の表面からのみ成長するため、窒化物半導体層１４の成長主面がａ面となる。 In this embodiment, as shown in FIG. 3B, growth nuclei 17 of nitride semiconductors are formed on the surface of the buffer layer 12 exposed from between the dielectric masks 13 in the initial stage of growth, and the growth nuclei 17 to nitride Epitaxial growth of the semiconductor layer 14 is performed. Therefore, the nitride semiconductor layer 14 does not grow from the surface or side surface of the dielectric mask 13, but grows only from the surface of the buffer layer 12 corresponding to the main surface of the r-plane sapphire substrate 11, so that the nitride semiconductor layer 14 grows. The main surface is the a surface.

窒化物半導体層１４の成長を継続すると、誘電体マスク１３の間から露出したバッファ層１２の表面からのみ窒化物半導体層１４は成長し、横方向成長によって誘電体マスク１３上を覆うまで形成される。窒化物半導体層１４の横方向成長に伴って貫通転位も横方向に曲げられて欠陥１５ａに集約され、欠陥密度は５×１０８ｃｍ-３程度まで低減される。 When the growth of the nitride semiconductor layer 14 is continued, the nitride semiconductor layer 14 grows only from the surface of the buffer layer 12 exposed from between the dielectric masks 13, and is formed until it covers the dielectric mask 13 by lateral growth. To. Threading dislocations with the lateral growth of the nitride semiconductor layer 14 is also aggregated into bent in defects 15a in the lateral direction, the defect density is reduced to about 5 × 10 8 cm -3.

最後に窒化物半導体層１４を成長した後に室温まで冷却して取り出すことで、図３（ｃ）に示したようにｒ面サファイア基板１１の主面にバッファ層１２が形成され、誘電体マスク１３を埋めて窒化物半導体層１４が形成された本実施形態の半導体成長用基板１０を得る。窒化物半導体層１４を形成した後に、継続して半導体素子を構成するための各層をエピタキシャル成長するとしてもよい。 Finally, after the nitride semiconductor layer 14 is grown, it is cooled to room temperature and taken out, so that the buffer layer 12 is formed on the main surface of the r-plane sapphire substrate 11 as shown in FIG. 3C, and the dielectric mask 13 is formed. Is buried to obtain the semiconductor growth substrate 10 of the present embodiment in which the nitride semiconductor layer 14 is formed. After forming the nitride semiconductor layer 14, each layer for continuously forming the semiconductor element may be epitaxially grown.

図４は、比較対象の半導体成長用基板２０を示す模式断面図である。図４に示すように半導体成長用基板２０は、ｒ面サファイア基板２１と、複数の凸形状２１ａと、バッファ層２２と、窒化物半導体層２４を備えている。 FIG. 4 is a schematic cross-sectional view showing the semiconductor growth substrate 20 to be compared. As shown in FIG. 4, the semiconductor growth substrate 20 includes an r-plane sapphire substrate 21, a plurality of convex shapes 21a, a buffer layer 22, and a nitride semiconductor layer 24.

凸形状２１ａは、ナノインプリント技術やフォトリソグラフィー技術を用いてｒ面サファイア基板２１上にエッチングマスクをパターニングした後に、塩素系ガスを用いてｒ面サファイア基板２１を異方性エッチングして形成することができる。またバッファ層２２は、r面サファイア基板２１の主面と凸形状２１ａ全体を覆うように形成されている。窒化物半導体層２４には、窒化物半導体層２４の横方向成長によって凸形状２１ａ上に集約された欠陥２５ａや、凸形状２１ａ間のバッファ層２２から窒化物半導体層２４の表面まで伸びる欠陥２５ｂ、凸形状２１ａの側面から生じた欠陥２５ｃを含んでいる。 The convex shape 21a can be formed by patterning an etching mask on the r-plane sapphire substrate 21 using nanoimprint technology or photolithography technology, and then anisotropically etching the r-plane sapphire substrate 21 with chlorine-based gas. it can. Further, the buffer layer 22 is formed so as to cover the main surface of the r-plane sapphire substrate 21 and the entire convex shape 21a. In the nitride semiconductor layer 24, defects 25a aggregated on the convex shape 21a due to lateral growth of the nitride semiconductor layer 24 and defects 25b extending from the buffer layer 22 between the convex shapes 21a to the surface of the nitride semiconductor layer 24. , Includes a defect 25c arising from the side surface of the convex shape 21a.

図４に示したように半導体成長用基板２０では、凸形状２１ａの側面にもバッファ層２２が形成されているため、窒化物半導体層２４の成長初期段階において凸形状２１ａの側面にも成長核が生じる。凸形状２１ａの側面から成長した窒化物半導体層２４は、ａ面とは異なる主面で結晶成長する可能性があるため、凸形状２１ａの側面から欠陥２５ｃが生じやすくなる。したがって半導体成長用基板２０では、横方向成長による欠陥密度の低減に限界があり、９×１０９ｃｍ-３程度の欠陥密度となってしまう。 As shown in FIG. 4, in the semiconductor growth substrate 20, since the buffer layer 22 is also formed on the side surface of the convex shape 21a, the growth nucleus is also formed on the side surface of the convex shape 21a at the initial stage of growth of the nitride semiconductor layer 24. Occurs. Since the nitride semiconductor layer 24 grown from the side surface of the convex shape 21a may grow crystals on a main surface different from the a surface, defects 25c are likely to occur from the side surface of the convex shape 21a. Therefore, in the semiconductor growth substrate 20, there is a limit to the reduction of the defect density due to the lateral growth, and the defect density is about 9 × 10 9 cm −3 .

それに対して本実施形態の半導体成長用基板１０では、ｒ面を主面とするｒ面サファイア基板１１上にバッファ層１２が形成され、バッファ層１２上に複数の誘電体マスク１３がパターニングされ、バッファ層１２および誘電体マスク１３を覆ってａ面を主面とする窒化物半導体層１４が形成されているため、欠陥密度を低減して高品質なａ面を主面とする窒化物半導体層を成長させることが可能となる。 On the other hand, in the semiconductor growth substrate 10 of the present embodiment, the buffer layer 12 is formed on the r-plane sapphire substrate 11 having the r-plane as the main surface, and a plurality of dielectric masks 13 are patterned on the buffer layer 12. Since the nitride semiconductor layer 14 having the a-plane as the main surface is formed over the buffer layer 12 and the dielectric mask 13, the defect density is reduced and the high-quality nitride semiconductor layer having the a-plane as the main surface is formed. It becomes possible to grow.

（第２実施形態）
次に、本発明の第２実施形態について図５を用いて説明する。図５は本実施形態の半導体装置であるＬＥＤを示す模式断面図である。図５に示すようにＬＥＤは、ｒ面サファイア基板１１、バッファ層１２、誘電体マスク１３、窒化物半導体層１４、活性層１８、ｐ型半導体層１９、ｎ側電極３１、ｐ側電極３２を有している。 (Second Embodiment)
Next, the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view showing an LED which is a semiconductor device of this embodiment. As shown in FIG. 5, the LED includes an r-plane sapphire substrate 11, a buffer layer 12, a dielectric mask 13, a nitride semiconductor layer 14, an active layer 18, a p-type semiconductor layer 19, an n-side electrode 31, and a p-side electrode 32. Have.

第１実施形態と同様に、ｒ面サファイア基板１１を用意し、バッファ層１２、誘電体マスク１３を形成し、ＭＯＣＶＤ法で窒化物半導体層１４をエピタキシャル成長する。続いて、ＭＯＣＶＤ法で活性層１８、ｐ型半導体層１９を順次成長して半導体基板を得る。 Similar to the first embodiment, the r-plane sapphire substrate 11 is prepared, the buffer layer 12 and the dielectric mask 13 are formed, and the nitride semiconductor layer 14 is epitaxially grown by the MOCVD method. Subsequently, the active layer 18 and the p-type semiconductor layer 19 are sequentially grown by the MOCVD method to obtain a semiconductor substrate.

次に、フォトリソグラフィーとエッチングによりｐ型半導体層１９と活性層１８の一部を除去して 窒化物半導体層１４の一部を露出させる。次に、 窒化物半導体層１４とｐ型半導体層１９の露出面に蒸着等により電極材料を形成し、ダイシングして個別チップ化することでＬＥＤを得る。 Next, a part of the p-type semiconductor layer 19 and the active layer 18 is removed by photolithography and etching to expose a part of the nitride semiconductor layer 14. Next, an electrode material is formed on the exposed surfaces of the nitride semiconductor layer 14 and the p-type semiconductor layer 19 by vapor deposition or the like, and the LED is obtained by dicing and forming individual chips.

活性層１８は、 窒化物半導体層１４上にエピタキシャル成長され、ａ面を主面とする半導体層であり、層内で電子と正孔が発光再結合することでＬＥＤが発光する。活性層１８は、窒化物半導体層１４とｐ型半導体層１９よりもバンドギャップが小さい材料で構成されており、例えばＩｎＧａＮ、ＡｌＩｎＧａＮなどが挙げられる。活性層１８は意図的に不純物を含まないノンドープとしてもよく、ｎ型不純物を含むｎ型やｐ型不純物を含むｐ型としてもよい。活性層１８は、ａ面を主面とする半導体層なので、厚膜化してもピエゾ電界による電子と正孔の空間的な分離は生じにくく、電流密度を高くしても効率的に電子と正孔が発光再結合できる。 The active layer 18 is a semiconductor layer epitaxially grown on the nitride semiconductor layer 14 and having the a-plane as the main surface, and the LED emits light when electrons and holes are luminescent and recombinated in the layer. The active layer 18 is made of a material having a bandgap smaller than that of the nitride semiconductor layer 14 and the p-type semiconductor layer 19, and examples thereof include InGaN and AlInGaN. The active layer 18 may be intentionally non-doped containing impurities, or may be n-type containing n-type impurities or p-type containing p-type impurities. Since the active layer 18 is a semiconductor layer having the a-plane as the main surface, spatial separation of electrons and holes due to the piezo electric field is unlikely to occur even if the film is thickened, and even if the current density is increased, the electrons and holes are efficiently positive. Holes can luminescence recombine.

ｐ型半導体層１９は、活性層１８上にエピタキシャル成長され、ａ面を主面とする半導体層であり、ｐ側電極３２から正孔が注入されて活性層１８に正孔を供給する層である。 The p-type semiconductor layer 19 is a semiconductor layer epitaxially grown on the active layer 18 and having the a-plane as the main surface, and is a layer in which holes are injected from the p-side electrode 32 to supply holes to the active layer 18. ..

ここでは 窒化物半導体層１４、ｐ型半導体層１９をそれぞれ単層で説明したが、それぞれ材料や組成の異なる複数の層を含んでいるとしてもよく、例えば、 窒化物半導体層１４とｐ型半導体層１９にクラッド層、コンタクト層、電流拡散層、電子ブロック層、導波路層などを含めてもよい。また、活性層１８も単層で説明したが、多重量子井戸構造（ＭＱＷ：Ｍｕｌｔｉ Ｑｕａｎｔｕｍ Ｗｅｌｌ）などの複数層で構成してもよい。 Here, the nitride semiconductor layer 14 and the p-type semiconductor layer 19 have been described as a single layer, but they may include a plurality of layers having different materials and compositions, for example, the nitride semiconductor layer 14 and the p-type semiconductor. The layer 19 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like. Further, although the active layer 18 has been described as a single layer, it may be composed of a plurality of layers such as a multiple quantum well structure (MQW: Multi Quantum Well).

本実施の形態でも、ｒ面サファイア基板１１上にバッファ層１２および誘電体マスク１３が形成されており、窒化物半導体層１４、活性層１８、ｐ型半導体層１９をエピタキシャル成長している。第１実施形態で述べたように窒化物半導体層１４は結晶性も表面平坦性も良好であり、欠陥密度が低減されている。したがって、欠陥密度が低減された窒化物半導体層１４上に成長された活性層１８、ｐ型半導体層１９も結晶性と表面平坦性が良好となる。これにより、活性層１８、ｐ型半導体層１９の特性も良好になり、ＬＥＤの外部量子効率の向上などが見込まれる。 Also in this embodiment, the buffer layer 12 and the dielectric mask 13 are formed on the r-plane sapphire substrate 11, and the nitride semiconductor layer 14, the active layer 18, and the p-type semiconductor layer 19 are epitaxially grown. As described in the first embodiment, the nitride semiconductor layer 14 has good crystallinity and surface flatness, and the defect density is reduced. Therefore, the active layer 18 and the p-type semiconductor layer 19 grown on the nitride semiconductor layer 14 having the reduced defect density also have good crystallinity and surface flatness. As a result, the characteristics of the active layer 18 and the p-type semiconductor layer 19 are also improved, and it is expected that the external quantum efficiency of the LED will be improved.

本発明の半導体装置であるＬＥＤは、上述したようにピエゾ電界によるドループが少なく、且つａ面内での異方性が小さく良好な結晶品質であることから高輝度化を実現できるので、車両用灯具などの灯具に用いることでチップ数の低減や高出力化を図ることが可能となる。また、半導体装置はＬＥＤに限定されず、半導体レーザであってもよく、二次元電子ガスを発生させる機能層を有する高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ）等の他の用途であってもよい。 As described above, the LED, which is the semiconductor device of the present invention, has less droop due to the piezo electric field, has less anisotropy in the a-plane, and has good crystal quality, so that high brightness can be realized, and thus for vehicles. By using it for lighting equipment such as lighting equipment, it is possible to reduce the number of chips and increase the output. Further, the semiconductor device is not limited to the LED, and may be a semiconductor laser, and has other uses such as a high electron mobility transistor (HEMT) having a functional layer for generating two-dimensional electron gas. You may.

本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

１０，２０…半導体成長用基板
１１，２１…ｒ面サファイア基板
１２，２２…バッファ層
１３…誘電体マスク
１４，２４…窒化物半導体層
１５ａ，１５ｂ，２５ａ，２５ｂ，２５ｃ…欠陥
１６…レジスト膜
１７…成長核
１８…活性層
１９…ｐ型半導体層
２１ａ…凸形状
３１…ｎ側電極
３２…ｐ側電極 10, 20 ... Semiconductor growth substrate 11,21 ... r-plane sapphire substrate 12, 22 ... Buffer layer 13 ... Dielectric mask 14, 24 ... Nitride semiconductor layer 15a, 15b, 25a, 25b, 25c ... Defect 16 ... Resist film 17 ... Growth nucleus 18 ... Active layer 19 ... P-type semiconductor layer 21a ... Convex shape 31 ... n-side electrode 32 ... p-side electrode

Claims (9)

ｒ面を主面とするｒ面サファイア基板と、
前記主面上に形成されたバッファ層と、
前記バッファ層上に形成された複数の誘電体マスクと、
前記バッファ層および前記誘電体マスクを覆って形成されたａ面を主面とする窒化物半導体層を備えることを特徴とする半導体成用長基板。 An r-plane sapphire substrate whose main surface is the r-plane,
The buffer layer formed on the main surface and
A plurality of dielectric masks formed on the buffer layer and
A semiconductor growth substrate comprising the nitride semiconductor layer having the a-plane formed over the buffer layer and the dielectric mask as a main surface. 請求項１に記載の半導体成長用基板であって、
前記誘電体マスクは、前記主面の面内方向における最大寸法が１．２μｍ未満、高さ方向の最大寸法が２μｍ未満であることを特徴とする半導体成長用基板。 The semiconductor growth substrate according to claim 1.
The dielectric mask is a semiconductor growth substrate, characterized in that the maximum dimension of the main surface in the in-plane direction is less than 1.2 μm and the maximum dimension in the height direction is less than 2 μm. 請求項１または２に記載の半導体成長用基板であって、
前記誘電体マスクは、ＳｉＯ２で構成されていることを特徴とする半導体成長用基板。 The semiconductor growth substrate according to claim 1 or 2.
The dielectric mask is a semiconductor growth substrate characterized by being composed of SiO 2 . 請求項１から３の何れか一つに記載の半導体成長用基板であって、
前記バッファ層は、ＡｌＮで構成されていることを特徴とする半導体成長用基板。 The semiconductor growth substrate according to any one of claims 1 to 3.
The buffer layer is a semiconductor growth substrate characterized by being composed of AlN. 請求項１から４の何れか一つに記載の半導体成長用基板であって、
前記窒化物半導体層は、ＧａＮで構成されていることを特徴とする半導体成長用基板。 The semiconductor growth substrate according to any one of claims 1 to 4.
The nitride semiconductor layer is a semiconductor growth substrate characterized by being made of GaN. 請求項１から５の何れか一つに記載の半導体成長用基板を用い、
前記半導体成長用基板上に機能層を備えることを特徴とする半導体素子。 Using the semiconductor growth substrate according to any one of claims 1 to 5,
A semiconductor device characterized in that a functional layer is provided on the semiconductor growth substrate. 請求項１から５の何れか一つに記載の半導体成長用基板を用い、
前記半導体成長用基板上に活性層を備えることを特徴とする半導体発光素子。 Using the semiconductor growth substrate according to any one of claims 1 to 5,
A semiconductor light emitting device comprising an active layer on the semiconductor growth substrate. ｒ面を主面とするｒ面サファイア基板の前記主面上にバッファ層を形成するバッファ層形成工程と、
前記バッファ層上に誘電体マスクを形成するマスク形成工程と、
前記誘電体マスクの間から露出する前記バッファ層からａ面を主面とする窒化物半導体層を成長させる下地層成長工程を備えることを特徴とする半導体成長用基板の製造方法。 A buffer layer forming step of forming a buffer layer on the main surface of the r-plane sapphire substrate having the r-plane as the main surface, and
A mask forming step of forming a dielectric mask on the buffer layer,
A method for manufacturing a semiconductor growth substrate, which comprises a base layer growth step for growing a nitride semiconductor layer having a surface a as a main surface from the buffer layer exposed between the dielectric masks. 請求項８に記載の半導体成長用基板の製造方法であって、
前記バッファ層形成工程では、スパッタ法を用いてＡｌＮで前記バッファ層を形成することを特徴とする半導体成長用基板の製造方法。 The method for manufacturing a semiconductor growth substrate according to claim 8.
The buffer layer forming step is a method for manufacturing a semiconductor growth substrate, which comprises forming the buffer layer with AlN by using a sputtering method.
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