JP2020202241A - Flip chip package, flip chip package substrate and method of manufacturing flip chip package - Google Patents

Flip chip package, flip chip package substrate and method of manufacturing flip chip package Download PDF

Info

Publication number
JP2020202241A
JP2020202241A JP2019106973A JP2019106973A JP2020202241A JP 2020202241 A JP2020202241 A JP 2020202241A JP 2019106973 A JP2019106973 A JP 2019106973A JP 2019106973 A JP2019106973 A JP 2019106973A JP 2020202241 A JP2020202241 A JP 2020202241A
Authority
JP
Japan
Prior art keywords
wiring board
chip package
wiring
flip
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019106973A
Other languages
Japanese (ja)
Other versions
JP7404665B2 (en
Inventor
浩功 野村
Hiroatsu Nomura
浩功 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2019106973A priority Critical patent/JP7404665B2/en
Publication of JP2020202241A publication Critical patent/JP2020202241A/en
Application granted granted Critical
Publication of JP7404665B2 publication Critical patent/JP7404665B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

To provide a flip chip package and a flip chip package substrate that are adaptable to narrow pitches and fine wiring and low in low manufacturing cost.SOLUTION: In a flip chip package 40 with two or more semiconductor chips mounted thereon, a second wiring board 5 having a smaller area than a first wiring board 3 is provided on a surface of the first wiring board on which semiconductor chips 6 and 7 are mounted. At least two of the semiconductor chips are electrically connected across both the first wiring board and the second wiring board, and are electrically connected to each other by wiring 10 formed on the second wiring board. The wire width, pitch, and via diameter of at least a part of the wiring formed on the second wiring board are smaller than the wire width, pitch, and via diameter of the wiring formed on the first wiring board.SELECTED DRAWING: Figure 1

Description

本発明は、フリップチップパッケージ、フリップチップパッケージ基板およびフリップチップパッケージの製造方法に関する。 The present invention relates to a flip chip package, a flip chip package substrate, and a method for manufacturing a flip chip package.

半導体製造プロセスの技術向上により、半導体チップは高機能化・高集積化が進み、ピン数も増加の一途を辿っている。これに対応するためフリップチッププロセスを利用した半導体パッケージ、すなわちフリップチップパッケージが開発されている。フリップチップパッケージの例を図５に示す。フリップチップパッケージは半導体チップ１の素子形成面全面に外部との電気的接続のための電極２を配置することができる。そのため、多ピン化に適しており、現在多くの半導体製品に採用されている。２３は半導体チップを搭載するためのフリップチップパッケージ基板、２４はフリップチップパッケージ基板２３をマザーボード等に実装するための電極を示す。 Due to technological improvements in the semiconductor manufacturing process, semiconductor chips are becoming more sophisticated and highly integrated, and the number of pins is steadily increasing. To cope with this, a semiconductor package using a flip chip process, that is, a flip chip package has been developed. An example of a flip chip package is shown in FIG. In the flip chip package, the electrode 2 for electrical connection with the outside can be arranged on the entire surface of the element forming surface of the semiconductor chip 1. Therefore, it is suitable for increasing the number of pins and is currently used in many semiconductor products. Reference numeral 23 denotes a flip chip package substrate for mounting a semiconductor chip, and 24 indicates an electrode for mounting the flip chip package substrate 23 on a motherboard or the like.

従来、フリップチップパッケージ基板には、絶縁樹脂と配線材料を交互に積層することで形成されるビルドアップ基板が多く用いられてきた。この樹脂製ビルドアップ基板は安価であり、微細な配線形成が可能であることなどから普及し、現在フリップチップパッケージ基板の主流となっている。 Conventionally, a build-up substrate formed by alternately laminating an insulating resin and a wiring material has been often used as a flip chip package substrate. This resin build-up substrate has become widespread because it is inexpensive and can form fine wiring, and is currently the mainstream of flip-chip package substrates.

近年、半導体チップの微細化がさらに進み、樹脂製のフリップチップパッケージ基板に対していくつかの問題が顕在化してきた。そのひとつが半導体チップの電極数の増加に伴う電極の狭ピッチ化である。従来、フリップチップパッケージに搭載される半導体チップの最小電極ピッチは１３０μｍから２００μｍ程度であった。しかし最近ではさらに電極ピッチの狭い半導体製品が出てきている。例えばＪＥＤＥＣで規格化されたＨＢＭ（Ｈｉｇｈ Ｂａｎｄｗｉｄｔｈ Ｍｅｍｏｒｙ）などは最小ピッチが５５μｍとなっている。電極が狭ピッチ化されることで、パッケージ基板側の電極に接続される信号配線も微細化が要求される。しかし樹脂製の基板は元々吸湿や熱処理による伸縮が大きいため、微細配線の形成が難しいという問題がある。 In recent years, the miniaturization of semiconductor chips has further progressed, and some problems have become apparent with respect to resin flip-chip package substrates. One of them is the narrowing of the electrode pitch as the number of electrodes in the semiconductor chip increases. Conventionally, the minimum electrode pitch of a semiconductor chip mounted on a flip chip package has been about 130 μm to 200 μm. However, recently, semiconductor products with a narrower electrode pitch have appeared. For example, HBM (High Bandwidth Memory) standardized by JEDEC has a minimum pitch of 55 μm. By narrowing the pitch of the electrodes, the signal wiring connected to the electrodes on the package substrate side is also required to be miniaturized. However, since the resin substrate originally has a large expansion and contraction due to moisture absorption and heat treatment, there is a problem that it is difficult to form fine wiring.

このような樹脂基板の問題を回避するための先行技術として、特許文献１に、フリップチップパッケージ基板に２つ以上の半導体チップを搭載する場合において、フリップチップパッケージ基板に、半導体チップ間を電気的に接続可能とする小さな多層配線基板であるインターコネクトブリッジを埋め込み、そのブリッジを介して半導体チップ間の信号や電源の接続を行う技術が開示されている。ブリッジはフリップチップパッケージ基板とは別に製造することができるため、狭ピッチや微細配線に適した材料や工法を適用することができる。 As a prior art for avoiding such a problem of a resin substrate, Patent Document 1 states that when two or more semiconductor chips are mounted on a flip chip package substrate, the flip chip package substrate is electrically connected between the semiconductor chips. There is disclosed a technique of embedding an interconnect bridge, which is a small multilayer wiring board that can be connected to a semiconductor chip, and connecting a signal or a power supply between semiconductor chips via the bridge. Since the bridge can be manufactured separately from the flip-chip package substrate, materials and construction methods suitable for narrow pitches and fine wiring can be applied.

しかし特許文献１の方法では、フリップチップパッケージ基板のブリッジを埋め込む部分に凹部を、フリップチップパッケージ基板の上面とブリッジの上面を面一に形成して、その面に形成した配線による結線を可能にしておく必要があり、工程が複雑になることで高コストになる、という問題があった。 However, in the method of Patent Document 1, a recess is formed in the portion of the flip-chip package substrate in which the bridge is embedded, and the upper surface of the flip-chip package substrate and the upper surface of the bridge are formed flush with each other, enabling wiring by wiring formed on the surfaces. There is a problem that it is necessary to keep it, and the cost becomes high due to the complicated process.

特許第５８７６０９３号公報Japanese Patent No. 5876093

上記の問題を解決するため、高コストとなる複雑な工程を使用せずに、２つ以上の半導体チップを搭載可能とする狭ピッチな微細配線に対応可能なフリップチップパッケージおよびフリップチップパッケージ基板を提供する事を課題とする。 In order to solve the above problems, flip-chip packages and flip-chip package substrates that can support narrow-pitch fine wiring that can mount two or more semiconductor chips without using complicated processes that are expensive. The issue is to provide.

上記課題を解決する手段として、本発明の請求項１に記載の発明は、２つ以上の半導体チップを搭載するフリップチップパッケージにおいて、
第一の配線基板の半導体チップを搭載する側の面に、第一の配線基板よりも面積の小さい第二の配線基板が備えられており、
半導体チップのうち少なくとも２つは、第一の配線基板と第二の配線基板の両方に跨って電気的に接続されているとともに、第二の配線基板に形成された配線によって相互に電気的に接続されており、
第二の配線基板に形成された少なくとも一部の、配線の線幅とピッチは、第一の配線基板に形成された配線の線幅とピッチより小さいことを特徴とするフリップチップパッケージである。 As a means for solving the above problems, the invention according to claim 1 of the present invention is a flip chip package in which two or more semiconductor chips are mounted.
A second wiring board having a smaller area than the first wiring board is provided on the surface of the first wiring board on the side where the semiconductor chip is mounted.
At least two of the semiconductor chips are electrically connected across both the first wiring board and the second wiring board, and are electrically connected to each other by the wiring formed on the second wiring board. Connected and
The flip-chip package is characterized in that the line width and pitch of the wiring formed on the second wiring board are smaller than the line width and pitch of the wiring formed on the first wiring board.

また、請求項２に記載の発明は、前記第一の配線基板と第二の配線基板の両方に跨って電気的に接続される半導体チップは、前記第一の配線基板との対向距離と、前記第二の配線基板との対向距離と、が１０μｍ以上１００μｍ以下異なることを特徴とする請求項１に記載のフリップチップパッケージである。 Further, according to the second aspect of the present invention, the semiconductor chip electrically connected across both the first wiring board and the second wiring board has the opposite distance to the first wiring board and the distance between the semiconductor chip and the first wiring board. The flip-chip package according to claim 1, wherein the facing distance from the second wiring board differs from 10 μm or more and 100 μm or less.

また、請求項３に記載の発明は、２つ以上の半導体チップを搭載するフリップチップパッケージに使用するフリップチップパッケージ基板であって、
多層配線積層体からなる、第一の配線基板と第二の配線基板を備えており、
第一の配線基板は、一方の面に、プリント配線基板との接続を行うパッドを備え、もう一方の面に、半導体チップとの接続を行うパッドを備えており、
第二の配線基板は、少なくとも２つの半導体チップとの接続を行うパッドを備えた面を上面にして第一の配線基板上に備えられており、
第二の配線基板により半導体チップ間が接続されていることを特徴とするフリップチップパッケージ基板である。 The invention according to claim 3 is a flip chip package substrate used for a flip chip package on which two or more semiconductor chips are mounted.
It has a first wiring board and a second wiring board made of a multi-layer wiring laminate.
The first wiring board is provided with a pad for connecting to the printed wiring board on one side and a pad for connecting to the semiconductor chip on the other side.
The second wiring board is provided on the first wiring board with the side having the pad for connecting to at least two semiconductor chips facing up.
It is a flip chip package substrate characterized in that semiconductor chips are connected by a second wiring board.

また、請求項４に記載の発明は、請求項１または２に記載のフリップチップパッケージの製造方法であって、
前記第二の配線基板を製造する工程と、
前記第一の配線基板と前記第二の配線基板とを接続することでフリップチップパッケージ基板を製造する工程と、
フリップチップパッケージ基板に接続用突起を形成する工程と、
接続用突起を形成したフリップチップパッケージ基板に半導体チップを実装する工程と、を備えており、
前記第二の配線基板を製造する工程は、
支持基板上に剥離層を形成した後、ビルドアップ工法により、最上部にパッドが配置される様に多層配線積層体を形成する工程と、
支持基板から多層配線積層体を剥離し、前記第一の配線基板の所定の位置に配置し固定する工程と、
前記半導体チップに、半導体チップと第一配線基板および第二配線基板とを電気的に接続する接続突起を形成する工程と、を備えていることを特徴とするフリップチップパッケージの製造方法である。 The invention according to claim 4 is the method for manufacturing a flip chip package according to claim 1 or 2.
The process of manufacturing the second wiring board and
A process of manufacturing a flip chip package substrate by connecting the first wiring board and the second wiring board, and
The process of forming connection protrusions on the flip chip package substrate,
It is equipped with a process of mounting a semiconductor chip on a flip-chip package substrate on which a protrusion for connection is formed.
The process of manufacturing the second wiring board is
After forming the release layer on the support substrate, the process of forming the multilayer wiring laminate so that the pad is arranged at the top by the build-up method,
A step of peeling the multilayer wiring laminate from the support substrate, arranging and fixing it at a predetermined position on the first wiring board, and
A method for manufacturing a flip chip package, which comprises a step of forming a connection protrusion for electrically connecting the semiconductor chip, a first wiring board, and a second wiring board to the semiconductor chip.

また、請求項５に記載の発明は、請求項１または２に記載のフリップチップパッケージの製造方法であって、
前記第二の配線基板を製造する工程と、
前記第一の配線基板と前記第二の配線基板とを接続することでフリップチップパッケージ基板を製造する工程と、
フリップチップパッケージ基板に接続用突起を形成する工程と、
接続用突起を形成したフリップチップパッケージ基板に半導体チップを実装する工程と、を備えており、
前記第二の配線基板を製造する工程は、
支持基板上に剥離層を形成した後、ビルドアップ工法により、最下部にパッドが配置される様に多層配線積層体を形成する工程と、
支持基板上に形成された多層配線積層体を前記第一の配線基板の所定の位置に配置し固定した後、支持基板を剥離する工程と、
前記半導体チップに、半導体チップと第一配線基板および第二配線基板とを電気的に接続する接続突起を形成する工程と、を備えていることを特徴とするフリップチップパッケージの製造方法である。 The invention according to claim 5 is the method for manufacturing a flip chip package according to claim 1 or 2.
The process of manufacturing the second wiring board and
A process of manufacturing a flip chip package substrate by connecting the first wiring board and the second wiring board, and
The process of forming connection protrusions on the flip chip package substrate,
It is equipped with a process of mounting a semiconductor chip on a flip-chip package substrate on which a protrusion for connection is formed.
The process of manufacturing the second wiring board is
After forming the release layer on the support substrate, the process of forming the multilayer wiring laminate so that the pad is arranged at the bottom by the build-up method,
A step of arranging and fixing the multilayer wiring laminate formed on the support substrate at a predetermined position of the first wiring board and then peeling off the support substrate.
A method for manufacturing a flip chip package, which comprises a step of forming a connection protrusion for electrically connecting the semiconductor chip, a first wiring board, and a second wiring board to the semiconductor chip.

本発明のフリップチップパッケージによれば、第一の配線基板よりも面積の小さい第二の配線基板が第一の配線基板上に備えられており、２つ以上の半導体チップのうち、少なくとも２つの半導体チップが、第一の配線基板と第二の配線基板に跨って接続されており、それらの半導体チップが第二の配線基板を介して接続されている。この第二の配線基板は、良好な平面性を備えた支持基板上にビルドアップ工法により形成された多層積層体である為、狭ピッチな微細配線に対応可能である。その為、半導体チップの電極数の増加に伴う電極の狭ピッチ化に対応可能である。その際、第二の配線基板を第一の配線基板に埋め込む必要がないため、工程が複雑になること無く、安価な半導体パッケージを製造する事ができる。 According to the flip chip package of the present invention, a second wiring board having a smaller area than the first wiring board is provided on the first wiring board, and at least two of two or more semiconductor chips are provided. The semiconductor chips are connected across the first wiring board and the second wiring board, and the semiconductor chips are connected via the second wiring board. Since this second wiring board is a multi-layer laminated body formed by a build-up method on a support substrate having good flatness, it can be used for fine wiring with a narrow pitch. Therefore, it is possible to cope with the narrowing of the electrode pitch as the number of electrodes of the semiconductor chip increases. At that time, since it is not necessary to embed the second wiring board in the first wiring board, it is possible to manufacture an inexpensive semiconductor package without complicating the process.

また、本発明のフリップチップパッケージ基板によれば、フリップチップパッケージ基板の半導体チップとの接続電極であるパッドに、接続用突起を形成し、そこに半導体チップを接合することにより、本発明のフリップチップパッケージを製造することができる。 Further, according to the flip-chip package substrate of the present invention, the flip-chip package substrate of the present invention is flipped by forming a connection protrusion on a pad which is a connection electrode of the flip-chip package substrate with the semiconductor chip and joining the semiconductor chip to the protrusion. Chip packages can be manufactured.

また、本発明のフリップチップパッケージの製造方法によれば、本発明のフリップチップパッケージを製造可能とすることができる。 Further, according to the method for manufacturing a flip chip package of the present invention, the flip chip package of the present invention can be manufactured.

本発明のフリップチップパッケージを例示する断面説明図。An explanatory cross-sectional view illustrating the flip chip package of the present invention. 本発明のフリップチップパッケージの製造方法の一例を示す断面説明図。The cross-sectional explanatory view which shows an example of the manufacturing method of the flip chip package of this invention. 本発明のフリップチップパッケージの製造方法の一例を示す断面説明図。The cross-sectional explanatory view which shows an example of the manufacturing method of the flip chip package of this invention. 本発明の実施例。Examples of the present invention. 従来のフリップチップパッケージを例示する断面図。Sectional drawing which illustrates the conventional flip chip package.

＜フリップチップパッケージ＞
本発明のフリップチップパッケージの実施形態の一例を、図１を用いて説明する。 <Flip chip package>
An example of an embodiment of the flip chip package of the present invention will be described with reference to FIG.

図１は、本発明のフリップチップパッケージ４０の一実施形態を示す断面図である。第一の配線基板３の半導体チップを搭載する側の面１５に、第一の配線基板３よりも面積の小さい第二の配線基板５が備えられている。 FIG. 1 is a cross-sectional view showing an embodiment of the flip chip package 40 of the present invention. A second wiring board 5 having a smaller area than the first wiring board 3 is provided on the surface 15 of the first wiring board 3 on the side on which the semiconductor chip is mounted.

第一の半導体チップ６は、接続用突起８によって第二の配線基板５のパッド１７に電気的に接続され、別の接続用突起９によって第一の配線基板３のパッド１１に電気的に接続されている。 The first semiconductor chip 6 is electrically connected to the pad 17 of the second wiring board 5 by the connection protrusion 8, and is electrically connected to the pad 11 of the first wiring board 3 by another connection protrusion 9. Has been done.

第二の半導体チップ７は、第一の半導体チップ６と同様に、接続用の突起８によって第二の配線基板５に電気的に接続され、別の接続用突起９によって第一の配線基板３に電気的に接続されている。 Like the first semiconductor chip 6, the second semiconductor chip 7 is electrically connected to the second wiring board 5 by the connecting protrusion 8, and the first wiring board 3 is electrically connected to the second wiring board 5 by another connecting protrusion 9. Is electrically connected to.

第一の半導体チップ６と第二の半導体チップ７は、第二の配線基板５に形成されたパッド１７とビア１６と配線１０によって相互に電気的に接続されている。また、同時に第一の配線基板３に形成されたパッド１１とビア１２と配線１３とビア１４を介して、第一の配線基板３の半導体チップが接続、または搭載された面とは反対側の面のパッド４に電気的に接続されている。図１では、第一の配線基板３はパッド２層と配線１層、また第二の配線基板５はパッド１層と配線１層の例を示しているが、配線の層数は必要に応じ増減が可能である。 The first semiconductor chip 6 and the second semiconductor chip 7 are electrically connected to each other by a pad 17, a via 16, and a wiring 10 formed on the second wiring board 5. At the same time, the semiconductor chip of the first wiring board 3 is connected or mounted on the side opposite to the surface to which the semiconductor chip of the first wiring board 3 is connected or mounted via the pad 11, the via 12, the wiring 13 and the via 14 formed on the first wiring board 3. It is electrically connected to the pad 4 on the surface. In FIG. 1, the first wiring board 3 shows an example of two pads and one layer of wiring, and the second wiring board 5 shows an example of one layer of pads and one layer of wiring, but the number of wiring layers may be as required. It can be increased or decreased.

半導体チップ６及び７は、例えば、片方がＧＰＵ（Ｇｒａｐｈｉｃ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）、もう片方がＨＢＭであっても良い。この場合、接続用突起８の配列ピッチは、従来の樹脂製フリップチップパッケージ基板のパッドピッチよりも非常に狭くなり、樹脂製フリップチップパッケージ基板の製造技術では製造が難しい。しかしながら本発明の第二の配線基板５は、平面性が良好なガラス基板などの支持基板上に形成する小さい多層配線基板（または、多層配線積層体）であることで、狭ピッチ微細構造に適した工程で製造できるため、問題なく半導体チップ６及び７を実装することができる。一方、接続用突起８、９は従来の樹脂製フリップチップパッケージのパッドピッチに合わせて設計されるため、問題なく実装可能である。 The semiconductor chips 6 and 7 may have, for example, one GPU (Graphic Processing Unit) and the other HBM. In this case, the arrangement pitch of the connecting protrusions 8 is much narrower than the pad pitch of the conventional resin flip-chip package substrate, and it is difficult to manufacture the resin flip-chip package substrate by the manufacturing technique. However, the second wiring board 5 of the present invention is a small multilayer wiring board (or multilayer wiring laminate) formed on a support substrate such as a glass substrate having good flatness, and is suitable for a narrow pitch microstructure. Since it can be manufactured in the same process, the semiconductor chips 6 and 7 can be mounted without any problem. On the other hand, since the connecting protrusions 8 and 9 are designed according to the pad pitch of the conventional resin flip-chip package, they can be mounted without any problem.

この構造では、半導体チップ６及び７から第一の配線基板３までの対向距離１８と、同じく半導体チップ６及び７から第二の配線基板５までの対向距離１９とは、第二の配線基板５の厚さの分だけ異なる。具体的には、接続突起９を接続突起８より第二の配線基板５の厚さ分だけ上乗せした厚さとして、半導体チップ６、７が第一の配線基板の表面に略平行となる様にすることで、半導体チップ６、７を実装可能としている。 In this structure, the facing distance 18 from the semiconductor chips 6 and 7 to the first wiring board 3 and the facing distance 19 from the semiconductor chips 6 and 7 to the second wiring board 5 are the second wiring board 5. It differs by the thickness of. Specifically, the thickness of the connecting protrusion 9 is increased by the thickness of the second wiring board 5 from the connecting protrusion 8 so that the semiconductor chips 6 and 7 are substantially parallel to the surface of the first wiring board. By doing so, the semiconductor chips 6 and 7 can be mounted.

＜フリップチップパッケージ基板＞
本発明のフリップチップパッケージ基板は、図１に例示した様な、２つ以上の半導体チップを搭載するフリップチップパッケージ４０に使用するフリップチップパッケージ基板３０（図２（ｄ）および図３（ｄ）参照）である。 <Flip chip package board>
The flip-chip package substrate of the present invention is the flip-chip package substrate 30 (FIGS. 2D and 3D) used for the flip-chip package 40 on which two or more semiconductor chips are mounted, as illustrated in FIG. See).

本発明のフリップチップパッケージ基板３０は、多層配線積層体からなる、第一の配線基板３と第二の配線基板５を備えている。 The flip-chip package substrate 30 of the present invention includes a first wiring board 3 and a second wiring board 5 made of a multilayer wiring laminate.

第一の配線基板３は、一方の面に、狭ピッチな微細配線では無いマザーボードの様なプリント配線基板との接続を行うパッド４を備え、もう一方の面に、狭ピッチなパッドを備えた半導体チップ６、７との接続を行うパッド１１を備えている。 The first wiring board 3 is provided with a pad 4 on one surface for connecting to a printed wiring board such as a motherboard, which is not a narrow-pitch fine wiring, and is provided with a narrow-pitch pad on the other surface. A pad 11 for connecting to the semiconductor chips 6 and 7 is provided.

第二の配線基板５は、少なくとも２つの半導体チップ６、７との接続を行うパッド１７を備えた面を上面にして第一の配線基板３上に備えられている。 The second wiring board 5 is provided on the first wiring board 3 with the surface provided with the pads 17 for connecting to at least two semiconductor chips 6 and 7 facing up.

第二の配線基板５により、少なくとも２つ半導体チップ６、７間が接続可能となることが特徴である。 The second wiring board 5 is characterized in that at least two semiconductor chips 6 and 7 can be connected to each other.

＜フリップチップパッケージの製造方法＞
（第一の実施形態）
次に、本発明のフリップチップパッケージの製造方法の第一の実施形態を、図２を用いて説明する。
図２（ａ）は、支持基板２０の片面に第二の配線基板５を多面付けで形成した断面図である。第二の配線基板５は、絶縁層と金属配線層（配線層とも記す。）を交互に積層し、パッド１７と配線層をビアで接続することで得られる。図２（ａ）はパッド１層、配線１層の場合を示しており、絶縁層を２１、配線層を１０、パッドを１７、ビアを１６で示している。配線の層数は必要に応じて増やしても良い。絶縁層の材料はシリコン酸化膜、エポキシ樹脂等が使用でき、配線１０は、銅、アルミ、コバルト等が使用できる。 <Manufacturing method of flip chip package>
(First Embodiment)
Next, the first embodiment of the method for manufacturing a flip chip package of the present invention will be described with reference to FIG.
FIG. 2A is a cross-sectional view in which the second wiring board 5 is formed on one side of the support board 20 by multi-imposition. The second wiring board 5 is obtained by alternately stacking an insulating layer and a metal wiring layer (also referred to as a wiring layer), and connecting the pad 17 and the wiring layer with vias. FIG. 2A shows the case of one pad layer and one wiring layer, and the insulating layer is shown by 21, the wiring layer is shown by 10, the pad is shown by 17, and the via is shown by 16. The number of wiring layers may be increased as needed. Silicon oxide film, epoxy resin or the like can be used as the material of the insulating layer, and copper, aluminum, cobalt or the like can be used for the wiring 10.

第二の配線基板５となる多層配線積層体の厚さは、およそ１０μｍ以上１００μｍ以下となり非常に薄いため、何らかの支持基板上に作製することが望ましい。支持基板２０としては、ガラス、シリコン等が使用できる。これらの支持基板材料は、平坦性が良好である事に加え、熱や吸湿による寸法変化が少ないため、狭ピッチ及び微細配線を形成するにあたって有利となる。支持基板２０の平坦性は、例えば、２５ｍｍ角の範囲で最大ふれ式平面度が０．５μｍ〜２．０μｍ以下であれば良い。この様な平面度を備えたガラス基板は、フロートガラスを研磨する事によって得られ、困難なく入手することができる。 Since the thickness of the multilayer wiring laminate to be the second wiring board 5 is about 10 μm or more and 100 μm or less, which is very thin, it is desirable to fabricate it on some kind of support substrate. As the support substrate 20, glass, silicon, or the like can be used. In addition to having good flatness, these support substrate materials have little dimensional change due to heat or moisture absorption, which is advantageous in forming narrow pitches and fine wiring. The flatness of the support substrate 20 may be, for example, as long as the maximum contact flatness is 0.5 μm to 2.0 μm or less in the range of 25 mm square. A glass substrate having such flatness can be obtained by polishing float glass and can be obtained without difficulty.

作製手順は、まず、支持基板２０上に剥離層２２を形成し、その上に絶縁層、配線層、さらに絶縁層、ビア、パッドの順に形成し、第二の配線基板５となる積層体を形成する。 In the manufacturing procedure, first, a release layer 22 is formed on the support substrate 20, an insulating layer, a wiring layer, an insulating layer, a via, and a pad are formed in this order on the release layer 22, and a laminated body to be a second wiring board 5 is formed. Form.

積層体の形成方法は、ダマシン工法、セミアディティブ工法など、必要とされる配線ルールに応じて既存の工法を適宜選択可能である。また剥離層２２は、紫外線照射、レーザー照射、加熱等によって接着性が無くなる既存の材料が使用できる。支持基板２０にガラスを用いれば、紫外線照射やレーザー照射も問題なく実施可能である。 As the method for forming the laminated body, an existing method can be appropriately selected according to the required wiring rules such as the damascene method and the semi-additive method. Further, as the release layer 22, an existing material whose adhesiveness is lost by ultraviolet irradiation, laser irradiation, heating or the like can be used. If glass is used for the support substrate 20, ultraviolet irradiation and laser irradiation can be performed without any problem.

次に、図２（ｂ）に示すように、多面付けされた第二の配線基板５を個片ごとに切り離す。切り離しにはダイサー等の装置が使用できる。 Next, as shown in FIG. 2B, the multi-imposed second wiring board 5 is separated into individual pieces. A device such as a dicer can be used for disconnection.

次に、図２（ｃ）に示すように、支持基板２０から第二の配線基板５を剥離する。剥離は、剥離層２２と絶縁層２１の境界面で行われる。 Next, as shown in FIG. 2C, the second wiring board 5 is peeled off from the support board 20. The peeling is performed at the interface between the peeling layer 22 and the insulating layer 21.

次に、図２（ｄ）に示すように、個片化された第二の配線基板５を第一の配線基板３に載置し、固定（接着）する。この様にして、本発明のフリップチップパッケージ基板３０を作製することができる。
載置する作業は、第二の配線基板５を吸着または把持可能な手段をロボットアームの先端に備えた専用装置を使用して、位置決めした後、第一の配線基板上の所定の位置に載置すれば良い。位置決め治具を使用して、マニュアルで第一の配線基板３上の所定の位置に載置することも可能である。固定にあたっては、熱硬化性接着剤などを用いて接着する。 Next, as shown in FIG. 2D, the individualized second wiring board 5 is placed on the first wiring board 3 and fixed (adhered). In this way, the flip chip package substrate 30 of the present invention can be manufactured.
In the mounting operation, after positioning using a dedicated device provided at the tip of the robot arm with a means capable of sucking or gripping the second wiring board 5, the mounting is performed at a predetermined position on the first wiring board. Just put it. It is also possible to manually place it at a predetermined position on the first wiring board 3 by using a positioning jig. When fixing, it is adhered using a thermosetting adhesive or the like.

次に、図２（ｅ）に示すように、半導体チップ６及び７を第一の配線基板３及び第二の配線基板５に接続する。この様にして、本発明のフリップチップパッケージ４０を作製することができる。
接続は接続用突起８、９によって行われる。このとき、半導体チップ６、７から第一の配線基板３までの対向距離（半導体チップ６、７と第一の配線基板３との向き合った面間の距離）１８と、同じく半導体チップ６及び７から第二の配線基板５までの対向距離（半導体チップ６、７と第二の配線基板５との向き合った面間の距離）１９は、第二の配線基板５の厚さの分だけ異なる。そのため接続用突起８と、接続用突起９は、第二の配線基板５の厚さ（およそ１０μｍ以上１００μｍ以下）の分だけ異なる高さとする。接続用突起
８、９の形成方法については後述する。 Next, as shown in FIG. 2E, the semiconductor chips 6 and 7 are connected to the first wiring board 3 and the second wiring board 5. In this way, the flip chip package 40 of the present invention can be manufactured.
The connection is made by the connecting protrusions 8 and 9. At this time, the facing distance (distance between the facing surfaces of the semiconductor chips 6 and 7 and the first wiring board 3) 18 from the semiconductor chips 6 and 7 to the first wiring board 3 and the semiconductor chips 6 and 7 are also the same. The facing distance (distance between the facing surfaces of the semiconductor chips 6 and 7 and the second wiring board 5) 19 from the second wiring board 5 to the second wiring board 5 differs by the thickness of the second wiring board 5. Therefore, the connecting protrusion 8 and the connecting protrusion 9 have different heights by the thickness of the second wiring board 5 (about 10 μm or more and 100 μm or less). The method of forming the connecting protrusions 8 and 9 will be described later.

（第二の実施形態）
次に、第二の実施形態を、図３を用いて説明する。
図３（ａ）は、支持基板２０の片面に第二の配線基板５´を多面付けで形成した断面図である。第一の実施形態と同様に、第二の配線基板５は絶縁層２１と金属配線層１０を交互に積層し、パッド１７と配線層１０をビア１６で接続することで得られる。図３（ａ）では、パッド１層、配線１層の場合を示している。配線の層数は必要に応じて増やしても良い。絶縁層２１の材料はシリコン酸化膜、エポキシ樹脂等が使用でき、配線は銅、アルミ、コバルト等が使用できる。 (Second embodiment)
Next, the second embodiment will be described with reference to FIG.
FIG. 3A is a cross-sectional view in which the second wiring board 5'is formed on one side of the support board 20 by multi-imposition. Similar to the first embodiment, the second wiring board 5 is obtained by alternately stacking the insulating layer 21 and the metal wiring layer 10 and connecting the pad 17 and the wiring layer 10 with the via 16. FIG. 3A shows the case of one pad layer and one wiring layer. The number of wiring layers may be increased as needed. Silicon oxide film, epoxy resin or the like can be used as the material of the insulating layer 21, and copper, aluminum, cobalt or the like can be used for the wiring.

第二の配線基板５となる多層配線積層体は、およそ１０μｍ以上１００μｍ以下となり非常に薄いため、何らかの支持基板上に作製することが望ましい。支持基板２０としては、ガラス、シリコン等が使用できる。これらの支持基板材料は、平坦性が良好である事に加え、熱や吸湿による寸法変化が少ないため、狭ピッチ及び微細配線を形成するにあたって有利となる。支持基板２０の平坦性は、例えば、２５ｍｍ角の範囲で最大ふれ式平面度が０．５μｍ〜２．０μｍ以下であれば良い。この様な平面度を備えたガラス基板は、フロートガラスを研磨する事によって得られ、困難なく入手することができる。 Since the multilayer wiring laminate to be the second wiring board 5 is about 10 μm or more and 100 μm or less and is very thin, it is desirable to fabricate it on some kind of support substrate. As the support substrate 20, glass, silicon, or the like can be used. In addition to having good flatness, these support substrate materials have little dimensional change due to heat or moisture absorption, which is advantageous in forming narrow pitches and fine wiring. The flatness of the support substrate 20 may be, for example, as long as the maximum contact flatness is 0.5 μm to 2.0 μm or less in the range of 25 mm square. A glass substrate having such flatness can be obtained by polishing float glass and can be obtained without difficulty.

作製手順は、支持基板２０上に剥離層２２を形成し、その上にパッド、絶縁層、ビア、配線層、さらに絶縁層の順で第二の配線基板５となる多層配線積層体を形成する。 In the manufacturing procedure, a release layer 22 is formed on the support substrate 20, and a multi-layer wiring laminate that becomes the second wiring board 5 in the order of a pad, an insulating layer, a via, a wiring layer, and an insulating layer is formed on the release layer 22. ..

多層配線積層体の形成方法は、ダマシン工法、セミアディティブ工法など、必要とされる配線ルールに応じて既存の工法を適宜選択可能である。また剥離層２２は、紫外線照射、レーザー照射、加熱等によって接着性が無くなる既存の材料が使用できる。支持基板２０にガラス基板を用いれば、紫外線照射やレーザー照射も問題なく実施可能である。 As the method for forming the multilayer wiring laminate, an existing construction method can be appropriately selected according to the required wiring rules such as the damascene construction method and the semi-additive construction method. Further, as the release layer 22, an existing material whose adhesiveness is lost by ultraviolet irradiation, laser irradiation, heating or the like can be used. If a glass substrate is used as the support substrate 20, ultraviolet irradiation and laser irradiation can be performed without any problem.

次に、図３（ｂ）に示すように、多面付けされた第二の配線基板５´を個片に切り離す。切り離しにはダイサー等の装置が使用できる。 Next, as shown in FIG. 3B, the multi-faceted second wiring board 5'is separated into individual pieces. A device such as a dicer can be used for disconnection.

次に、図３（ｃ）に示すように、個片化された第二の配線基板５´を第一の配線基板３に載置し、固定する。載置する作業は、第一の実施形態と同様に実施することができる。固定にあたっては、熱硬化性接着剤などが使用できる。 Next, as shown in FIG. 3C, the individualized second wiring board 5'is placed on the first wiring board 3 and fixed. The loading operation can be carried out in the same manner as in the first embodiment. For fixing, a thermosetting adhesive or the like can be used.

次に、図３（ｄ）に示すように、支持基板２０を第二の配線基板５´から剥離する。剥離は絶縁層２１の境界面で行われる。 Next, as shown in FIG. 3D, the support substrate 20 is peeled off from the second wiring board 5'. The peeling is performed at the boundary surface of the insulating layer 21.

次に、図３（ｅ）に示すように、半導体チップ６、７を第一の配線基板３及び第二の配線基板５に接続する。接続は接続用突起８、９によって行われる。このとき、半導体チップ６、７から第一の配線基板３までの対向距離１８と、同じく半導体チップ６、７から第二の配線基板５までの対向距離１９は、第二の配線基板５の厚さの分だけ異なる。そのため接続用突起８と接続用突起９は、第二の配線基板５の厚さ（およそ１０μｍ以上１００μｍ以下）の分だけ異なる高さとする。接続用突起８、９の形成方法については後述する。 Next, as shown in FIG. 3E, the semiconductor chips 6 and 7 are connected to the first wiring board 3 and the second wiring board 5. The connection is made by the connecting protrusions 8 and 9. At this time, the facing distance 18 from the semiconductor chips 6 and 7 to the first wiring board 3 and the facing distance 19 from the semiconductor chips 6 and 7 to the second wiring board 5 are the thickness of the second wiring board 5. It's different by the amount. Therefore, the connecting protrusion 8 and the connecting protrusion 9 have different heights by the thickness of the second wiring board 5 (about 10 μm or more and 100 μm or less). The method of forming the connecting protrusions 8 and 9 will be described later.

（接続用突起の形成方法）
次に接続用突起の形成方法の例について図４を用いて説明する。まず、接続用突起８、９を半導体チップ６及び７に形成する。 (Method of forming connection protrusions)
Next, an example of a method for forming the connecting protrusion will be described with reference to FIG. First, the connecting protrusions 8 and 9 are formed on the semiconductor chips 6 and 7.

接続用突起８、９の形成方法は、はんだ印刷、はんだボール搭載、電解銅めっきによる
銅ポストなどの工法が利用できる。接続用突起９は接続用突起８より、第二の配線基板の厚さ分だけ高く形成する。 As a method for forming the connecting protrusions 8 and 9, a method such as solder printing, solder ball mounting, or a copper post by electrolytic copper plating can be used. The connection protrusion 9 is formed higher than the connection protrusion 8 by the thickness of the second wiring board.

はんだ印刷で形成する場合は、印刷回数を変えるなどして高さを調整することができる。具体的には、第二の配線基板への印刷回数を、第一の配線基板への印刷回数より少なくすれば良い。 When forming by solder printing, the height can be adjusted by changing the number of printings. Specifically, the number of times of printing on the second wiring board may be less than the number of times of printing on the first wiring board.

はんだボール搭載で形成する場合は、搭載するはんだボールの径を変えることで高さを調整することができる。具体的には、第二の配線基板に搭載するはんだボールの径を、第一の配線基板に搭載するはんだボールの径より小さくすれば良い。 When the solder balls are mounted, the height can be adjusted by changing the diameter of the solder balls to be mounted. Specifically, the diameter of the solder balls mounted on the second wiring board may be smaller than the diameter of the solder balls mounted on the first wiring board.

銅ポストで形成する場合は、電解銅めっきの時間を変えることで高さを調整することができる。具体的には、第二の配線基板への電解銅めっきの時間を、第一の配線基板への電解銅めっきの時間より短くすれば良い。 When forming with a copper post, the height can be adjusted by changing the time of electrolytic copper plating. Specifically, the time for electrolytic copper plating on the second wiring board may be shorter than the time for electrolytic copper plating on the first wiring board.

１・・・半導体チップ、２・・・電極、３・・・第一の配線基板、４・・・（プリント配線基板と接続する）パッド、５・・・第二の配線基板、６・・・半導体チップ、７・・・半導体チップ、８・・・接続用突起、９・・・接続用突起、１０・・・配線、１１・・・（第二の配線基板と接続する）パッド、１２・・・ビア、１３・・・配線、１４・・・ビア、１５・・・第一の配線基板の第二の配線基板と接続する面、１６・・・ビア、１７・・・パッド、１８・・・半導体チップと第一の配線基板との対向距離、１９・・・半導体チップと第二の配線基板との対向距離、２０・・・支持基板、２１・・・絶縁層、２２・・・剥離層、２３、３０・・・フリップチップパッケージ基板、２４・・・電極、４０・・・フリップチップパッケージ 1 ... Semiconductor chip, 2 ... Electrode, 3 ... First wiring board, 4 ... Pad (connected to printed wiring board), 5 ... Second wiring board, 6 ... -Semiconductor chip, 7 ... Semiconductor chip, 8 ... Connection protrusion, 9 ... Connection protrusion, 10 ... Wiring, 11 ... (Connecting to the second wiring board) Pad, 12 ... Via, 13 ... Wiring, 14 ... Via, 15 ... Surface connecting to the second wiring board of the first wiring board, 16 ... Via, 17 ... Pad, 18 ... The facing distance between the semiconductor chip and the first wiring board, 19 ... The facing distance between the semiconductor chip and the second wiring board, 20 ... Supporting board, 21 ... Insulation layer, 22 ... -Release layer, 23, 30 ... Flip chip package substrate, 24 ... Electrode, 40 ... Flip chip package

Claims (5)

２つ以上の半導体チップを搭載するフリップチップパッケージにおいて、
第一の配線基板の半導体チップを搭載する側の面に、第一の配線基板よりも面積の小さい第二の配線基板が備えられており、
半導体チップのうち少なくとも２つは、第一の配線基板と第二の配線基板の両方に跨って電気的に接続されているとともに、第二の配線基板に形成された配線によって相互に電気的に接続されており、
第二の配線基板に形成された少なくとも一部の、配線の線幅とピッチは、第一の配線基板に形成された配線の線幅とピッチより小さいことを特徴とするフリップチップパッケージ。 In a flip chip package that mounts two or more semiconductor chips
A second wiring board having a smaller area than the first wiring board is provided on the surface of the first wiring board on the side where the semiconductor chip is mounted.
At least two of the semiconductor chips are electrically connected across both the first wiring board and the second wiring board, and are electrically connected to each other by the wiring formed on the second wiring board. Connected and
A flip-chip package characterized in that the line width and pitch of the wiring formed on the second wiring board is smaller than the line width and pitch of the wiring formed on the first wiring board. 前記第一の配線基板と第二の配線基板の両方に跨って電気的に接続される半導体チップは、前記第一の配線基板との対向距離と、前記第二の配線基板との対向距離と、が１０μｍ以上１００μｍ以下異なることを特徴とする請求項１に記載のフリップチップパッケージ。 A semiconductor chip electrically connected across both the first wiring board and the second wiring board has a facing distance with the first wiring board and a facing distance with the second wiring board. The flip chip package according to claim 1, wherein the is different from 10 μm or more and 100 μm or less. ２つ以上の半導体チップを搭載するフリップチップパッケージに使用するフリップチップパッケージ基板であって、
多層配線積層体からなる、第一の配線基板と第二の配線基板を備えており、
第一の配線基板は、一方の面に、プリント配線基板との接続を行うパッドを備え、もう一方の面に、半導体チップとの接続を行うパッドを備えており、
第二の配線基板は、少なくとも２つの半導体チップとの接続を行うパッドを備えた面を上面にして第一の配線基板上に備えられており、
第二の配線基板により半導体チップ間が接続されていることを特徴とするフリップチップパッケージ基板。 A flip-chip package substrate used for a flip-chip package that mounts two or more semiconductor chips.
It has a first wiring board and a second wiring board made of a multi-layer wiring laminate.
The first wiring board is provided with a pad for connecting to the printed wiring board on one side and a pad for connecting to the semiconductor chip on the other side.
The second wiring board is provided on the first wiring board with the side having the pad for connecting to at least two semiconductor chips facing up.
A flip-chip package substrate characterized in that semiconductor chips are connected by a second wiring board. 請求項１または２に記載のフリップチップパッケージの製造方法であって、
前記第二の配線基板を製造する工程と、
前記第一の配線基板と前記第二の配線基板とを接続することでフリップチップパッケージ基板を製造する工程と、
フリップチップパッケージ基板に接続用突起を形成する工程と、
接続用突起を形成したフリップチップパッケージ基板に半導体チップを実装する工程と、を備えており、
前記第二の配線基板を製造する工程は、
支持基板上に剥離層を形成した後、ビルドアップ工法により、最上部にパッドが配置される様に多層配線積層体を形成する工程と、
支持基板から多層配線積層体を剥離し、前記第一の配線基板の所定の位置に配置し固定する工程と、
前記半導体チップに、半導体チップと第一配線基板および第二配線基板とを電気的に接続する接続突起を形成する工程と、を備えていることを特徴とするフリップチップパッケージの製造方法。 The method for manufacturing a flip chip package according to claim 1 or 2.
The process of manufacturing the second wiring board and
A process of manufacturing a flip chip package substrate by connecting the first wiring board and the second wiring board, and
The process of forming connection protrusions on the flip chip package substrate,
It is equipped with a process of mounting a semiconductor chip on a flip-chip package substrate on which a protrusion for connection is formed.
The process of manufacturing the second wiring board is
After forming the release layer on the support substrate, the process of forming the multilayer wiring laminate so that the pad is arranged at the top by the build-up method,
A step of peeling the multilayer wiring laminate from the support substrate, arranging and fixing it at a predetermined position on the first wiring board, and
A method for manufacturing a flip chip package, which comprises a step of forming a connection protrusion for electrically connecting the semiconductor chip, a first wiring board, and a second wiring board to the semiconductor chip. 請求項１または２に記載のフリップチップパッケージの製造方法であって、
前記第二の配線基板を製造する工程と、
前記第一の配線基板と前記第二の配線基板とを接続することでフリップチップパッケージ基板を製造する工程と、
フリップチップパッケージ基板に接続用突起を形成する工程と、
接続用突起を形成したフリップチップパッケージ基板に半導体チップを実装する工程と、を備えており、
前記第二の配線基板を製造する工程は、
支持基板上に剥離層を形成した後、ビルドアップ工法により、最下部にパッドが配置される様に多層配線積層体を形成する工程と、
支持基板上に形成された多層配線積層体を前記第一の配線基板の所定の位置に配置し固定した後、支持基板を剥離する工程と、
前記半導体チップに、半導体チップと第一配線基板および第二配線基板とを電気的に接続する接続突起を形成する工程と、を備えていることを特徴とするフリップチップパッケージの製造方法。 The method for manufacturing a flip chip package according to claim 1 or 2.
The process of manufacturing the second wiring board and
A process of manufacturing a flip chip package substrate by connecting the first wiring board and the second wiring board, and
The process of forming connection protrusions on the flip chip package substrate,
It is equipped with a process of mounting a semiconductor chip on a flip-chip package substrate on which a protrusion for connection is formed.
The process of manufacturing the second wiring board is
After forming the release layer on the support substrate, the process of forming the multilayer wiring laminate so that the pad is arranged at the bottom by the build-up method,
A step of arranging and fixing the multilayer wiring laminate formed on the support substrate at a predetermined position of the first wiring board and then peeling off the support substrate.
A method for manufacturing a flip chip package, which comprises a step of forming a connection protrusion for electrically connecting the semiconductor chip, a first wiring board, and a second wiring board to the semiconductor chip.
JP2019106973A 2019-06-07 2019-06-07 Flip chip package, flip chip package substrate and flip chip package manufacturing method Active JP7404665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019106973A JP7404665B2 (en) 2019-06-07 2019-06-07 Flip chip package, flip chip package substrate and flip chip package manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019106973A JP7404665B2 (en) 2019-06-07 2019-06-07 Flip chip package, flip chip package substrate and flip chip package manufacturing method

Publications (2)

Publication Number Publication Date
JP2020202241A true JP2020202241A (en) 2020-12-17
JP7404665B2 JP7404665B2 (en) 2023-12-26

Family

ID=73743500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019106973A Active JP7404665B2 (en) 2019-06-07 2019-06-07 Flip chip package, flip chip package substrate and flip chip package manufacturing method

Country Status (1)

Country Link
JP (1) JP7404665B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7399402B1 (en) 2022-11-10 2023-12-18 眞一 前田 Wiring structure of electronic components, connection method of electronic components

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261311A (en) * 2005-03-16 2006-09-28 Sony Corp Semiconductor device and its manufacturing method
JP2017092094A (en) * 2015-11-04 2017-05-25 富士通株式会社 Electronic device, method of manufacturing electronic device and electronic apparatus
JP2017228647A (en) * 2016-06-22 2017-12-28 富士通株式会社 Resin interposer, semiconductor device using the same, and method of manufacturing resin interposer
WO2018047861A1 (en) * 2016-09-08 2018-03-15 凸版印刷株式会社 Wiring board and method for manufacturing wiring board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6137196B2 (en) 2012-12-07 2017-05-31 信越化学工業株式会社 Interposer substrate and manufacturing method thereof
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9917043B2 (en) 2016-01-12 2018-03-13 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261311A (en) * 2005-03-16 2006-09-28 Sony Corp Semiconductor device and its manufacturing method
JP2017092094A (en) * 2015-11-04 2017-05-25 富士通株式会社 Electronic device, method of manufacturing electronic device and electronic apparatus
JP2017228647A (en) * 2016-06-22 2017-12-28 富士通株式会社 Resin interposer, semiconductor device using the same, and method of manufacturing resin interposer
WO2018047861A1 (en) * 2016-09-08 2018-03-15 凸版印刷株式会社 Wiring board and method for manufacturing wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7399402B1 (en) 2022-11-10 2023-12-18 眞一 前田 Wiring structure of electronic components, connection method of electronic components
WO2024101348A1 (en) * 2022-11-10 2024-05-16 眞一 前田 Electronic component wiring structure, and electronic component connection method

Also Published As

Publication number Publication date
JP7404665B2 (en) 2023-12-26

Similar Documents

Publication Publication Date Title
JP3961537B2 (en) Manufacturing method of semiconductor mounting wiring board and manufacturing method of semiconductor package
US6985362B2 (en) Printed circuit board and electronic package using same
TWI443791B (en) Method of manufacturing wiring board, method of manufacturing semiconductor device and wiring board
US20090017613A1 (en) Method of manufacturing interconnect substrate and semiconductor device
JP2004335641A (en) Method of manufacturing substrate having built-in semiconductor element
JP5367523B2 (en) Wiring board and method of manufacturing wiring board
JP2004343030A (en) Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board
TWI505756B (en) Printed circuit board and method for manufacturing the same
JP2007266111A (en) Semiconductor device, laminated semiconductor device using the same, base substrate, and semiconductor device manufacturing method
JP2009246367A (en) System and method of forming wafer scale package
JP4528715B2 (en) Semiconductor device and manufacturing method thereof
JP6444269B2 (en) Electronic component device and manufacturing method thereof
WO2007066563A1 (en) Printed wiring board with component-mounting pins and electronic equipment using the same
JP2004119729A (en) Method of manufacturing circuit device
JP7404665B2 (en) Flip chip package, flip chip package substrate and flip chip package manufacturing method
JP2018186121A (en) Semiconductor package substrate, semiconductor package, and semiconductor device
JP2007096337A (en) Wiring substrate for mounting semiconductor, semiconductor package, and its manufacturing method
JP2004119730A (en) Method of manufacturing circuit device
JP2009004813A (en) Wiring substrate for mounting semiconductor
JP2007142128A (en) Semiconductor device and its production process
JP2020004926A (en) Wiring board and manufacturing method thereof
JP4429280B2 (en) Manufacturing method of wiring board for mounting semiconductor, and manufacturing method of semiconductor device
TWI420996B (en) Printed circuit board and method of manufacturing the same
TWI420989B (en) Printed circuit board and method of manufacturing the same
JP2004320059A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220525

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230316

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230404

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20230522

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230613

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230803

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20231114

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20231127

R150 Certificate of patent or registration of utility model

Ref document number: 7404665

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150