JP2020092229A - Semiconductor device, manufacturing method of semiconductor device, and clip lead - Google Patents

Semiconductor device, manufacturing method of semiconductor device, and clip lead Download PDF

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JP2020092229A
JP2020092229A JP2018229906A JP2018229906A JP2020092229A JP 2020092229 A JP2020092229 A JP 2020092229A JP 2018229906 A JP2018229906 A JP 2018229906A JP 2018229906 A JP2018229906 A JP 2018229906A JP 2020092229 A JP2020092229 A JP 2020092229A
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semiconductor device
joint
chip
clip lead
bent
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JP7329919B2 (en
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大介 宮崎
Daisuke Miyazaki
大介 宮崎
奈津紀 竹原
Natsuki Takehara
奈津紀 竹原
洋平 篠竹
Yohei Shinotake
洋平 篠竹
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Shindengen Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8484—Sintering
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a semiconductor device, capable of conducting a relatively large current, yet highly resistant to thermal cycling stress.SOLUTION: A semiconductor device 1 includes: a chip 10; a first electrode unit 20; a second electrode unit 22; and a clip lead 100 having a first junction 110, a second junction 120, and a cross-linked unit 130. The cross-linked unit 130 has a flat plate unit 131 having a predetermined thickness, a first bending unit 132, and a second bending unit 133. The first junction 110 and the first bending unit 132 configure a thermal stress relief structure 140 for relieving thermal stress on the first junction member 30 between the chip 10 and the first junction 110. The thermal stress relief structure 140 has a structure in which at least the first junction 110 and the first bending unit 132 are thinner than the flat plate unit 131.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置、半導体装置の製造方法及びクリップリードに関する。 The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a clip lead.

従来、チップと電極部とを電気的に接続するクリップリードを備える半導体装置が知られている（例えば、特許文献１参照。）。 Conventionally, a semiconductor device including a clip lead that electrically connects a chip and an electrode portion is known (for example, refer to Patent Document 1).

図１１は、従来の半導体装置８００を示す図である。図１１中、符号８５０は接合部材を示し、符号Ｓは基板を示す。
従来の半導体装置８００は、図１１に示すように、一方の面及び他方の面にそれぞれ表面電極８１２，８１４を有するチップ８１０と、一方の面の表面電極８１２と電気的に接続されている第１電極部８２０と、第１電極部８２０と間隔をあけて配置された第２電極部８２２と、チップ８１０の他方の面の表面電極８１４と接合部材８３０を介して接合された第１接合部９１０、第１接合部９１０と間隔をあけて配置され、第２電極部８２２と接合部材８４０を介して接合された第２接合部９２０、及び、第１接合部９１０と第２接合部９２０とを架橋する架橋部９３０とを有し、チップ８１０と第２電極部８２２とを電気的に接続するクリップリード９００とを備える。第１電極部８２０と第２電極部８２２とは同一の基板上に配置されており、クリップリード９００においては、第１接合部９１０、第２接合部９２０及び架橋部９３０は、いずれも同じ厚さである。 FIG. 11 is a diagram showing a conventional semiconductor device 800. In FIG. 11, reference numeral 850 indicates a joining member, and reference numeral S indicates a substrate.
As shown in FIG. 11, a conventional semiconductor device 800 is electrically connected to a chip 810 having surface electrodes 812 and 814 on one surface and the other surface, and a surface electrode 812 on one surface. 1st electrode part 820, 2nd electrode part 822 arrange|positioned with the 1st electrode part 820 at intervals, 1st joining part joined by surface electrode 814 of the other surface of chip 810 via joining member 830 910, a second joining portion 920 that is arranged with a gap from the first joining portion 910, and is joined to the second electrode portion 822 via a joining member 840; and a first joining portion 910 and a second joining portion 920. And a clip lead 900 that electrically connects the chip 810 and the second electrode portion 822. The first electrode portion 820 and the second electrode portion 822 are arranged on the same substrate, and in the clip lead 900, the first joint portion 910, the second joint portion 920, and the bridging portion 930 all have the same thickness. That's it.

架橋部９３０は、所定の厚みを有する平板部９３１と、平板部９３１から下側に折り曲げられ、第１接合部９１０と接続されている第１折り曲げ部９３２と、平板部９３１から下側に折り曲げられ、第２接合部９２０と接続されている第２折り曲げ部９３３とを有する。 The bridge portion 930 includes a flat plate portion 931 having a predetermined thickness, a first bent portion 932 that is bent downward from the flat plate portion 931 and is connected to the first joint portion 910, and a flat plate portion 931 that is bent downward. And a second bent portion 933 connected to the second joint portion 920.

従来の半導体装置８００によれば、クリップリード９００によってチップ８１０と第２電極部８２２とを電気的に接続するため、ボンディングワイヤによってチップ８１０と第２電極部８２２とを電気的に接続した場合よりも大きな電流を導通可能な半導体装置となる。 According to the conventional semiconductor device 800, since the chip 810 and the second electrode portion 822 are electrically connected by the clip lead 900, compared to the case where the chip 810 and the second electrode portion 822 are electrically connected by the bonding wire. Also becomes a semiconductor device capable of conducting a large current.

特開２０１２−２１２７１２号公報JP 2012-212712 A

ところで近年、チップの性能が上がり、チップサイズが比較的小さく、かつ、定格電流が比較的大きいチップが登場したことに伴い、より大きな電流を導通可能で、かつ、小型化された電子機器が求められている。このような電子機器を実現するためには、クリップリードの断面積（電流の導通路に対する断面積）が大きく、より大きな電流を導通可能なクリップリードを用いる必要がある。 By the way, in recent years, the performance of chips has improved, and with the advent of chips with a relatively small chip size and a relatively large rated current, there has been a demand for electronic devices capable of conducting a larger current and downsized. Has been. In order to realize such an electronic device, it is necessary to use a clip lead having a large cross-sectional area (cross-sectional area with respect to a current conducting path) and capable of conducting a larger current.

しかしながら、単にクリップリードの断面積を大きくすると、クリップリードの第１接合部の厚さが大きくなるため、チップと第１接合部との間の接合部材(第１接合部材)に加わる応力が大きくなり、熱サイクルストレスに対する耐性が低下するおそれがある、という問題がある。 However, simply increasing the cross-sectional area of the clip lead increases the thickness of the first joint portion of the clip lead, so that the stress applied to the joint member (first joint member) between the chip and the first joint portion is large. Therefore, there is a risk that the resistance to thermal cycle stress may decrease.

そこで、本発明は上記した問題を解決するためになされたものであり、比較的大きな電流を導通可能でありながら熱サイクルストレスに対する耐性が高い半導体装置を提供することを目的とする。また、このような半導体装置を製造するための半導体装置の製造方法を提供することを目的とする。さらにまた、このような半導体装置に用いるクリップリードを提供することを目的とする。 Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of conducting a relatively large current and having high resistance to thermal cycle stress. Another object is to provide a method for manufacturing a semiconductor device for manufacturing such a semiconductor device. Still another object is to provide a clip lead used in such a semiconductor device.

［１］本発明の半導体装置は、一方の面及び他方の面にそれぞれ表面電極を有するチップと、前記チップの前記一方の面の前記表面電極と電気的に接続されている第１電極部と、前記第１電極部と間隔をあけて配置された第２電極部と、前記チップの前記他方の面の前記表面電極と第１接合部材を介して接合された第１接合部、前記第１接合部と間隔をあけて配置され、前記第２電極部と第２接合部材を介して接合された第２接合部、及び、前記第１接合部と前記第２接合部とを架橋する架橋部を有し、前記チップと前記第２電極部とを電気的に接続するクリップリードとを備え、前記架橋部は、所定の厚みを有する平板部と、前記平板部から下側に折り曲げられ、前記第１接合部と接続されている第１折り曲げ部と、前記平板部から前記下側に折り曲げられ、前記第２接合部と接続されている第２折り曲げ部とを有し、前記第１接合部及び前記第１折り曲げ部は、前記チップと前記第１接合部との間の前記第１接合部材に対する熱応力を緩和するための熱応力緩和構造を構成し、前記熱応力緩和構造は、少なくとも前記第１接合部及び前記第１折り曲げ部が前記平板部よりも薄くなるように構成された構造を含むことを特徴とする。 [1] A semiconductor device of the present invention includes a chip having surface electrodes on one surface and the other surface, and a first electrode portion electrically connected to the surface electrode on the one surface of the chip. A second electrode portion spaced apart from the first electrode portion, a first joint portion joined to the surface electrode on the other surface of the chip via a first joint member, the first joint portion, A second joint portion that is arranged with a gap from the joint portion and is joined to the second electrode portion via a second joint member, and a bridge portion that bridges the first joint portion and the second joint portion. And a clip lead that electrically connects the chip and the second electrode portion, the bridging portion is a flat plate portion having a predetermined thickness, and the flat plate portion is bent downward, A first bent portion connected to a first joint portion; and a second bent portion bent from the flat plate portion to the lower side and connected to the second joint portion, the first joint portion And the first bent portion constitutes a thermal stress relaxation structure for relaxing thermal stress on the first bonding member between the chip and the first bonding portion, and the thermal stress relaxation structure is at least the thermal stress relaxation structure. The first joining portion and the first bent portion may include a structure configured to be thinner than the flat plate portion.

［２］本発明の半導体装置において、前記熱応力緩和構造は、少なくとも前記第１接合部及び前記第１折り曲げ部が異形条材を折り曲げることによって形成された構造を含むことが好ましい。 [2] In the semiconductor device of the present invention, it is preferable that the thermal stress relaxation structure includes a structure in which at least the first joint portion and the first bent portion are formed by bending a profiled strip.

［３］本発明の半導体装置において、前記熱応力緩和構造は、前記第１接合部に対する前記第１折り曲げ部の傾斜角度が９０°〜１２０°の範囲内になるように構成された構造を含むことが好ましい。 [3] In the semiconductor device of the present invention, the thermal stress relaxation structure includes a structure in which an inclination angle of the first bent portion with respect to the first joint portion is within a range of 90° to 120°. Preferably.

［４］本発明の半導体装置においては、前記クリップリードにおいて、前記第１折り曲げ部の前記チップ側の面全体が前記第１接合部材と接していることが好ましい。 [4] In the semiconductor device of the present invention, in the clip lead, it is preferable that the entire surface of the first bent portion on the chip side is in contact with the first joining member.

［５］本発明の半導体装置においては、前記第１接合部において、前記第１接合部の厚みのうちの少なくとも半分の厚みまで前記第１接合部材に埋められていることが好ましい。 [5] In the semiconductor device of the present invention, it is preferable that at the first bonding portion, at least half the thickness of the first bonding portion is filled with the first bonding member.

［６］本発明の半導体装置において、前記第２接合部及び前記第２折り曲げ部は、いずれも前記平板部よりも薄いことが好ましい。 [6] In the semiconductor device of the present invention, it is preferable that both the second joint portion and the second bent portion are thinner than the flat plate portion.

［７］本発明の半導体装置において、前記第１接合部、前記第２接合部、前記第１折り曲げ部及び前記第２折り曲げ部は、いずれも同じ厚さであることが好ましい。 [7] In the semiconductor device of the present invention, it is preferable that the first joint portion, the second joint portion, the first bent portion, and the second bent portion all have the same thickness.

［８］本発明の半導体装置において、前記第２接合部及び前記第２折り曲げ部は、いずれも前記平板部と同じ厚さであることが好ましい。 [8] In the semiconductor device of the present invention, it is preferable that both the second joint portion and the second bent portion have the same thickness as the flat plate portion.

［９］本発明の半導体装置において、前記架橋部は、前記平板部と前記第１折り曲げ部との間に前記平板部よりも薄い肩部をさらに有することが好ましい。 [9] In the semiconductor device of the present invention, it is preferable that the bridging portion further has a shoulder portion thinner than the flat plate portion between the flat plate portion and the first bent portion.

［１０］本発明の半導体装置においては、前記肩部の下側の面と前記平板部の下側の面との間には段差部が形成されていることが好ましい。 [10] In the semiconductor device of the present invention, it is preferable that a step portion is formed between the lower surface of the shoulder portion and the lower surface of the flat plate portion.

［１１］本発明の半導体装置においては、前記第１接合部材と前記クリップリードとの接触面の端部が前記段差部にあることが好ましい。 [11] In the semiconductor device of the present invention, it is preferable that an end portion of a contact surface between the first bonding member and the clip lead is in the step portion.

［１２］本発明の半導体装置において、前記肩部は、側面から見て階段状の肩部であることが好ましい。 [12] In the semiconductor device of the present invention, it is preferable that the shoulder is a stepped shoulder when viewed from the side.

［１３］本発明の半導体装置においては、前記第１接合部において、前記チップと接合する面とは反対側の面に溝が形成されていることが好ましい。 [13] In the semiconductor device of the present invention, it is preferable that a groove is formed on a surface of the first bonding portion opposite to a surface bonded to the chip.

［１４］本発明の半導体装置の製造方法は、［１］〜［１３］のいずれかに記載の半導体装置を製造するための半導体装置の製造方法であって、第１接合部、前記第１接合部と間隔をあけて配置された第２接合部、及び、前記第１接合部と前記第２接合部とを架橋する架橋部を有し、前記架橋部は、所定の厚みを有する平板部と、前記平板部から一方側に折り曲げられ、前記第１接合部と接続されている第１折り曲げ部と、前記平板部から前記一方側に折り曲げられ、前記第２接合部と接続されている第２折り曲げ部とを有するクリップリードをチップ及び電極部上に接合部材を介して配置するクリップリード配置工程と、前記チップと前記第１接合部との間、及び、前記電極部と前記第２接合部との間をそれぞれ前記接合部材で接合する接合工程とを含み、前記クリップリード配置工程においては、前記クリップリードとして、前記第１接合部及び前記第１折り曲げ部が前記第１接合部と前記チップとの間の前記接合部材に対する熱応力を緩和するための熱応力緩和構造を構成するクリップリードを前記チップ及び前記電極部上に配置することを特徴とする。 [14] A semiconductor device manufacturing method according to the present invention is a semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of [1] to [13], wherein It has a 2nd joining part arranged at a gap with a joining part, and a bridge part which bridges the 1st joining part and the 2nd joining part, and the bridge part has a flat part which has a predetermined thickness. A first bent portion that is bent from the flat plate portion to one side and is connected to the first joint portion; and a first bent portion that is bent from the flat plate portion to the one side and is connected to the second joint portion. Clip lead disposing step of disposing a clip lead having two bent parts on the chip and the electrode part via a bonding member, between the chip and the first bonding part, and the electrode part and the second bonding And a joining step of joining each of the portions with a joining member by the joining member. In the clip lead arranging step, the first joining portion and the first bent portion serve as the clip leads and the first joining portion and the first joining portion. A clip lead forming a thermal stress relaxation structure for relaxing thermal stress on the joining member between the chip and the chip is arranged on the chip and the electrode portion.

［１５］本発明のクリップリードは、［１］〜［１３］のいずれかに記載の半導体装置に用いることを特徴とする。 [15] The clip lead of the present invention is used in the semiconductor device according to any one of [1] to [13].

本発明の半導体装置及びクリップリードによれば、架橋部は、所定の厚みを有する平板部を有するため、クリップリードの断面積（電流の導通路に対する断面積）が大きく、クリップリードは、比較的大きな電流を導通可能なクリップリードとなる。従って、チップサイズが小さく、かつ、定格電流が比較的大きいチップに対応したクリップリードとなり、その結果、比較的大きな電流を導通可能で、かつ、小型化された電子機器を実現することができる半導体装置及びクリップリードとなる。 According to the semiconductor device and the clip lead of the present invention, since the bridging portion has the flat plate portion having a predetermined thickness, the cross-sectional area of the clip lead (the cross-sectional area for the current conducting path) is large, and the clip lead is relatively large. It becomes a clip lead that can conduct a large current. Accordingly, the clip lead corresponds to a chip having a small chip size and a relatively large rated current, and as a result, a semiconductor capable of conducting a relatively large current and realizing a downsized electronic device. It becomes the device and the clip lead.

また、本発明の半導体装置及びクリップリードによれば、第１接合部及び第１折り曲げ部は、チップと第１接合部との間の第１接合部材に対する熱応力を緩和するための熱応力緩和構造を構成するため、比較的大きな電流を導通した場合でも、チップと第１接合部との間の第１接合部材に加わる熱応力を比較的小さくすることができ、その結果、熱サイクルストレスに対する耐性を比較的高くすることができる。 Further, according to the semiconductor device and the clip lead of the present invention, the first joint portion and the first bent portion relax the thermal stress for relieving the thermal stress on the first joint member between the chip and the first joint portion. Since the structure is configured, the thermal stress applied to the first joining member between the chip and the first joining portion can be made relatively small even when a relatively large current is conducted, and as a result, the thermal stress against the thermal cycle stress can be reduced. The resistance can be made relatively high.

また、本発明の半導体装置及びクリップリードによれば、熱応力緩和構造は、少なくとも第１接合部及び第１折り曲げ部が平板部よりも薄くなるように構成された構造を含むため、第１接合部の剛性を比較的小さくすることができ、チップと第１接合部との熱膨張係数の違いに起因する第１接合部材の応力が比較的小さくなる。その結果、熱サイクルストレスに対する耐性を比較的高くすることができる。 Further, according to the semiconductor device and the clip lead of the present invention, since the thermal stress relaxation structure includes a structure in which at least the first joint portion and the first bent portion are thinner than the flat plate portion, the first joint portion The rigidity of the portion can be made relatively small, and the stress of the first joining member due to the difference in thermal expansion coefficient between the chip and the first joining portion becomes relatively small. As a result, the resistance to thermal cycle stress can be made relatively high.

本発明の半導体装置の製造方法によれば、クリップリード配置工程において、所定の厚みを有する平板部を有する架橋部を有するクリップリード、すなわち、クリップリードの断面積（電流の導通路に対する断面積）が大きく、比較的大きな電流を導通可能なクリップリードをチップ及び電極部上に配置するため、チップサイズが小さく、かつ、定格電流が比較的大きいチップに対応したクリップリードを配置することとなり、その結果、比較的大きな電流を導通可能で、かつ、小型化された電子機器を実現することができる半導体装置を製造することができる。 According to the semiconductor device manufacturing method of the present invention, in the clip lead arranging step, the clip lead having the bridging portion having the flat plate portion having the predetermined thickness, that is, the cross-sectional area of the clip lead (the cross-sectional area with respect to the current conducting path). Since the large size of the clip lead that can conduct a relatively large current is arranged on the chip and the electrode portion, the clip lead corresponding to the chip having a small chip size and a relatively large rated current is arranged. As a result, it is possible to manufacture a semiconductor device capable of conducting a relatively large current and realizing a downsized electronic device.

また、本発明の半導体装置の製造方法によれば、クリップリードとして、第１接合部及び第１折り曲げ部が第１接合部とチップとの間の第１接合部材に対する熱応力を緩和するための熱応力緩和構造を構成するクリップリードをチップ及び電極部上に配置するため、比較的大きな電流を導通した場合でも、第１接合部材に加わる熱応力を比較的小さくすることができ、その結果、熱サイクルストレスに対する耐性の高い半導体装置を製造することができる。 Further, according to the method for manufacturing a semiconductor device of the present invention, as the clip lead, the first joint portion and the first bent portion are provided to reduce thermal stress on the first joint member between the first joint portion and the chip. Since the clip lead forming the thermal stress relaxation structure is arranged on the chip and the electrode portion, the thermal stress applied to the first joining member can be made relatively small even when a relatively large current is conducted, and as a result, A semiconductor device having high resistance to thermal cycle stress can be manufactured.

また、本発明の半導体装置の製造方法によれば、クリップリード配置工程においては、クリップリードとして、第１接合部及び第１折り曲げ部が第１接合部とチップとの間の接合部材に対する熱応力を緩和するための熱応力緩和構造を構成し、熱応力緩和構造は、少なくとも第１接合部及び第１折り曲げ部が平板部よりも薄くなるように構成された構造を含むクリップリードをチップ及び電極部上に配置するため、製造された半導体装置は、第１接合部の剛性を小さくすることができ、チップと第１接合部との熱膨張係数の違いに起因する第１接合部材の応力が小さくなる。その結果、熱サイクルストレスに対する耐性の高い半導体装置を製造することができる。 Further, according to the method of manufacturing a semiconductor device of the present invention, in the clip lead disposing step, the first bonding portion and the first bent portion serve as the clip lead, and thermal stress is exerted on the bonding member between the first bonding portion and the chip. And a clip lead including a structure in which at least the first joint portion and the first bent portion are configured to be thinner than the flat plate portion. In the manufactured semiconductor device, the rigidity of the first joint can be reduced, and the stress of the first joint member due to the difference in thermal expansion coefficient between the chip and the first joint can be reduced. Get smaller. As a result, a semiconductor device having high resistance to thermal cycle stress can be manufactured.

実施形態１に係る半導体装置１の断面図である。3 is a cross-sectional view of the semiconductor device 1 according to the first embodiment. FIG. 実施形態１に係るクリップリード１００の製造方法を説明するために示す図である。6A and 6B are views for explaining the method for manufacturing the clip lead 100 according to the first embodiment. 異形条材１００’を説明するために示す図である。It is a figure shown in order to demonstrate the profile strip 100'. 実施形態１に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a diagram shown for explaining the method for manufacturing the semiconductor device according to the first embodiment. 実施形態１に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a diagram shown for explaining the method for manufacturing the semiconductor device according to the first embodiment. 実施形態２に係る半導体装置２の断面図である。6 is a cross-sectional view of a semiconductor device 2 according to a second embodiment. FIG. 実施形態３に係る半導体装置３の断面図である。6 is a cross-sectional view of a semiconductor device 3 according to a third embodiment. FIG. 実施形態４に係る半導体装置４の断面図である。FIG. 9 is a cross-sectional view of a semiconductor device 4 according to a fourth embodiment. 実施形態５に係る半導体装置５の断面図である。FIG. 9 is a cross-sectional view of a semiconductor device 5 according to a fifth embodiment. 変形例に係る半導体装置６を示す図である。It is a figure which shows the semiconductor device 6 which concerns on a modification. 従来の半導体装置８００を示す図である。It is a figure which shows the conventional semiconductor device 800.

以下、本発明の半導体装置、半導体装置の製造方法及びクリップリードについて、図に示す実施形態に基づいて説明する。なお、各図面は模式図であり、必ずしも実際の寸法を厳密に反映したものではない。また、各実施形態においては、基本的な構成、特徴、機能が同じ構成要素（形状が完全に同一でない構成要素を含む）については、実施形態をまたいで同じ符号を使用するとともに再度の説明を省略することがある。 Hereinafter, a semiconductor device, a method for manufacturing a semiconductor device, and a clip lead of the present invention will be described based on the embodiments shown in the drawings. It should be noted that each drawing is a schematic diagram and does not necessarily reflect the actual dimensions strictly. Further, in each embodiment, components having the same basic configuration, characteristics, and functions (including components not completely identical in shape) will be denoted by the same reference numerals across the embodiments and will not be described again. May be omitted.

［実施形態１］
１．実施形態１に係る半導体装置１の構成
図１は、実施形態１に係る半導体装置１を示す図である。図１（ａ）は半導体装置１の断面図を示し、図１（ｂ）はチップ１０近傍の要部拡大断面図を示し、図１（ｃ）は第２電極部２２近傍の要部拡大断面図を示す。
図２は、実施形態１に係るクリップリード１００を説明するために示す図である。図２(ａ)は折り曲げ前の異形条材１００’を示す断面図であり、図２（ｂ）はクリップリード１００を示す断面図である。
図３は、異形条材１００’を説明するために示す図である。図３（ａ）は銅平条材１００’’の断面図を示し、図３（ｂ）は銅平条材１００’’を圧延している様子を示す図であり、図３（ｃ）は異形条材１００’の断面図を示す図である。 [Embodiment 1]
1. Configuration of Semiconductor Device 1 According to First Embodiment FIG. 1 is a diagram showing the semiconductor device 1 according to the first embodiment. 1A is a sectional view of the semiconductor device 1, FIG. 1B is an enlarged sectional view of an essential part near the chip 10, and FIG. 1C is an enlarged sectional view of an essential part near the second electrode part 22. The figure is shown.
FIG. 2 is a diagram for explaining the clip lead 100 according to the first embodiment. 2A is a cross-sectional view showing the deformed strip 100′ before bending, and FIG. 2B is a cross-sectional view showing the clip lead 100.
FIG. 3 is a diagram shown for explaining the profiled strip 100′. FIG. 3A is a cross-sectional view of the copper flat strip 100″, FIG. 3B is a view showing a state of rolling the copper flat strip 100″, and FIG. It is a figure which shows the cross section of profile strip 100'.

実施形態１に係る半導体装置１は、図１に示すように、チップ１０と、表面上に第１電極部２０及び第２電極部２２が配置された基板Ｓと、クリップリード１００と、第１接合部材３０と、第２接合部材４０と、端子７０と、樹脂８０とを備える。 As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a chip 10, a substrate S on which a first electrode portion 20 and a second electrode portion 22 are arranged, a clip lead 100, and a first electrode. The joining member 30, the second joining member 40, the terminal 70, and the resin 80 are provided.

チップ１０は、一方の面（基板側）及び他方の面（基板とは反対側）にそれぞれ表面電極１２，１４を有する半導体チップである。チップ１０は、基板Ｓ上に配置された第１電極部２０上に第３接合部材５０を介して接合されている。実施形態１においては２端子の半導体チップを用いるが、３端子や４端子等適宜の半導体チップを用いてもよい。 The chip 10 is a semiconductor chip having surface electrodes 12 and 14 on one surface (on the side of the substrate) and the other surface (on the side opposite to the substrate), respectively. The chip 10 is bonded to the first electrode portion 20 arranged on the substrate S via the third bonding member 50. Although a two-terminal semiconductor chip is used in the first embodiment, an appropriate semiconductor chip such as a three-terminal or a four-terminal semiconductor chip may be used.

基板Ｓは、一方の表面に、第１電極部２０及び第２電極部２２が配置されており、他方面には放熱用のフィンＦが配置されている。基板Ｓとしては、一般的なプリント基板を用いてもよいし、ＤＣＢ基板（Ｄｉｒｅｃｔ Ｃоｐｐｅｒ Ｂｏｎｄｉｎｇ基板）を用いてもよいし、その他適宜の基板を用いてもよい。第１電極部２０及び第２電極部２２はいずれも基板上のパターン配線である。
第１電極部２０は、チップ１０の一方の面の表面電極１２と電気的に接続されている。
第２電極部２２は、第１電極部２０と間隔をあけて配置されている。第２電極部２２の所定の領域においては、第２接合部材４０を介してクリップリード１００の第２接合部１２０と接合されており、第２電極部２２の別の領域においては、第４接合部材６０を介して外部接続用の端子７０が接合されている。 The first electrode portion 20 and the second electrode portion 22 are arranged on one surface of the substrate S, and the fins F for heat dissipation are arranged on the other surface. As the board S, a general printed board may be used, a DCB board (Direct Copper Bonding board) may be used, or any other suitable board may be used. Both the first electrode portion 20 and the second electrode portion 22 are pattern wiring on the substrate.
The first electrode portion 20 is electrically connected to the surface electrode 12 on one surface of the chip 10.
The second electrode portion 22 is arranged with a space from the first electrode portion 20. In a predetermined area of the second electrode portion 22, it is joined to the second joining portion 120 of the clip lead 100 via the second joining member 40, and in a different area of the second electrode portion 22, a fourth joining portion. A terminal 70 for external connection is joined via the member 60.

クリップリード１００は、チップ１０の他方の面の表面電極１４と第１接合部材３０を介して接合された第１接合部１１０、第１接合部１１０と間隔をあけて配置され、第２電極部２２と第２接合部材４０を介して接合された第２接合部１２０、及び、第１接合部１１０と第２接合部１２０とを架橋する架橋部１３０を有し、チップ１０と第２電極部２２とを電気的に接続する。なお、熱応力緩和構造１４０については後述する。 The clip lead 100 is disposed with a space between the first bonding portion 110 and the first bonding portion 110, which are bonded to the surface electrode 14 on the other surface of the chip 10 via the first bonding member 30, and the second electrode portion. 22 and the second bonding member 40 and the second bonding portion 120, and the bridge portion 130 that bridges the first bonding portion 110 and the second bonding portion 120, and the chip 10 and the second electrode portion. 22 is electrically connected. The thermal stress relaxation structure 140 will be described later.

クリップリード１００は、銅などの金属からなる。クリップリード１００は、一方側に突出した凸部の形状(台地状の形状)をした板厚部１３１’と板薄部１３２’，１３３’を有する異形条材１００’が折り曲げられてなる（図２参照。）。異形条材１００’は、銅平条材１００’’から（例えばロールＲ等で）圧延することによって板厚部１３１’と板薄部１３２’，１３３’とが形成されたものである（図３参照。）。 The clip lead 100 is made of metal such as copper. The clip lead 100 is formed by bending a deformed strip 100′ having a thick plate portion 131′ and a thin plate portion 132′, 133′ having a convex shape (plateau shape) protruding to one side (see FIG. 2). The deformed strip 100' is formed by rolling the flat copper strip 100'' (for example, with a roll R) to form a thick portion 131' and thin portions 132' and 133' (Fig. See 3.).

なお、本明細書において、異形条材とは、フープ材のように異形状の断面を有するものがロール状に巻かれているもののみならず、当該フープ材から切り離されて個片化したものも異形条材というものとする。 In the present specification, the deformed strip material is not limited to one in which a hoop material having an irregularly shaped cross section is wound in a roll shape, but is also separated into individual pieces from the hoop material. Is also called profiled strip.

クリップリード１００は、異形条材１００’の板薄部１３２’，１３３’における板厚部１３１’側の部分において、板薄部１３２’，１３３’を他方側（図２の紙面下側）に向かって折り曲げることにより、第１折り曲げ部１３２及び第２折り曲げ部１３３が形成されている。さらに、板薄部１３２’の中途で折り曲げることにより第１接合部１１０が形成され、板薄部１３３’の中途で折り曲げることにより第２接合部１２０が形成されている（図２参照。）。 In the clip lead 100, the thin plate portions 132' and 133' are arranged on the other side (the lower side of the plane of FIG. 2) at the thin plate portions 132' and 133' of the deformed strip 100' on the plate thickness portion 131' side. The first bent portion 132 and the second bent portion 133 are formed by bending toward each other. Further, the first joint portion 110 is formed by bending the sheet thin portion 132' in the middle thereof, and the second joint portion 120 is formed by bending the sheet thin portion 133' in the middle thereof (see FIG. 2).

第１接合部１１０は、平面的に見てチップ１０の他方の面の表面電極１４と対応する位置に配置されており、第１接合部材３０を介してチップ１０の他方の面の表面電極１４と接続されている。第１接合部１１０は、平板部１３１よりも薄い平板形状であり、チップ１０の他方の面の表面電極１４とほぼ平行になるように配置されている。 The first bonding portion 110 is arranged at a position corresponding to the surface electrode 14 on the other surface of the chip 10 in plan view, and the surface electrode 14 on the other surface of the chip 10 is interposed via the first bonding member 30. Connected with. The first bonding portion 110 has a flat plate shape thinner than the flat plate portion 131, and is arranged so as to be substantially parallel to the surface electrode 14 on the other surface of the chip 10.

第２接合部１２０は、平面的に見て第２電極部２２の少なくとも一部と重なる位置に配置され、第２接合部材４０を介して第２電極部２２と接続されている。第２接合部１２０は、平板部１３１よりも薄い平板形状である。第１接合部１１０と第２接合部１２０とは同じ厚さである。 The second joint portion 120 is arranged at a position overlapping at least a part of the second electrode portion 22 when seen in a plan view, and is connected to the second electrode portion 22 via the second joint member 40. The second joint portion 120 has a flat plate shape thinner than the flat plate portion 131. The first joint 110 and the second joint 120 have the same thickness.

架橋部１３０は、平板部１３１と、第１折り曲げ部１３２と、第２折り曲げ部１３３と、肩部１３４，１３５とを有する。 The bridge portion 130 has a flat plate portion 131, a first bent portion 132, a second bent portion 133, and shoulder portions 134 and 135.

平板部１３１は、チップ１０の定格電流に対応した電流量を導通可能な所定の厚みを有する。平板部１３１が所定の厚さを有するため、平板部１３１と樹脂８０との接触面積が大きくなり、クリップリード１００が固定されやすい。 The flat plate portion 131 has a predetermined thickness capable of conducting a current amount corresponding to the rated current of the chip 10. Since the flat plate portion 131 has a predetermined thickness, the contact area between the flat plate portion 131 and the resin 80 is large, and the clip lead 100 is easily fixed.

第１折り曲げ部１３２は、平板部１３１（肩部１３４）から下側に向かって折り曲げられており、平板部１３１と接続されている側とは反対側で第１接合部１１０と接続されている。第１折り曲げ部１３２は、第１接合部１１０に対する傾斜角度が９０°〜１２０°の範囲内になっている。 The first bent portion 132 is bent downward from the flat plate portion 131 (shoulder portion 134) and is connected to the first joint portion 110 on the side opposite to the side connected to the flat plate portion 131. .. The inclination angle of the first bent portion 132 with respect to the first joint portion 110 is within the range of 90° to 120°.

第２折り曲げ部１３３は、平板部１３１（肩部１３５）から下側に向かって折り曲げられており、平板部１３１と接続されている側とは反対側で第２接合部１２０と接続されている。第２折り曲げ部１３３も、第２接合部１２０に対する傾斜角度が９０°〜１２０°の範囲内になっている。 The second bent portion 133 is bent downward from the flat plate portion 131 (shoulder portion 135) and is connected to the second joint portion 120 on the side opposite to the side connected to the flat plate portion 131. .. The second bent portion 133 also has an inclination angle with respect to the second joint portion 120 within the range of 90° to 120°.

肩部１３４は、平板部１３１と第１折り曲げ部１３２との間に形成されており、平板部１３１よりも薄い。肩部１３５は、平板部１３１と第２折り曲げ部１３３との間に形成されており、平板部１３１よりも薄い。肩部１３４，１３５は、平板部１３１と接続されている部分から外側（平板部１３１とは離れていく方向）に向かうに従って薄くなっており、所定の厚さ（例えば、第１折り曲げ部１３２や第２折り曲げ部１３３と同じ厚さ）になった位置から当該所定の厚さで外側に延在している。平板部１３１の下側の表面と肩部１３４，１３５の下側の表面は同一面(段差がない状態)になっている。 The shoulder portion 134 is formed between the flat plate portion 131 and the first bent portion 132, and is thinner than the flat plate portion 131. The shoulder portion 135 is formed between the flat plate portion 131 and the second bent portion 133 and is thinner than the flat plate portion 131. The shoulders 134 and 135 become thinner from the portion connected to the flat plate portion 131 toward the outside (in the direction away from the flat plate portion 131), and have a predetermined thickness (for example, the first bent portion 132 or The second bent portion 133 has the same thickness as the second bent portion 133) and extends outward with a predetermined thickness. The lower surface of the flat plate portion 131 and the lower surface of the shoulder portions 134 and 135 are flush with each other (there is no step).

第１接合部１１０、第２接合部１２０、第１折り曲げ部１３２、第２折り曲げ部１３３の厚さ及び肩部１３４，１３５における外側に延在している部分の厚さはいずれも、平板部１３１よりも薄く、かつ、同じ厚さである。 The thicknesses of the first joint portion 110, the second joint portion 120, the first bent portion 132, the second bent portion 133 and the thicknesses of the shoulder portions 134 and 135 extending outward are all flat plate portions. It is thinner than 131 and has the same thickness.

第１接合部１１０及び第１折り曲げ部１３２は、第１接合部１１０とチップ１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成する。
熱応力緩和構造１４０は、第１接合部１１０及び第１折り曲げ部１３２が平板部１３１よりも薄くなるように構成された構造、異形条材が折り曲げられた構造及び第１接合部に対する第１折り曲げ部の傾斜角度が９０°〜１２０°の範囲内になるように構成された構造を含む。 The first joint portion 110 and the first bent portion 132 configure a thermal stress relaxation structure 140 for relaxing thermal stress on the first joint member 30 between the first joint portion 110 and the chip 10.
The thermal stress relaxation structure 140 has a structure in which the first joint 110 and the first bent portion 132 are thinner than the flat plate portion 131, a structure in which a deformed strip is bent, and a first fold for the first joint. And a structure configured such that the inclination angle of the part is within a range of 90° to 120°.

第１〜第４接合部材３０，４０，５０，６０は、はんだ、銀ナノペーストを焼結したもの等適宜の接合部材を用いることができる。実施形態１においては、接合する際の流動性が高いはんだを用いる。 As the first to fourth joining members 30, 40, 50 and 60, suitable joining members such as solder and one obtained by sintering silver nano paste can be used. In the first embodiment, a solder having high fluidity at the time of joining is used.

第１接合部材３０は、第１接合部１１０、第１折り曲げ部１３２及び肩部１３４とチップ１０の他方の面の表面電極１４との間に配置されている。すなわち、第１折り曲げ部１３２のチップ側（下側）の面全体が第１接合部材３０と接しており、第１接合部材３０とクリップリード１００との接触面の端部が肩部１３４の下側になっている。
また、第１接合部１１０においては、第１接合部１１０の厚みのうちの少なくとも半分の厚みまで第１接合部材３０に埋められている（図１（ａ）及び（ｂ）参照。）。
なお、第１接合部材３０は、チップ１０とクリップリード１００との熱膨張係数の違いによる第１接合部材３０の応力を緩和するために第３接合部材５０よりも厚い。 The first bonding member 30 is arranged between the first bonding portion 110, the first bent portion 132, the shoulder portion 134 and the surface electrode 14 on the other surface of the chip 10. That is, the entire chip side (lower side) surface of the first bent portion 132 is in contact with the first joining member 30, and the end portion of the contact surface between the first joining member 30 and the clip lead 100 is below the shoulder portion 134. It's on the side.
In addition, in the first joint portion 110, at least half the thickness of the first joint portion 110 is embedded in the first joint member 30 (see FIGS. 1A and 1B).
The first joining member 30 is thicker than the third joining member 50 in order to relieve the stress of the first joining member 30 due to the difference in thermal expansion coefficient between the chip 10 and the clip lead 100.

第２接合部材４０は、第２接合部１２０、第２折り曲げ部１３３及び肩部１３５と第２電極部２２との間に配置されている。すなわち、第２折り曲げ部１３３の第２電極部２２側全体が第２接合部材４０と接しており、第２接合部材４０とクリップリード１００との接触面の端部が肩部１３５の下側になっている。
第２接合部１２０においては、第２接合部１２０の厚みのうちの少なくとも半分の厚みまで第２接合部材４０に埋められている（図１（ａ）及び（ｃ）参照。）。
第２接合部材４０は、第２電極部２２が形成されている基板Ｓとクリップリード１００との熱膨張係数の違いによる第２接合部材４０の応力を緩和するために第３接合部材５０よりも厚い。 The second joint member 40 is arranged between the second joint portion 120, the second bent portion 133, the shoulder portion 135, and the second electrode portion 22. That is, the entire second bent portion 133 on the second electrode portion 22 side is in contact with the second joining member 40, and the end portion of the contact surface between the second joining member 40 and the clip lead 100 is below the shoulder portion 135. Is becoming
In the second joint portion 120, at least half the thickness of the second joint portion 120 is filled with the second joint member 40 (see FIGS. 1A and 1C).
The second joining member 40 is more than the third joining member 50 in order to relax the stress of the second joining member 40 due to the difference in thermal expansion coefficient between the substrate S on which the second electrode portion 22 is formed and the clip lead 100. thick.

端子７０は、第２電極部２２と第４接合部材６０を介して接続されており、外側に向かって延在している。樹脂８０は、適宜の樹脂を用いることができ、樹脂８０によって、チップ１０、基板Ｓ（第１電極部２０及び第２電極部２２を含む）、クリップリード１００、第１〜第４接合部材３０〜６０及び端子７０の一部が樹脂封止されている。 The terminal 70 is connected to the second electrode portion 22 via the fourth joining member 60 and extends outward. An appropriate resin can be used as the resin 80, and depending on the resin 80, the chip 10, the substrate S (including the first electrode portion 20 and the second electrode portion 22), the clip lead 100, and the first to fourth bonding members 30. ˜60 and a part of the terminal 70 are resin-sealed.

２．実施形態１に係る半導体装置の製造方法
図４及び図５は、実施形態１に係る半導体装置の製造方法を説明するために示す図である。図４（ａ）〜図４（ｃ）及び図５（ａ）〜図５（ｃ）は各工程図である。 2. Method of Manufacturing Semiconductor Device According to First Embodiment FIGS. 4 and 5 are diagrams for explaining the method of manufacturing a semiconductor device according to the first embodiment. FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C are process drawings.

実施形態１に係る半導体装置の製造方法は、基板準備工程と、チップ配置工程と、接合部材配置工程と、クリップリード配置工程と、接合工程と、後処理工程とをこの順序で含む。 The method for manufacturing a semiconductor device according to the first embodiment includes a substrate preparation step, a chip placement step, a joining member placement step, a clip lead placement step, a joining step, and a post-treatment step in this order.

（１）基板準備工程
まず、一方の面側に第１電極部２０及び第２電極部２２が配置された基板Ｓを準備する（図４（ａ）参照。）。なお、符号Ｆは放熱用のフィンを示す。 (1) Substrate Preparation Step First, the substrate S having the first electrode portion 20 and the second electrode portion 22 arranged on one surface side is prepared (see FIG. 4A). The symbol F indicates a fin for heat dissipation.

（２）チップ配置工程
次に、適宜の方法（例えば、はんだ印刷）によって基板Ｓの第１電極部２０上にはんだペースト５０’を配置し、はんだペースト５０’上に一方の面の表面電極１２がはんだペースト５０’と接するようにチップ１０を配置する（図４（ｂ）参照。）。なお、はんだペースト５０’は印刷で供給してもよいし、ディスペンサで供給してもよい。 (2) Chip Arranging Step Next, the solder paste 50′ is arranged on the first electrode portion 20 of the substrate S by an appropriate method (for example, solder printing), and the surface electrode 12 on one surface is arranged on the solder paste 50′. The chip 10 is arranged so that the solder contacts the solder paste 50' (see FIG. 4B). The solder paste 50′ may be supplied by printing or a dispenser.

（３）接合部材配置工程
次に、所定の冶具（例えば、ディスペンサ）を用いてチップ１０の他方の面の表面電極１４上にはんだペースト３０’を配置する（図４（ｃ）参照。）。また、適宜の方法（例えば、はんだ印刷）によって基板Ｓ上の第２電極部２２上にはんだペースト４０’，６０’を配置する。なお、はんだペースト３０’，４０’は、熱応力を緩和するために比較的厚く形成されており、少なくともはんだペースト５０’よりも厚くなるように構成されている。なお、はんだペースト４０’，６０’をディスペンサで供給してもよい。 (3) Bonding Member Placement Step Next, the solder paste 30′ is placed on the surface electrode 14 on the other surface of the chip 10 using a predetermined jig (for example, a dispenser) (see FIG. 4C). Further, the solder pastes 40′ and 60′ are arranged on the second electrode portion 22 on the substrate S by an appropriate method (for example, solder printing). The solder pastes 30 ′ and 40 ′ are formed relatively thick in order to reduce thermal stress, and are configured to be at least thicker than the solder paste 50 ′. The solder pastes 40' and 60' may be supplied by a dispenser.

（４）クリップリード配置工程
次に、はんだペースト３０’上に第１接合部１１０を配置するとともに、はんだペースト４０’上に第２接合部１２０を配置することにより、クリップリード１００をチップ１０及び第２電極部２２上に配置して組立体１’を形成する（図５（ａ）参照。）。また、はんだペースト６０’上に端子７０を配置する。 (4) Clip Lead Arranging Step Next, the first joint portion 110 is arranged on the solder paste 30′ and the second joint portion 120 is arranged on the solder paste 40′. The assembly 1'is formed by disposing the assembly 1'on the second electrode portion 22 (see FIG. 5A). Further, the terminals 70 are arranged on the solder paste 60′.

（５）接合工程
次に、所定の装置内（例えばソルダー装置の加熱炉内）に組立体１’を配置して加熱することにより各はんだペーストを溶融し、基板Ｓとチップ１０、チップ１０とクリップリード１００、第２電極部２２とクリップリード１００、及び、第２電極部２２と端子７０を第１〜第４接合部材（はんだ）３０，４０，５０，６０で接合する（図５（ｂ）参照。）。 (5) Bonding Step Next, the solder paste is melted by arranging the assembly 1′ in a predetermined device (for example, in a heating furnace of a solder device) and heating the substrate 1 and the chip 10 and the chip 10. The clip lead 100, the second electrode portion 22 and the clip lead 100, and the second electrode portion 22 and the terminal 70 are joined by the first to fourth joining members (solders) 30, 40, 50, 60 (FIG. 5B. )reference.).

このとき、チップ１０とクリップリード１００の間に配置されたはんだペースト３０’が溶融され、第１折り曲げ部１３２の下側を通って肩部１３４の下側まで這い上がる。また、第２電極部２２とクリップリード１００の間に配置されたはんだペースト４０’が溶融され、第２折り曲げ部１３３の下側を通って肩部１３５の下側まで這い上がる。 At this time, the solder paste 30 ′ disposed between the chip 10 and the clip lead 100 is melted and passes under the first bent portion 132 and crawls up to the lower side of the shoulder portion 134. Further, the solder paste 40 ′ disposed between the second electrode portion 22 and the clip lead 100 is melted, passes through the lower side of the second bent portion 133, and climbs up to the lower side of the shoulder portion 135.

（６）後処理工程
次に、接合工程において各はんだペーストから基板Ｓやチップ１０に広がることがある有機物を洗い落とす。次に、必要に応じて基板Ｓやチップ１０上の所定の箇所をワイヤボンディングする。次に、組立体１’を金型内に入れて樹脂８０で樹脂封止する（図５（ｃ）参照。）。
このようにして実施形態１に係る半導体装置１を製造することができる。 (6) Post-Processing Step Next, organic substances that may spread on the substrate S and the chip 10 are washed off from each solder paste in the joining step. Next, if necessary, predetermined portions on the substrate S or the chip 10 are wire-bonded. Next, the assembly 1'is put in a mold and resin-sealed with a resin 80 (see FIG. 5C).
In this way, the semiconductor device 1 according to the first embodiment can be manufactured.

３．実施形態１に係る半導体装置１、クリップリード１００及び半導体装置の製造方法の効果
実施形態１に係る半導体装置１及びクリップリード１００によれば、架橋部１３０は、所定の厚みを有する平板部１３１を有するため、クリップリード１００は、クリップリードの断面積（電流の導通路に対する断面積）が大きく、比較的大きな電流を導通可能なクリップリードとなる。従って、チップサイズが小さく、かつ、定格電流が比較的大きいチップに対応したクリップリードとなり、比較的大きな電流を導通可能で、かつ、小型化された電子機器を実現することができる半導体装置となる。 3. Effect of Semiconductor Device 1, Clip Lead 100, and Method of Manufacturing Semiconductor Device According to First Embodiment According to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the bridging portion 130 includes the flat plate portion 131 having a predetermined thickness. Because of this, the clip lead 100 has a large cross-sectional area (cross-sectional area with respect to the current conducting path) of the clip lead and is a clip lead capable of conducting a relatively large current. Therefore, the semiconductor device becomes a clip lead corresponding to a chip having a small chip size and a relatively large rated current, capable of conducting a relatively large current, and realizing a downsized electronic device. ..

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、第１接合部１１０及び第１折り曲げ部１３２は、チップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するため、比較的大きな電流を導通した場合でも、第１接合部材３０に加わる熱応力を比較的小さくすることができ、その結果、熱サイクルストレスに対する耐性を比較的高くすることができる。 In addition, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the first joint portion 110 and the first bent portion 132 heat the first joint member 30 between the chip 10 and the first joint portion 110. Since the thermal stress relaxation structure 140 for relaxing the stress is configured, the thermal stress applied to the first joining member 30 can be made relatively small even when a relatively large current is conducted, and as a result, the thermal cycle stress can be obtained. The resistance to can be relatively high.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、熱応力緩和構造１４０は、少なくとも第１接合部１１０及び第１折り曲げ部１３２が平板部１３１よりも薄くなるように構成された構造を含むため、第１接合部１１０の剛性を比較的小さくすることができ、チップ１０と第１接合部１１０との熱膨張係数の違いに起因する第１接合部材３０の応力が比較的小さくなる。その結果、熱サイクルストレスに対する耐性を比較的高くすることができる。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the thermal stress relaxation structure 140 is configured such that at least the first joint portion 110 and the first bent portion 132 are thinner than the flat plate portion 131. Since the structure includes the first joint 110, the rigidity of the first joint 110 can be made relatively small, and the stress of the first joint member 30 due to the difference in thermal expansion coefficient between the chip 10 and the first joint 110 is relatively small. Become. As a result, the resistance to thermal cycle stress can be made relatively high.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、熱応力緩和構造１４０は、少なくとも第１接合部１１０及び第１折り曲げ部１３２が平板部１３１よりも薄くなるように構成された構造を含むため、折り曲げ加工がしやすく、クリップリード１００を形成し易くなる。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the thermal stress relaxation structure 140 is configured such that at least the first joint portion 110 and the first bent portion 132 are thinner than the flat plate portion 131. Since the structure is included, the bending process is easy and the clip lead 100 is easy to form.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、熱応力緩和構造１４０は、第１接合部１１０及び第１折り曲げ部１３２（を含むクリップリード）が異形条材１００’を折り曲げることによって形成された構造を含むため、プレス加工されたものを折り曲げることによって形成されたクリップリードよりも加工による変質を抑え、残留応力を小さくすることができる。従って、このことによっても熱サイクルストレスに対する耐性を高くすることができる。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, in the thermal stress relaxation structure 140, the first bonding portion 110 and the first bent portion 132 (including the clip lead) bend the deformed strip 100′. Since the structure formed by the above is included, it is possible to suppress the deterioration due to the processing and reduce the residual stress as compared with the clip lead formed by bending the pressed one. Therefore, this also makes it possible to increase the resistance to thermal cycle stress.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、熱応力緩和構造１４０は、第１接合部１１０に対する第１折り曲げ部１３２の傾斜角度が９０°〜１２０°の範囲内になるように構成された構造を含むため、接合工程において、第１接合部材３０（はんだ）が第１折り曲げ部１３２の下側を這い上がり易くなる。従って、製造された半導体装置を使用したときに、第１折り曲げ部１３２及び第１接合部材３０（はんだ）の両方を通って第２電極部２２へ熱を放出し、第２電極部２２から外部へ熱を放出することができるため、チップ１０から発生する熱を効率よく外部に放出することができる。このことから、チップ１０及び第１接合部１１０の温度上昇を抑えることができるため、高温時のチップ１０及び第１接合部１１０の膨張を抑制することができる。その結果、このことによっても第１接合部材３０に加わる熱応力を小さくすることができ、熱サイクルストレスに対する耐性を高くすることができる。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, in the thermal stress relaxation structure 140, the inclination angle of the first bent portion 132 with respect to the first joint 110 is within the range of 90° to 120°. Since it includes the structure configured as described above, in the joining step, the first joining member 30 (solder) can easily crawl below the first bent portion 132. Therefore, when the manufactured semiconductor device is used, heat is radiated to the second electrode portion 22 through both the first bent portion 132 and the first joining member 30 (solder), and the second electrode portion 22 is exposed to the outside. Since the heat can be released to the outside, the heat generated from the chip 10 can be efficiently released to the outside. From this, since the temperature rise of the chip 10 and the first joint 110 can be suppressed, the expansion of the chip 10 and the first joint 110 at high temperature can be suppressed. As a result, also by this, the thermal stress applied to the first joining member 30 can be reduced, and the resistance to the thermal cycle stress can be increased.

なお、第１接合部１１０に対する第１折り曲げ部１３２の傾斜角度を９０°以上としたのは、第１接合部１１０に対する第１折り曲げ部１３２の傾斜角度を９０°未満とした場合には、第１接合部１１０に対して鋭角に第１折り曲げ部１３２が形成されていることとなり、第１接合部材３０（はんだ）が第１折り曲げ部１３２のチップ側の面を這い上がり難くなるからであり、第１接合部１１０に対する第１折り曲げ部１３２の傾斜角度を１２０°以下としたのは、第１接合部１１０に対する第１折り曲げ部１３２の傾斜角度を１２０°を超える角度とした場合には、溶融したはんだがチップ側面に流れる場合があり、チップ１０の一方の面（基板側）の表面電極１２とチップ１０の他方の面（基板とは反対側）の表面電極１４が短絡するおそれがあるからである。 The inclination angle of the first bent portion 132 with respect to the first joint portion 110 is set to 90° or more because the inclination angle of the first bent portion 132 with respect to the first joint portion 110 is less than 90°. This is because the first bending portion 132 is formed at an acute angle with respect to the first joining portion 110, and it becomes difficult for the first joining member 30 (solder) to crawl on the chip-side surface of the first bending portion 132. The inclination angle of the first bent portion 132 with respect to the first joint portion 110 is set to 120° or less when the inclination angle of the first bent portion 132 with respect to the first joint portion 110 is set to an angle exceeding 120°. Since the solder may flow to the side surface of the chip, the surface electrode 12 on one surface (substrate side) of the chip 10 and the surface electrode 14 on the other surface (opposite the substrate) of the chip 10 may be short-circuited. Is.

また、実施形態１に係る半導体装置１によれば、クリップリード１００においては、第１折り曲げ部１３２のチップ側(下側)の面全体が第１接合部材３０と接しているため、チップ１０から第２電極部２２へ流れる電流を、第１折り曲げ部１３２及び第１接合部材３０の両方を介して流すことができる（第１接合部材３０をいわば電流路のバイパスとして活用することができる。）。従って、チップサイズが小さく、かつ、定格電流が比較的大きいチップに対応した比較的大きな電流を流すことができる。 Further, according to the semiconductor device 1 of the first embodiment, in the clip lead 100, the entire surface of the first bent portion 132 on the chip side (lower side) is in contact with the first joining member 30, and therefore, from the chip 10 The current flowing to the second electrode portion 22 can be made to flow through both the first bent portion 132 and the first joining member 30 (the first joining member 30 can be used as a so-called current path bypass). .. Therefore, a relatively large current corresponding to a chip having a small chip size and a relatively large rated current can be passed.

また、実施形態１に係る半導体装置１によれば、クリップリード１００においては、第１折り曲げ部１３２のチップ側の面全体が第１接合部材３０と接しているため、第１折り曲げ部１３２及び第１接合部材３０（はんだ）の両方を通って第２電極部２２へ熱を放出し、第２電極部２２から外部へ熱を放出することができる。従って、チップ１０から発生する熱を効率よく外部に放出することができ、チップ１０及び第１接合部１１０の温度上昇を抑えることができるため、高温時のチップ１０及び第１接合部１１０の膨張を抑制することができる。従って、このことによっても第１接合部材３０に加わる熱応力を小さくすることができ、熱サイクルストレスに対する耐性を高くすることができる。 Further, according to the semiconductor device 1 of the first embodiment, in the clip lead 100, the entire surface of the first bent portion 132 on the chip side is in contact with the first joining member 30, so that the first bent portion 132 and the first bent portion 132 It is possible to radiate heat to the second electrode portion 22 through both of the one joining member 30 (solder) and radiate heat to the outside from the second electrode portion 22. Therefore, the heat generated from the chip 10 can be efficiently radiated to the outside, and the temperature rise of the chip 10 and the first bonding portion 110 can be suppressed, so that the expansion of the chip 10 and the first bonding portion 110 at high temperature. Can be suppressed. Therefore, also by this, the thermal stress applied to the first joining member 30 can be reduced, and the resistance to the thermal cycle stress can be increased.

また、実施形態１に係る半導体装置１によれば、第１接合部１１０においては、第１接合部１１０の厚みのうちの少なくとも半分の厚みまで第１接合部材３０に埋められているため、クリップリード１００が固定されやすいだけでなく、チップ１０の他方の面の表面電極１４から第１接合部１１０への電流経路が増加し、比較的大きな電流を流すことができる。 Further, according to the semiconductor device 1 according to the first embodiment, in the first bonding portion 110, the first bonding member 30 is filled up to at least half the thickness of the thickness of the first bonding portion 110. Not only is the lead 100 easily fixed, but the current path from the surface electrode 14 on the other surface of the chip 10 to the first junction 110 is increased, and a relatively large current can be passed.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、第２接合部１２０及び第２折り曲げ部１３３はいずれも、平板部１３１よりも薄いため、第２接合部１２０の剛性を小さくすることができ、第２接合部１２０と基板Ｓとの熱膨張係数の違いに起因する第２接合部材４０に対する熱応力が小さくなる。その結果、第２接合部材４０における熱サイクルストレスに対する耐性を高くすることができる。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, since the second joint portion 120 and the second bent portion 133 are both thinner than the flat plate portion 131, the rigidity of the second joint portion 120 is small. Therefore, the thermal stress on the second bonding member 40 due to the difference in thermal expansion coefficient between the second bonding portion 120 and the substrate S is reduced. As a result, the resistance of the second joining member 40 to thermal cycle stress can be increased.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、第１接合部１１０、第１折り曲げ部１３２、第２接合部１２０及び第２折り曲げ部１３３はいずれも同じ厚さであるため、重心バランスがとりやすく、クリップリード１００の位置決めがしやすくなる。 In addition, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the first joint portion 110, the first bent portion 132, the second joint portion 120, and the second bent portion 133 all have the same thickness. The center of gravity is easily balanced, and the clip lead 100 is easily positioned.

また、実施形態１に係る半導体装置１及びクリップリード１００によれば、架橋部１３０は、平板部１３１と第１折り曲げ部１３２との間に平板部１３１よりも薄い肩部１３４を有するため、平板部１３１から直に下側に向かって折り曲げられたクリップリードよりも折り曲げ部分が弱くなりにくい。 Further, according to the semiconductor device 1 and the clip lead 100 according to the first embodiment, the bridging portion 130 has the shoulder portion 134 that is thinner than the flat plate portion 131 between the flat plate portion 131 and the first bent portion 132. The bent portion is less likely to be weaker than the clip lead bent directly downward from the portion 131.

実施形態１に係る半導体装置の製造方法においては、クリップリード配置工程において、所定の厚みを有する平板部１３１を有する架橋部１３０を有するクリップリード１００をチップ１０及び第２電極部２２上に配置する。このような構成とすることにより、クリップリード１００の断面積（電流の導通路に対する断面積）が大きく、比較的大きな電流を導通可能なクリップリード、すなわち、チップサイズが小さく、かつ、定格電流が比較的大きいチップに対応したクリップリードをチップ１０及び第２電極部２２上に配置することとなり、その結果、比較的大きな電流を導通可能で、かつ、小型化された電子機器を実現することができる半導体装置を製造することができる。 In the method of manufacturing a semiconductor device according to the first embodiment, in the clip lead arranging step, the clip lead 100 having the bridging portion 130 having the flat plate portion 131 having a predetermined thickness is arranged on the chip 10 and the second electrode portion 22. .. With such a configuration, the clip lead 100 has a large cross-sectional area (a cross-sectional area with respect to a current conducting path), and a clip lead capable of conducting a relatively large current, that is, a small chip size and a rated current. The clip lead corresponding to a relatively large chip is arranged on the chip 10 and the second electrode portion 22, and as a result, a relatively large current can be conducted and a downsized electronic device can be realized. A semiconductor device that can be manufactured can be manufactured.

また、実施形態１に係る半導体装置の製造方法によれば、第１接合部１１０及び第１折り曲げ部１３２がチップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するクリップリード１００をチップ１０及び第２電極部２２上に配置するため、比較的大きな電流を導通した場合でも、第１接合部材３０に加わる熱応力を比較的小さくすることができ、その結果、熱サイクルストレスに対する耐性の高い半導体装置を製造することができる。 In addition, according to the method for manufacturing a semiconductor device of the first embodiment, the first joint portion 110 and the first bent portion 132 alleviate thermal stress on the first joint member 30 between the chip 10 and the first joint portion 110. Since the clip lead 100 that constitutes the thermal stress relaxation structure 140 is disposed on the chip 10 and the second electrode portion 22, the thermal stress applied to the first bonding member 30 is compared even when a relatively large current is conducted. As a result, a semiconductor device having high resistance to thermal cycle stress can be manufactured.

また、実施形態１に係る半導体装置の製造方法によれば、クリップリード配置工程においては、第１接合部１１０及び第１折り曲げ部１３２がチップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成し、熱応力緩和構造１４０は、少なくとも第１接合部１１０及び第１折り曲げ部１３２が平板部１３１よりも薄くなるように構成された構造を含むクリップリード１００をチップ１０及び第２電極部２２上に配置するため、製造された半導体装置１は、第１接合部１１０の剛性を小さくすることができ、チップ１０と第１接合部１１０との熱膨張係数の違いに起因する第１接合部材３０の応力が小さくなる。その結果、熱サイクルストレスに対する耐性の高い半導体装置を製造することができる。 Further, according to the method for manufacturing a semiconductor device in accordance with the first embodiment, in the clip lead disposing step, the first joint portion 110 and the first bent portion 132 form the first joint between the chip 10 and the first joint portion 110. A thermal stress relaxation structure 140 for relaxing thermal stress on the member 30 is configured, and the thermal stress relaxation structure 140 is configured such that at least the first joint portion 110 and the first bent portion 132 are thinner than the flat plate portion 131. Since the clip lead 100 including the above structure is arranged on the chip 10 and the second electrode portion 22, the manufactured semiconductor device 1 can reduce the rigidity of the first bonding portion 110 and the chip 10 and the first bonding portion. The stress of the first joining member 30 due to the difference in thermal expansion coefficient from the portion 110 is reduced. As a result, a semiconductor device having high resistance to thermal cycle stress can be manufactured.

［実施形態２］
図６は、実施形態２に係る半導体装置２の断面図である。
実施形態２に係る半導体装置２及びクリップリード１００ａは、基本的には実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するが、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なる。すなわち、実施形態２に係るクリップリード１００ａにおいては、肩部１３４ａの下側の面と平板部１３１ａの下側の面との間には段差部１３６が形成されている(図６参照。)。 [Embodiment 2]
FIG. 6 is a sectional view of the semiconductor device 2 according to the second embodiment.
The semiconductor device 2 and the clip lead 100a according to the second embodiment have basically the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment, but the shape of the clip lead is the semiconductor device according to the first embodiment. 1 and the clip lead 100. That is, in the clip lead 100a according to the second embodiment, the step portion 136 is formed between the lower surface of the shoulder portion 134a and the lower surface of the flat plate portion 131a (see FIG. 6).

実施形態２においては、肩部１３４ａの下側の面から見て平板部１３１ａがチップ側（下側）に向かって突出する凸部が形成されており、平板部１３１ａの下側の面から見て肩部１３４ａ及び第１折り曲げ部１３２で構成される凹部が形成されている。なお、当該段差が垂直な段差である場合（段差の傾斜面が平板部１３１ａの側面である場合）には、平板部１３１ａ、肩部１３４ａ及び第１折り曲げ部１３２で凹部が形成される。 In the second embodiment, the flat plate portion 131a is formed with a convex portion that projects toward the chip side (lower side) when viewed from the lower surface of the shoulder portion 134a, and is viewed from the lower surface of the flat plate portion 131a. A recessed portion formed by the shoulder portion 134a and the first bent portion 132 is formed. When the step is a vertical step (when the inclined surface of the step is the side surface of the flat plate portion 131a), the flat plate portion 131a, the shoulder portion 134a, and the first bent portion 132 form a recess.

実施形態２においては、第１折り曲げ部１３２の下側の面全体が第１接合部材３０と接しており、第１接合部材３０とクリップリード１００との接触面の端部が段差部１３６にある。言い換えると、肩部１３４ａ及び第１折り曲げ部１３２で形成される凹部内に第１接合部材３０とクリップリード１００との接触面の端部がある。 In the second embodiment, the entire lower surface of the first bent portion 132 is in contact with the first joining member 30, and the end portion of the contact surface between the first joining member 30 and the clip lead 100 is at the step portion 136. .. In other words, the end of the contact surface between the first joining member 30 and the clip lead 100 is inside the recess formed by the shoulder portion 134a and the first bent portion 132.

また、クリップリード１００ａにおいては、肩部１３５ａの下側の面と平板部１３１ａの下側の面との間には段差部１３７が形成されている。また、実施形態２においては、平板部１３１ａの下側の面から見て肩部１３５ａ及び第２折り曲げ部１３３で構成される凹部が形成されている。 Further, in the clip lead 100a, a step portion 137 is formed between the lower surface of the shoulder portion 135a and the lower surface of the flat plate portion 131a. Further, in the second embodiment, a concave portion formed by the shoulder portion 135a and the second bent portion 133 is formed when viewed from the lower surface of the flat plate portion 131a.

実施形態２においては、第２折り曲げ部１３３の下側の面全体が第２接合部材４０と接しており、第２接合部材４０とクリップリード１００との接触面の端部が段差部１３７にある。言い換えると、肩部１３５ａ及び第２折り曲げ部１３３で構成される凹部内に第２接合部材４０とクリップリード１００との接触面の端部がある。 In the second embodiment, the entire lower surface of the second bent portion 133 is in contact with the second joining member 40, and the end portion of the contact surface between the second joining member 40 and the clip lead 100 is at the step portion 137. .. In other words, the end portion of the contact surface between the second joining member 40 and the clip lead 100 is inside the recessed portion formed by the shoulder portion 135a and the second bent portion 133.

このように、実施形態２に係る半導体装置２及びクリップリード１００ａは、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なるが、実施形態１に係る半導体装置１及びクリップリード１００の場合と同様に、架橋部１３０ａは、所定の厚みを有する平板部１３１ａを有し、第１接合部１１０及び第１折り曲げ部１３２は、チップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するため、比較的大きな電流を導通可能でありながら熱サイクルストレスに対する耐性が高い半導体装置及びクリップリードとなる。 As described above, the semiconductor device 2 and the clip lead 100a according to the second embodiment differ from the semiconductor device 1 and the clip lead 100 according to the first embodiment in the shape of the clip lead, but the semiconductor device 1 according to the first embodiment is different. Similarly to the case of the clip lead 100, the bridging portion 130a has a flat plate portion 131a having a predetermined thickness, and the first joint portion 110 and the first bent portion 132 connect the chip 10 and the first joint portion 110. Since the thermal stress relaxation structure 140 for relaxing the thermal stress on the first joining member 30 between is configured, a semiconductor device and a clip lead that can conduct a relatively large current but have high resistance to thermal cycle stress.

また、実施形態２に係る半導体装置２及びクリップリード１００ａによれば、肩部１３４ａの下側の面と平板部１３１ａの下側の面との間には段差部１３６が形成されているため、第１折り曲げ部１３２の下側を這い上がった第１接合部材３０が必要以上に第２折り曲げ部１３３側に流れなくなる。従って、第１接合部材３０が意図しない形状（例えば、チップ側面に向かって垂れ下がるような形状）となってチップ１０の一方の面（基板側）の表面電極１２とチップ１０の他方の面（基板とは反対側）の表面電極１４が短絡することを防ぐことができる。 Further, according to the semiconductor device 2 and the clip lead 100a according to the second embodiment, since the step portion 136 is formed between the lower surface of the shoulder portion 134a and the lower surface of the flat plate portion 131a, The first joining member 30 crawling up below the first bent portion 132 does not flow to the second bent portion 133 side more than necessary. Therefore, the first bonding member 30 has an unintended shape (for example, a shape that hangs down toward the side surface of the chip) and the surface electrode 12 on one surface (substrate side) of the chip 10 and the other surface (substrate) of the chip 10. It is possible to prevent the front surface electrode 14 (on the opposite side to) from being short-circuited.

また、実施形態２に係る半導体装置２及びクリップリード１００ａによれば、第１接合部材３０とクリップリード１００ａとの接触面の端部が段差部１３６にあるため、第１折り曲げ部１３２の下側を這い上がった第１接合部材３０が第２折り曲げ部１３３側に流れることを防ぐことができる。 Further, according to the semiconductor device 2 and the clip lead 100a according to the second embodiment, since the end portion of the contact surface between the first joining member 30 and the clip lead 100a is at the step portion 136, the lower side of the first bent portion 132 is formed. It is possible to prevent the first joining member 30 that has crawled up from flowing to the second bent portion 133 side.

また、実施形態２に係る半導体装置２及びクリップリード１００ａによれば、第２接合部材４０とクリップリード１００ａとの接触面の端部が段差部１３７にあるため、第２折り曲げ部１３３の下側を這い上がった第２接合部材４０が第１折り曲げ部１３２側に流れることを防ぐことができる。 Further, according to the semiconductor device 2 and the clip lead 100a according to the second embodiment, since the end portion of the contact surface between the second joining member 40 and the clip lead 100a is at the step portion 137, the lower side of the second bent portion 133 is formed. It is possible to prevent the second joining member 40 that has crawled up from flowing to the first bent portion 132 side.

さらにまた、実施形態２に係る半導体装置２及びクリップリード１００ａによれば、肩部１３４ａの下側の面から見て平板部１３１ａがチップ側（下側）に向かって突出する凸部が形成されているため、放熱に寄与する体積が大きくなり、チップ１０から発生する熱をより効率よく外部に放出することができる。従って、チップ１０及び第１接合部１１０の温度上昇を抑えることができることから、高温時のチップ１０及び第１接合部１１０の膨張を抑制することができる。その結果、第１接合部材３０に加わる熱応力をより一層小さくすることができ、熱サイクルストレスに対する耐性をより一層高くすることができる。 Further, according to the semiconductor device 2 and the clip lead 100a according to the second embodiment, the flat plate portion 131a is formed with the convex portion protruding toward the chip side (lower side) when viewed from the lower surface of the shoulder portion 134a. Therefore, the volume that contributes to heat dissipation is increased, and the heat generated from the chip 10 can be more efficiently radiated to the outside. Therefore, since the temperature rise of the chip 10 and the first joint 110 can be suppressed, the expansion of the chip 10 and the first joint 110 at high temperature can be suppressed. As a result, the thermal stress applied to the first joining member 30 can be further reduced, and the resistance to thermal cycle stress can be further enhanced.

なお、実施形態２に係る半導体装置２及びクリップリード１００ａは、クリップリードの形状以外の点においては実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するため、実施形態１に係る半導体装置１及びクリップリード１００が有する効果のうち該当する効果を有する。 The semiconductor device 2 and the clip lead 100a according to the second embodiment have the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment except for the shape of the clip lead, and thus the semiconductor device 2 and the clip lead 100a according to the first embodiment. This has the corresponding effect among the effects of the semiconductor device 1 and the clip lead 100.

［実施形態３］
図７は、実施形態３に係る半導体装置３の断面図である。
実施形態３に係る半導体装置３及びクリップリード１００ｂは、基本的には実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するが、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なる。すなわち、実施形態３に係る半導体装置３及びクリップリード１００ｂにおいて、肩部は、側面から見て階段状の肩部１３４ｂ，１３５ｂである(図７参照。)。 [Third Embodiment]
FIG. 7 is a sectional view of the semiconductor device 3 according to the third embodiment.
The semiconductor device 3 and the clip lead 100b according to the third embodiment have basically the same configuration as the semiconductor device 1 and the clip lead 100 according to the first embodiment, but the shape of the clip lead is the semiconductor device according to the first embodiment. 1 and the clip lead 100. That is, in the semiconductor device 3 and the clip lead 100b according to the third embodiment, the shoulders are stepped shoulders 134b and 135b when viewed from the side (see FIG. 7).

このように、実施形態３に係る半導体装置３及びクリップリード１００ｂは、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なるが、実施形態１に係る半導体装置１及びクリップリード１００の場合と同様に、架橋部１３０ｂは、所定の厚みを有する平板部１３１ｂを有し、第１接合部１１０及び第１折り曲げ部１３２は、チップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するため、比較的大きな電流を導通可能でありながら熱サイクルストレスに対する耐性が高い半導体装置及びクリップリードとなる。 As described above, the semiconductor device 3 and the clip lead 100b according to the third embodiment differ from the semiconductor device 1 and the clip lead 100 according to the first embodiment in the shape of the clip lead, but the semiconductor device 1 according to the first embodiment is different. Similarly to the case of the clip lead 100, the bridging portion 130b has a flat plate portion 131b having a predetermined thickness, and the first joint portion 110 and the first bent portion 132 connect the chip 10 and the first joint portion 110. Since the thermal stress relaxation structure 140 for relaxing the thermal stress on the first joining member 30 between is configured, a semiconductor device and a clip lead that can conduct a relatively large current but have high resistance to thermal cycle stress.

また、実施形態３に係る半導体装置３及びクリップリード１００ｂによれば、肩部は、側面から見て階段状の肩部１３４ｂ，１３５ｂであるため、樹脂との接触面積が大きくなる。従って、樹脂との密着性が高くなり、高温時でもクリップリード１００ｂが膨張し難くなる。従って、第１接合部材３０に加わる熱応力をより一層小さくすることができ、熱サイクルストレスに対する耐性をより一層高くすることができる。 Further, according to the semiconductor device 3 and the clip lead 100b according to the third embodiment, the shoulder portions are stepped shoulder portions 134b and 135b as viewed from the side surface, and thus the contact area with the resin is large. Therefore, the adhesiveness with the resin becomes high, and the clip lead 100b becomes difficult to expand even at high temperature. Therefore, the thermal stress applied to the first joining member 30 can be further reduced, and the resistance to thermal cycle stress can be further enhanced.

なお、実施形態３に係る半導体装置３及びクリップリード１００ｂは、クリップリードの形状以外の点においては実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するため、実施形態１に係る半導体装置１及びクリップリード１００が有する効果のうち該当する効果を有する。 The semiconductor device 3 and the clip lead 100b according to the third embodiment have the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment except for the shape of the clip lead, and thus the semiconductor device 3 and the clip lead 100b according to the first embodiment. This has the corresponding effect among the effects of the semiconductor device 1 and the clip lead 100.

［実施形態４］
図８は、実施形態４に係る半導体装置４の断面図である。
実施形態４に係る半導体装置４及びクリップリード１００ｃは、基本的には実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するが、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なる。すなわち、実施形態４における第２接合部１２０ｃ及び第２折り曲げ部１３３ｃはいずれも平板部１３１と同じ厚さである(図８参照。)。 [Embodiment 4]
FIG. 8 is a sectional view of the semiconductor device 4 according to the fourth embodiment.
The semiconductor device 4 and the clip lead 100c according to the fourth embodiment have basically the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment, but the shape of the clip lead is the semiconductor device according to the first embodiment. 1 and the clip lead 100. That is, both the second joint portion 120c and the second bent portion 133c in the fourth embodiment have the same thickness as the flat plate portion 131 (see FIG. 8).

このように、実施形態４に係る半導体装置４及びクリップリード１００ｃは、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なるが、実施形態１に係る半導体装置１及びクリップリード１００の場合と同様に、架橋部１３０ｃは、所定の厚みを有する平板部１３１ｃを有し、第１接合部１１０及び第１折り曲げ部１３２は、チップ１０と第１接合部１１０との間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するため、比較的大きな電流を導通可能でありながら熱サイクルストレスに対する耐性が高い半導体装置及びクリップリードとなる。 As described above, the semiconductor device 4 and the clip lead 100c according to the fourth embodiment differ from the semiconductor device 1 and the clip lead 100 according to the first embodiment in the shape of the clip lead, but the semiconductor device 1 according to the first embodiment is different. Similarly to the case of the clip lead 100, the bridging portion 130c has a flat plate portion 131c having a predetermined thickness, and the first joint portion 110 and the first bent portion 132 connect the chip 10 and the first joint portion 110. Since the thermal stress relaxation structure 140 for relaxing the thermal stress on the first joining member 30 between is configured, a semiconductor device and a clip lead that can conduct a relatively large current but have high resistance to thermal cycle stress.

また、実施形態４に係る半導体装置４及びクリップリード１００ｃによれば、第２接合部１２０ｃ及び第２折り曲げ部１３３ｃはいずれも平板部１３１ｃと同じ厚さであるため、放熱に寄与する体積が大きくなり、チップ１０から発生する熱をより効率よく外部に放出することができる。従って、チップ１０及び第１接合部１１０の温度上昇を抑えることができることから、高温時のチップ１０及び第１接合部１１０の膨張を抑制することができる。その結果、第１接合部材３０に加わる熱応力をより一層小さくすることができ、熱サイクルストレスに対する耐性をより一層高くすることができる。 Further, according to the semiconductor device 4 and the clip lead 100c according to the fourth embodiment, since the second joint portion 120c and the second bent portion 133c have the same thickness as the flat plate portion 131c, the volume contributing to heat dissipation is large. Therefore, the heat generated from the chip 10 can be released to the outside more efficiently. Therefore, since the temperature rise of the chip 10 and the first joint 110 can be suppressed, the expansion of the chip 10 and the first joint 110 at high temperature can be suppressed. As a result, the thermal stress applied to the first joining member 30 can be further reduced, and the resistance to thermal cycle stress can be further enhanced.

なお、実施形態４に係る半導体装置４及びクリップリード１００ｃは、クリップリードの形状以外の点においては実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するため、実施形態１に係る半導体装置１及びクリップリード１００が有する効果のうち該当する効果を有する。 The semiconductor device 4 and the clip lead 100c according to the fourth embodiment have the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment except for the shape of the clip lead, and thus the semiconductor device 4 and the clip lead 100c according to the first embodiment. This has the corresponding effect among the effects of the semiconductor device 1 and the clip lead 100.

［実施形態５］
図９は、実施形態５に係る半導体装置５の断面図である。
実施形態５に係る半導体装置５及びクリップリード１００ｄは、基本的には実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するが、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なる。すなわち、実施形態５における第１接合部１１０ｄにおいては、チップ１０と接合する面とは反対側の面に溝１３８が形成されている(図９参照。)。 [Fifth Embodiment]
FIG. 9 is a sectional view of the semiconductor device 5 according to the fifth embodiment.
The semiconductor device 5 and the clip lead 100d according to the fifth embodiment have basically the same configuration as the semiconductor device 1 and the clip lead 100 according to the first embodiment, but the shape of the clip lead is the semiconductor device according to the first embodiment. 1 and the clip lead 100. That is, in the first bonding portion 110d in the fifth embodiment, the groove 138 is formed on the surface opposite to the surface to be bonded to the chip 10 (see FIG. 9).

第２接合部１２０ｄにおいては、第２電極部２２と接合する面とは反対側の面に溝１３９が形成されている。 In the second bonding portion 120d, the groove 139 is formed on the surface opposite to the surface that is bonded to the second electrode portion 22.

このように、実施形態５に係る半導体装置５及びクリップリード１００ｄは、クリップリードの形状が実施形態１に係る半導体装置１及びクリップリード１００の場合とは異なるが、実施形態１に係る半導体装置１及びクリップリード１００の場合と同様に、架橋部１３０ｄは、所定の厚みを有する平板部１３１ｄを有し、第１接合部１１０ｄ及び第１折り曲げ部１３２は、チップ１０と第１接合部１１０ｄとの間の第１接合部材３０に対する熱応力を緩和するための熱応力緩和構造１４０を構成するため、比較的大きな電流を導通可能でありながら熱サイクルストレスに対する耐性が高い半導体装置及びクリップリードとなる。 As described above, the semiconductor device 5 and the clip lead 100d according to the fifth embodiment are different from the semiconductor device 1 and the clip lead 100 according to the first embodiment in the shape of the clip lead, but the semiconductor device 1 according to the first embodiment is different. Similarly to the case of the clip lead 100, the bridging portion 130d has a flat plate portion 131d having a predetermined thickness, and the first joining portion 110d and the first bending portion 132 connect the chip 10 and the first joining portion 110d. Since the thermal stress relaxation structure 140 for relaxing the thermal stress on the first joining member 30 between is configured, a semiconductor device and a clip lead that can conduct a relatively large current but have high resistance to thermal cycle stress.

また、実施形態５に係る半導体装置５及びクリップリード１００ｄによれば、第１接合部１１０ｄにおいては、チップ１０と接合する面とは反対側の面に溝１３８が形成されているため 、樹脂とクリップリード１００ｄとの密着性が高くなる。従って、熱によるクリップリード１００ｄの膨張・収縮が樹脂によって制限されるため、第１接合部材３０に対する熱応力を小さくすることができる。その結果、熱サイクルストレスに対する耐性をより一層高くすることができる。 Further, according to the semiconductor device 5 and the clip lead 100d according to the fifth embodiment, the groove 138 is formed on the surface on the side opposite to the surface to be bonded to the chip 10 in the first bonding portion 110d. The adhesiveness with the clip lead 100d becomes high. Therefore, the expansion/contraction of the clip lead 100d due to heat is limited by the resin, so that the thermal stress on the first joining member 30 can be reduced. As a result, resistance to thermal cycle stress can be further increased.

なお、実施形態５に係る半導体装置５及びクリップリード１００ｄは、クリップリードの形状以外の点においては実施形態１に係る半導体装置１及びクリップリード１００と同様の構成を有するため、実施形態１に係る半導体装置１及びクリップリード１００が有する効果のうち該当する効果を有する。 The semiconductor device 5 and the clip lead 100d according to the fifth embodiment have the same configurations as the semiconductor device 1 and the clip lead 100 according to the first embodiment except for the shape of the clip lead, and thus the semiconductor device 5 and the clip lead 100d according to the first embodiment. This has the corresponding effect among the effects of the semiconductor device 1 and the clip lead 100.

以上、本発明を上記の実施形態に基づいて説明したが、本発明は上記の実施形態に限定されるものではない。その趣旨を逸脱しない範囲において種々の態様において実施することが可能であり、例えば、次のような変形も可能である。 Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment. The present invention can be implemented in various modes without departing from the spirit of the invention, and the following modifications are possible, for example.

（１）上記各実施形態において記載した構成要素の数、形状、位置、大きさ等は例示であり、本発明の効果を損なわない範囲において変更することが可能である。 (1) The numbers, shapes, positions, sizes, etc. of the constituent elements described in each of the above-described embodiments are mere examples, and can be changed within a range that does not impair the effects of the present invention.

（２）上記実施形態２〜５においては、実施形態１を基に各実施形態を説明しているが、本発明はこれに限定されるものではない。実施形態１の特徴に加えて実施形態２〜５の特徴のうち複数の特徴を含む半導体装置及びクリップリードも本発明に含まれるものとする。 (2) In Embodiments 2 to 5 above, each embodiment is described based on Embodiment 1, but the present invention is not limited to this. It is assumed that the present invention also includes a semiconductor device and a clip lead including a plurality of features of the features of the second to fifth embodiments in addition to the features of the first embodiment.

（３）上記各実施形態において、基板の裏側（チップとは反対側の面）に放熱用のフィンＦが配置されているが、放熱フィンが配置されていなくてもよい。 (3) In each of the above embodiments, the fins F for heat dissipation are arranged on the back side of the substrate (the surface opposite to the chip), but the heat dissipation fins may not be arranged.

（４）上記各実施形態においては、第１折り曲げ部１３２及び第２折り曲げ部１３３の下側の表面にめっきが塗られていてもよい。このような構成とすることにより、接合工程においてはんだが第１折り曲げ部の下側や第２折り曲げ部の下側を這い上がりやすくなる、という効果を得ることができる。 (4) In each of the above embodiments, plating may be applied to the lower surface of the first bent portion 132 and the second bent portion 133. With such a configuration, it is possible to obtain the effect that the solder is likely to crawl below the first bent portion and below the second bent portion in the joining process.

（５）図１０は、変形例に係る半導体装置６を説明するために示す図である。図１０(ａ)は半導体装置６の平面図であり、図１０(ｂ)は半導体装置６の断面図である。
上記各実施形態においては、第１電極部及び第２電極部を基板Ｓ上に形成されたパターン配線としたが、本発明はこれに限定されるものではない。例えば、第１電極部（リードフレームＬＦ１のダイパッド）及び第２電極部（リードフレームＬＦ２の端子）を、離間した複数のリードフレームＬＦ１，ＬＦ２上にそれぞれ形成された所定の領域であるとしてもよい。このような半導体装置としては、例えばダイパッド及びドレイン電極端子を有するリードフレームＬＦ１とソース電極端子を有するＬＦ２とをクリップリードを用いて接続する半導体装置が考えられる(図１０参照。なお、図１０においてはＭＯＳＦＥＴであるが、ＩＧＢＴ等そのほか適宜の半導体装置でもよい。)。その他、第１電極部及び第２電極部が離間した位置に設けられ、第１電極部上にチップが配置され、チップと第２電極部がクリップリードで電気的に接続される構成であれば、適宜の構成を有する半導体装置であってもよい。 (5) FIG. 10 is a diagram for explaining the semiconductor device 6 according to the modification. 10A is a plan view of the semiconductor device 6, and FIG. 10B is a cross-sectional view of the semiconductor device 6.
In each of the above embodiments, the first electrode portion and the second electrode portion are the pattern wiring formed on the substrate S, but the present invention is not limited to this. For example, the first electrode portion (die pad of the lead frame LF1) and the second electrode portion (terminal of the lead frame LF2) may be predetermined regions formed on the plurality of spaced lead frames LF1 and LF2, respectively. .. As such a semiconductor device, for example, a semiconductor device in which a lead frame LF1 having a die pad and a drain electrode terminal and an LF2 having a source electrode terminal are connected using a clip lead is conceivable (see FIG. 10; in FIG. 10). Is a MOSFET, but it may be an appropriate semiconductor device such as an IGBT). In addition, if the first electrode portion and the second electrode portion are provided at positions separated from each other, the chip is arranged on the first electrode portion, and the chip and the second electrode portion are electrically connected by a clip lead Alternatively, it may be a semiconductor device having an appropriate configuration.

１，２，３，４，５，６，８００…半導体装置、１’…組立体、１０、８１０…チップ、１２，８１２…チップの一方の面の表面電極、１４，８１４…チップの他方の面の表面電極、２０，８２０…第１電極部、２２，８２２…第２電極部、３０,８３０…第１接合部材、４０，８４０…第２接合部材、５０，８５０…第３接合部材、６０…第４接合部材、７０…端子、８０…樹脂、１００，１００ａ，１００ｂ，１００ｃ，１００ｄ，１００ｅ，９００…クリップリード、１００’…異形条材、１００’’…銅平条材、１１０，１１０ｄ，１１０ｅ，９１０…第１接合部、１２０，１２０ｄ，１２０ｅ，９２０…第２接合部、１３０，１３０ａ，１３０ｂ，１３０ｃ，１３０ｄ，１３０ｅ，９３０…架橋部、１３１，１３１ａ，１３１ｂ，１３１ｃ，１３１ｄ，１３１ｅ，９３１…平板部、１３１’…板厚部、１３２，１３２ｅ，９３２…第１折り曲げ部、１３２’，１３３’…板薄部、１３３，１３３ｃ，１３３ｅ，９３３…第２折り曲げ部、１３４，１３４ａ，１３４ｂ，１３４ｅ，１３５，１３５ａ，１３５ｂ，１３５ｅ…肩部、１３６，１３７…段差部、１３８，１３９…溝、１４０…熱応力緩和部、Ｆ…フィン、Ｓ…基板、Ｗ…ワイヤ、ＬＦ１，ＬＦ２，ＬＦ３…リードフレーム 1, 2, 3, 4, 5, 6, 800... Semiconductor device, 1'... Assembly, 10, 810... Chip, 12, 812... Surface electrode on one side of chip, 14, 814... On the other side of chip Surface electrode, 20, 820... first electrode part, 22, 822... second electrode part, 30,830... first joining member, 40, 840... second joining member, 50, 850... third joining member, 60... 4th joining member, 70... Terminal, 80... Resin, 100, 100a, 100b, 100c, 100d, 100e, 900... Clip lead, 100'... Deformed strip, 100''... Copper flat strip, 110, 110d, 110e, 910... 1st joining part, 120, 120d, 120e, 920... 2nd joining part, 130, 130a, 130b, 130c, 130d, 130e, 930... Bridge part, 131, 131a, 131b, 131c, 131d , 131e, 931... Flat plate portion, 131'... Plate thickness portion, 132, 132e, 932... First bent portion, 132', 133'... Sheet thin portion, 133, 133c, 133e, 933... Second bent portion, 134 , 134a, 134b, 134e, 135, 135a, 135b, 135e... Shoulder portion, 136, 137... Step portion, 138, 139... Groove, 140... Thermal stress relaxation portion, F... Fin, S... Substrate, W... Wire, LF1, LF2, LF3... Lead frame

Claims (15)

一方の面及び他方の面にそれぞれ表面電極を有するチップと、
前記チップの前記一方の面の前記表面電極と電気的に接続されている第１電極部と、
前記第１電極部と間隔をあけて配置された第２電極部と、
前記チップの前記他方の面の前記表面電極と第１接合部材を介して接合された第１接合部、前記第１接合部と間隔をあけて配置され、前記第２電極部と第２接合部材を介して接合された第２接合部、及び、前記第１接合部と前記第２接合部とを架橋する架橋部を有し、前記チップと前記第２電極部とを電気的に接続するクリップリードとを備え、
前記架橋部は、
所定の厚みを有する平板部と、
前記平板部から下側に折り曲げられ、前記第１接合部と接続されている第１折り曲げ部と、
前記平板部から前記下側に折り曲げられ、前記第２接合部と接続されている第２折り曲げ部とを有し、
前記第１接合部及び前記第１折り曲げ部は、前記チップと前記第１接合部との間の前記第１接合部材に対する熱応力を緩和するための熱応力緩和構造を構成し、
前記熱応力緩和構造は、少なくとも前記第１接合部及び前記第１折り曲げ部が前記平板部よりも薄くなるように構成された構造を含むことを特徴とする半導体装置。 A chip having surface electrodes on one surface and the other surface,
A first electrode portion electrically connected to the surface electrode on the one surface of the chip;
A second electrode portion spaced apart from the first electrode portion;
A first joining portion joined to the surface electrode on the other surface of the chip via a first joining member, the first joining portion is arranged with a gap, and the second electrode portion and the second joining member are arranged. A clip that has a second joint portion joined via a bridge and a bridge portion that bridges the first joint portion and the second joint portion, and electrically connects the chip and the second electrode portion. With leads,
The bridge portion,
A flat plate portion having a predetermined thickness,
A first bent portion that is bent downward from the flat plate portion and is connected to the first joint portion;
A second bent portion that is bent from the flat plate portion to the lower side and is connected to the second joint portion,
The first joint portion and the first bent portion constitute a thermal stress relaxation structure for relaxing thermal stress on the first joint member between the chip and the first joint portion,
The semiconductor device, wherein the thermal stress relaxation structure includes a structure in which at least the first bonding portion and the first bent portion are thinner than the flat plate portion. 前記熱応力緩和構造は、少なくとも前記第１接合部及び前記第１折り曲げ部が異形条材を折り曲げることによって形成された構造を含むことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the thermal stress relaxation structure includes a structure in which at least the first joint portion and the first bent portion are formed by bending a profiled strip. 前記熱応力緩和構造は、前記第１接合部に対する前記第１折り曲げ部の傾斜角度が９０°〜１２０°の範囲内になるように構成された構造を含むことを特徴とする請求項１又は２に記載の半導体装置。 The said thermal stress relaxation structure contains the structure comprised so that the inclination angle of the said 1st bending part with respect to the said 1st junction may be in the range of 90 degrees-120 degrees. The semiconductor device according to 1. 前記クリップリードにおいては、前記第１折り曲げ部の前記チップ側の面全体が前記第１接合部材と接していることを特徴とする請求項１〜３のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein in the clip lead, the entire surface of the first bent portion on the chip side is in contact with the first joining member. 前記第１接合部においては、前記第１接合部の厚みのうちの少なくとも半分の厚みまで前記第１接合部材に埋められていることを特徴とする請求項１〜４のいずれかに記載の半導体装置。 The semiconductor according to any one of claims 1 to 4, wherein in the first bonding portion, at least half of the thickness of the first bonding portion is filled with the first bonding member. apparatus. 前記第２接合部及び前記第２折り曲げ部は、いずれも前記平板部よりも薄いことを特徴とする請求項１〜５のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein each of the second joint portion and the second bent portion is thinner than the flat plate portion. 前記第１接合部、前記第２接合部、前記第１折り曲げ部及び前記第２折り曲げ部はいずれも同じ厚さであることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the first joint portion, the second joint portion, the first bent portion, and the second bent portion all have the same thickness. 前記第２接合部及び前記第２折り曲げ部は、いずれも前記平板部と同じ厚さであることを特徴とする請求項１〜５のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the second joint portion and the second bent portion both have the same thickness as the flat plate portion. 前記架橋部は、前記平板部と前記第１折り曲げ部との間に前記平板部よりも薄い肩部をさらに有することを特徴とする請求項１〜８のいずれかに記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the bridge portion further has a shoulder portion thinner than the flat plate portion between the flat plate portion and the first bent portion. 前記肩部の下側の面と前記平板部の下側の面との間には段差部が形成されていることを特徴とする請求項９に記載の半導体装置。 10. The semiconductor device according to claim 9, wherein a step portion is formed between the lower surface of the shoulder portion and the lower surface of the flat plate portion. 前記第１接合部材と前記クリップリードとの接触面の端部が前記段差部にあることを特徴とする請求項１０に記載の半導体装置。 11. The semiconductor device according to claim 10, wherein an end portion of a contact surface between the first joining member and the clip lead is at the step portion. 前記肩部は、側面から見て階段状の肩部であることを特徴とする請求項９〜１１のいずれかに記載の半導体装置。 The semiconductor device according to claim 9, wherein the shoulder portion is a stepped shoulder portion when viewed from a side surface. 前記第１接合部においては、前記チップと接合する面とは反対側の面に溝が形成されていることを特徴とする請求項１〜１２のいずれかに記載の半導体装置。 13. The semiconductor device according to claim 1, wherein a groove is formed in a surface of the first bonding portion opposite to a surface of the first bonding portion, the surface being bonded to the chip. 請求項１〜１３のいずれかに記載の半導体装置を製造するための半導体装置の製造方法であって、
第１接合部、前記第１接合部と間隔をあけて配置された第２接合部、及び、前記第１接合部と前記第２接合部とを架橋する架橋部を有し、前記架橋部は、所定の厚みを有する平板部と、前記平板部から一方側に折り曲げられ、前記第１接合部と接続されている第１折り曲げ部と、前記平板部から前記一方側に折り曲げられ、前記第２接合部と接続されている第２折り曲げ部とを有するクリップリードをチップ及び電極部上に接合部材を介して配置するクリップリード配置工程と、
前記チップと前記第１接合部との間、及び、前記電極部と前記第２接合部との間をそれぞれ前記接合部材で接合する接合工程とを含み、
前記クリップリード配置工程においては、前記クリップリードとして、前記第１接合部及び前記第１折り曲げ部が前記第１接合部と前記チップとの間の前記接合部材に対する熱応力を緩和するための熱応力緩和構造を構成し、前記熱応力緩和構造は、少なくとも前記第１接合部及び前記第１折り曲げ部が前記平板部よりも薄くなるように構成された構造を含むクリップリードを前記チップ及び前記電極部上に配置することを特徴とする半導体装置の製造方法。 A semiconductor device manufacturing method for manufacturing the semiconductor device according to claim 1.
A first joint portion, a second joint portion spaced apart from the first joint portion, and a bridge portion bridging the first joint portion and the second joint portion, wherein the bridge portion is A flat plate portion having a predetermined thickness, a first bent portion bent from the flat plate portion to one side and connected to the first joining portion, and a first bent portion bent from the flat plate portion to the one side, A clip lead arranging step of arranging a clip lead having a second bent portion connected to the joint portion on the chip and the electrode portion via the joint member;
A bonding step of bonding the tip and the first bonding portion, and bonding the electrode portion and the second bonding portion with the bonding member,
In the clip lead arranging step, as the clip lead, the first joint portion and the first bent portion are thermal stresses for alleviating thermal stress on the joint member between the first joint portion and the chip. The chip and the electrode portion include a clip lead that constitutes a relaxation structure, and the thermal stress relaxation structure includes a structure in which at least the first joint portion and the first bent portion are thinner than the flat plate portion. A method for manufacturing a semiconductor device, which is characterized in that the semiconductor device is arranged above. 請求項１〜１３のいずれかに記載の半導体装置に用いることを特徴とするクリップリード。 A clip lead used for the semiconductor device according to claim 1.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4145495A1 (en) * 2021-09-01 2023-03-08 Infineon Technologies AG Method of manufacturing an electrical interconnect for a semiconductor device as well as the corresponding device having the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151554A (en) * 2000-08-31 2002-05-24 Nec Corp Semiconductor device
JP2009129952A (en) * 2007-11-20 2009-06-11 Denso Corp Semiconductor device
WO2014068936A1 (en) * 2012-11-05 2014-05-08 日本精工株式会社 Semiconductor module
WO2015059882A1 (en) * 2013-10-21 2015-04-30 日本精工株式会社 Semiconductor module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151554A (en) * 2000-08-31 2002-05-24 Nec Corp Semiconductor device
JP2009129952A (en) * 2007-11-20 2009-06-11 Denso Corp Semiconductor device
WO2014068936A1 (en) * 2012-11-05 2014-05-08 日本精工株式会社 Semiconductor module
WO2015059882A1 (en) * 2013-10-21 2015-04-30 日本精工株式会社 Semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4145495A1 (en) * 2021-09-01 2023-03-08 Infineon Technologies AG Method of manufacturing an electrical interconnect for a semiconductor device as well as the corresponding device having the same
US11756923B2 (en) 2021-09-01 2023-09-12 Infineon Technologies Ag High density and durable semiconductor device interconnect

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