JP2019212717A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor Download PDF

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JP2019212717A
JP2019212717A JP2018106422A JP2018106422A JP2019212717A JP 2019212717 A JP2019212717 A JP 2019212717A JP 2018106422 A JP2018106422 A JP 2018106422A JP 2018106422 A JP2018106422 A JP 2018106422A JP 2019212717 A JP2019212717 A JP 2019212717A
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layer
plating layer
internal electrode
ceramic capacitor
laminated
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JP7145652B2 (en
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晴菜 生方
haruna Ubukata
晴菜 生方
聡子 並木
Satoko Namiki
聡子 並木
篤博 柳澤
Atsuhiro Yanagisawa
篤博 柳澤
知徳 山藤
Tomonori Yamato
知徳 山藤
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Priority to JP2018106422A priority Critical patent/JP7145652B2/en
Priority to US16/417,323 priority patent/US11264168B2/en
Priority to TW108117485A priority patent/TWI807030B/en
Priority to KR1020190060423A priority patent/KR20190137692A/en
Priority to CN201910461518.8A priority patent/CN110556248B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
    • H01G4/1245—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates containing also titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/129—Ceramic dielectrics containing a glassy phase, e.g. glass ceramic

Abstract

To provide a laminated ceramic capacitor capable of suppressing hydrogen intrusion from an external electrode.SOLUTION: A laminated ceramic capacitor includes a laminated chip in which a dielectric layer mainly composed of ceramic and an internal electrode layer are alternately laminated, and the plurality of laminated internal electrode layers are formed so as to be exposed at two opposite end faces, and that has a substantially rectangular parallelepiped shape, and a pair of external electrodes formed on the two end faces, and the pair of external electrodes have a structure in which a plating layer is formed on a base layer, and the base layer is mainly composed of a metal or alloy containing at least one of Ni and Cu, and an inclusion containing Mo is provided on at least a part of the surface on the plating layer side.SELECTED DRAWING: Figure 1

Description

本発明は、積層セラミックコンデンサに関する。   The present invention relates to a multilayer ceramic capacitor.

積層セラミックコンデンサは、複数の誘電体層と複数の内部電極とが交互に積層された積層体と、積層体の表面に引き出された内部電極と導通するように積層体の表面に形成された一対の外部電極とを備えている。外部電極は、下地層上にめっき処理が施されている。特許文献１では、めっき処理の際に発生する水素が内部電極に吸蔵され、誘電体層を還元することで絶縁抵抗が劣化することが記載されている。また、特許文献１では、貴金属を主成分とする内部電極を用いた場合に水素の吸収を抑制する金属としてＮｉ（ニッケル）を添加することが記載されている。一方、特許文献２では、内部電極にＮｉが用いられている場合であっても、水素の影響によって絶縁抵抗の劣化が生じることが記載されている。   The multilayer ceramic capacitor is a pair formed on the surface of the multilayer body so as to be electrically connected to the multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked and the internal electrode drawn on the surface of the multilayer body. External electrodes. The external electrode is plated on the base layer. Patent Document 1 describes that the hydrogen generated during the plating process is occluded in the internal electrode, and the insulation resistance is deteriorated by reducing the dielectric layer. Patent Document 1 describes that Ni (nickel) is added as a metal that suppresses absorption of hydrogen when an internal electrode containing a noble metal as a main component is used. On the other hand, Patent Document 2 describes that even when Ni is used for the internal electrode, the insulation resistance is deteriorated due to the influence of hydrogen.

特開平１−８００１１号公報Japanese Patent Laid-Open No. 1-80011 特開２０１６−６６７８３号公報JP, 2006-66783, A

水素の影響を抑制するためには、水素の侵入経路である外部電極からの水素の侵入を抑制することが望まれる。   In order to suppress the influence of hydrogen, it is desired to suppress the intrusion of hydrogen from the external electrode which is a hydrogen intrusion route.

本発明は、上記課題に鑑みなされたものであり、外部電極からの水素の侵入を抑制することができる積層セラミックコンデンサを提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor that can suppress the intrusion of hydrogen from an external electrode.

本発明に係る積層セラミックコンデンサは、セラミックを主成分とする誘電体層と、内部電極層と、が交互に積層され、積層された複数の前記内部電極層が交互に対向する２端面に露出するように形成され、略直方体形状を有する積層チップと、前記２端面に形成された１対の外部電極と、を備え、前記１対の外部電極は、下地層上にめっき層が形成された構造を有し、前記下地層は、ＮｉおよびＣｕの少なくともいずれか一方を含む金属または合金を主成分とし、前記めっき層側の表面の少なくとも一部に、Ｍｏを含む介在物が備わることを特徴とする。   In the multilayer ceramic capacitor according to the present invention, dielectric layers mainly composed of ceramic and internal electrode layers are alternately stacked, and the plurality of stacked internal electrode layers are exposed at two opposite end faces. A laminated chip having a substantially rectangular parallelepiped shape and a pair of external electrodes formed on the two end faces, wherein the pair of external electrodes has a plating layer formed on a base layer The underlayer is mainly composed of a metal or alloy containing at least one of Ni and Cu, and at least part of the surface on the plating layer side is provided with inclusions containing Mo. To do.

上記積層セラミックコンデンサにおいて、前記めっき層は、Ｓｎめっき層を含んでいてもよい。   In the multilayer ceramic capacitor, the plating layer may include a Sn plating layer.

上記積層セラミックコンデンサにおいて、前記下地層の主成分金属をＮｉとしてもよい。   In the multilayer ceramic capacitor, the main component metal of the base layer may be Ni.

上記積層セラミックコンデンサにおいて、前記内部電極層は、Ｎｉを主成分としてもよい。   In the multilayer ceramic capacitor, the internal electrode layer may contain Ni as a main component.

上記積層セラミックコンデンサにおいて、前記誘電体層の主成分セラミックは、ペロブスカイト構造を有していてもよい。   In the multilayer ceramic capacitor, the main component ceramic of the dielectric layer may have a perovskite structure.

本発明によれば、外部電極からの水素の侵入を抑制することができる。   According to the present invention, intrusion of hydrogen from the external electrode can be suppressed.

積層セラミックコンデンサの部分断面斜視図である。It is a partial section perspective view of a multilayer ceramic capacitor. 図１のＡ−Ａ線の部分断面図である。It is a fragmentary sectional view of the AA line of FIG. 積層セラミックコンデンサの製造方法のフローを例示する図である。It is a figure which illustrates the flow of the manufacturing method of a multilayer ceramic capacitor. （ａ）はＳＴＥＭを用いて下地層およびＣｕめっき層を観察した結果を示す図であり、（ｂ）はＳＴＥＭ−ＥＤＳを用いて下地層およびＣｕめっき層におけるＭｏの分布を測定した結果である。(A) is a figure which shows the result of having observed the base layer and Cu plating layer using STEM, (b) is the result of having measured distribution of Mo in a base layer and Cu plating layer using STEM-EDS. . （ａ）は測定箇所を例示する図であり、（ｂ）はＢ線断面におけるＭｏ濃度の測定結果である。(A) is a figure which illustrates a measurement location, (b) is a measurement result of Mo concentration in a B line section.

以下、図面を参照しつつ、実施形態について説明する。   Hereinafter, embodiments will be described with reference to the drawings.

（実施形態）
まず、積層セラミックコンデンサについて説明する。図１は、積層セラミックコンデンサ１００の部分断面斜視図である。図１で例示するように、積層セラミックコンデンサ１００は、直方体形状を有する積層チップ１０と、積層チップ１０のいずれかの対向する２端面に設けられた外部電極２０ａ，２０ｂとを備える。なお、積層チップ１０の当該２端面以外の４面を側面と称する。外部電極２０ａ，２０ｂは、４つの側面に延在している。ただし、外部電極２０ａ，２０ｂは、４つの側面において互いに離間している。 (Embodiment)
First, a multilayer ceramic capacitor will be described. FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100. As illustrated in FIG. 1, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape, and external electrodes 20 a and 20 b provided on two opposing end faces of the multilayer chip 10. Note that four surfaces other than the two end surfaces of the laminated chip 10 are referred to as side surfaces. The external electrodes 20a and 20b extend on four side surfaces. However, the external electrodes 20a and 20b are separated from each other on the four side surfaces.

積層チップ１０は、誘電体として機能するセラミック材料を含む誘電体層１１と、卑金属材料を含む内部電極層１２とが、交互に積層された構成を有する。各内部電極層１２の端縁は、積層チップ１０の外部電極２０ａが設けられた端面と、外部電極２０ｂが設けられた端面とに、交互に露出している。それにより、各内部電極層１２は、外部電極２０ａと外部電極２０ｂとに、交互に導通している。その結果、積層セラミックコンデンサ１００は、複数の誘電体層１１が内部電極層１２を介して積層された構成を有する。また、積層チップ１０において、４つの側面のうち、誘電体層１１と内部電極層１２との積層方向（以下、積層方向と称する。）の上面と下面とに対応する２側面は、カバー層１３によって覆われている。カバー層１３は、セラミック材料を主成分とする。例えば、カバー層１３の材料は、誘電体層１１とセラミック材料の主成分が同じである。   The multilayer chip 10 has a configuration in which dielectric layers 11 including a ceramic material functioning as a dielectric and internal electrode layers 12 including a base metal material are alternately stacked. The edge of each internal electrode layer 12 is alternately exposed on the end surface of the multilayer chip 10 where the external electrode 20a is provided and the end surface where the external electrode 20b is provided. Thereby, each internal electrode layer 12 is alternately conducted to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are stacked via the internal electrode layer 12. In the multilayer chip 10, of the four side surfaces, two side surfaces corresponding to the upper surface and the lower surface in the stacking direction of the dielectric layer 11 and the internal electrode layer 12 (hereinafter referred to as the stacking direction) are the cover layer 13. Covered by. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layer 11 and the ceramic material.

積層セラミックコンデンサ１００のサイズは、例えば、長さ０．２５ｍｍ、幅０．１２５ｍｍ、高さ０．１２５ｍｍであり、または長さ０．４ｍｍ、幅０．２ｍｍ、高さ０．２ｍｍ、または長さ０．６ｍｍ、幅０．３ｍｍ、高さ０．３ｍｍであり、または長さ１．０ｍｍ、幅０．５ｍｍ、高さ０．５ｍｍであり、または長さ３．２ｍｍ、幅１．６ｍｍ、高さ１．６ｍｍであり、または長さ４．５ｍｍ、幅３．２ｍｍ、高さ２．５ｍｍであるが、これらのサイズに限定されるものではない。   The size of the multilayer ceramic capacitor 100 is, for example, a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, a height of 0.2 mm, or a length. 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm, width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height The length is 1.6 mm, or the length is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but is not limited to these sizes.

内部電極層１２は、Ｎｉ，Ｃｕ（銅），Ｓｎ（スズ）等の卑金属を主成分とする。内部電極層１２として、Ｐｔ（白金）、Ｐｄ（パラジウム）、Ａｇ（銀）、Ａｕ（金）などの貴金属やこれらを含む合金を用いてもよい。誘電体層１１は、例えば、一般式ＡＢＯ３で表されるペロブスカイト構造を有するセラミック材料を主成分とする。なお、当該ペロブスカイト構造は、化学量論組成から外れたＡＢＯ３−αを含む。例えば、当該セラミック材料として、ＢａＴｉＯ３（チタン酸バリウム）、ＣａＺｒＯ３（ジルコン酸カルシウム）、ＣａＴｉＯ３（チタン酸カルシウム）、ＳｒＴｉＯ３（チタン酸ストロンチウム）、ペロブスカイト構造を形成するＢａ１-ｘ−ｙＣａｘＳｒｙＴｉ１−ｚＺｒｚＯ３(０≦ｘ≦１，０≦ｙ≦１，０≦ｚ≦１)等を用いることができる。 The internal electrode layer 12 contains a base metal such as Ni, Cu (copper), or Sn (tin) as a main component. As the internal electrode layer 12, a noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or an alloy containing these may be used. The dielectric layer 11 includes, for example, a ceramic material having a perovskite structure represented by the general formula ABO 3 as a main component. Note that the perovskite structure includes ABO 3-α deviating from the stoichiometric composition. For example, as the ceramic material, BaTiO 3 (barium titanate), CaZrO 3 (calcium zirconate), CaTiO 3 (calcium titanate), SrTiO 3 (strontium titanate), and Ba 1-xy that forms a perovskite structure. Ca x Sr y Ti 1-z Zr z O 3 (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) , or the like can be used.

図２は、外部電極２０ａの断面図であり、図１のＡ−Ａ線の部分断面図である。なお、図２では断面を表すハッチを省略している。図２で例示するように、外部電極２０ａは、下地層２１上に、Ｃｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４が形成された構造を有する。下地層２１、Ｃｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４は、積層チップ１０の両端面から４つの側面に延在している。なお、図２では、外部電極２０ａについて例示しているが、外部電極２０ｂも同様の構造を有する。   2 is a cross-sectional view of the external electrode 20a, and is a partial cross-sectional view taken along line AA of FIG. In FIG. 2, a hatch indicating a cross section is omitted. As illustrated in FIG. 2, the external electrode 20 a has a structure in which a Cu plating layer 22, a Ni plating layer 23, and a Sn plating layer 24 are formed on a base layer 21. The underlayer 21, the Cu plating layer 22, the Ni plating layer 23, and the Sn plating layer 24 extend from the both end surfaces of the multilayer chip 10 to four side surfaces. Although FIG. 2 illustrates the external electrode 20a, the external electrode 20b has a similar structure.

下地層２１は、ＮｉおよびＣｕの少なくともいずれか一方を含む金属または合金を主成分とし、下地層２１の緻密化のためのガラス成分を含んでいてもよく、下地層２１の焼結性を制御するための共材を含んでいてもよい。ガラス成分は、Ｂａ，Ｓｒ，Ｃａ，Ｚｎ（亜鉛），Ａｌ（アルミニウム），Ｓｉ（ケイ素），Ｂ（ホウ素）等の酸化物である。共材は、セラミック成分であり、例えば、誘電体層１１が主成分とするセラミック成分である。   The underlayer 21 is mainly composed of a metal or alloy containing at least one of Ni and Cu, may contain a glass component for densification of the underlayer 21, and controls the sinterability of the underlayer 21. A common material for the purpose may be included. The glass component is an oxide such as Ba, Sr, Ca, Zn (zinc), Al (aluminum), Si (silicon), and B (boron). The common material is a ceramic component, for example, a ceramic component mainly composed of the dielectric layer 11.

また、下地層２１のめっき層側の表面に、Ｍｏ（モリブデン）を含む介在物２５が形成されている。下地層２１の表面にＭｏを含む介在物２５が形成されていることから、Ｃｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４を形成する場合に発生する水素が下地層２１および内部電極層１２に侵入することが抑制される。例えば、Ｍｏは、水素透過を妨げる働きを有している。水素透過を妨げるＭｏを含む介在物２５が下地層２１の表面に存在することで、外部電極２０ａ，２０ｂにおける水素の透過性が低下し、水素の侵入経路を遮断している（ブロッキング効果を発揮している）と考えられる。水素の侵入経路が遮断されれば、下地層２１および内部電極層１２への水素の吸蔵が抑制され、誘電体層１１の還元が抑制される。それにより、積層セラミックコンデンサ１００の絶縁抵抗の低下が抑制される。なお、Ｃｕめっき層２２およびＮｉめっき層２３のめっき工程では、めっき対象の表面で水素が多く発生する。したがって、水素の侵入経路を遮断することは特に効果的である。   An inclusion 25 containing Mo (molybdenum) is formed on the surface of the base layer 21 on the plating layer side. Since inclusions 25 containing Mo are formed on the surface of the underlayer 21, hydrogen generated when forming the Cu plating layer 22, the Ni plating layer 23, and the Sn plating layer 24 is generated by the underlayer 21 and the internal electrode layer. 12 is suppressed from entering. For example, Mo has a function of hindering hydrogen permeation. The inclusion 25 containing Mo that hinders hydrogen permeation is present on the surface of the underlayer 21, so that the hydrogen permeability in the external electrodes 20a and 20b is reduced and the hydrogen intrusion path is blocked (the blocking effect is exhibited) it seems to do. If the hydrogen intrusion path is blocked, the occlusion of hydrogen into the base layer 21 and the internal electrode layer 12 is suppressed, and the reduction of the dielectric layer 11 is suppressed. Thereby, a decrease in the insulation resistance of the multilayer ceramic capacitor 100 is suppressed. In the plating process of the Cu plating layer 22 and the Ni plating layer 23, a large amount of hydrogen is generated on the surface of the plating target. Therefore, it is particularly effective to block the hydrogen entry path.

介在物２５の形状は、特に限定されるものではない。例えば、介在物２５は、下地層２１の表面を覆うように層状に形成されていてもよい。または、介在物２５は、下地層２１の表面において島状に点在していてもよい。また、介在物２５は、Ｍｏの化合物を主成分とする。介在物２５の主成分であるＭｏ化合物は、酸化モリブデン（ＭｏＯ２、ＭｏＯ３）などである。 The shape of the inclusion 25 is not particularly limited. For example, the inclusions 25 may be formed in layers so as to cover the surface of the base layer 21. Alternatively, the inclusions 25 may be scattered in an island shape on the surface of the base layer 21. The inclusion 25 contains a Mo compound as a main component. The Mo compound that is the main component of the inclusion 25 is molybdenum oxide (MoO 2 , MoO 3 ) or the like.

なお、本実施形態においては、下地層２１の表面に存在する元素としてＭｏに着目しているが、それに限られない。水素透過を妨げる効果を有する元素をＭｏの代わりに用いてもよい。   In the present embodiment, attention is focused on Mo as an element present on the surface of the underlayer 21, but the present invention is not limited to this. An element having an effect of preventing hydrogen permeation may be used instead of Mo.

なお、内部電極層１２がＮｉを主成分とすると、内部電極層１２の水素吸蔵性が高くなる。したがって、内部電極層１２がＮｉを主成分とする場合には、外部電極２０ａ，２０ｂからの水素侵入を抑制することが特に効果的である。また、Ｃｕめっき層２２およびＮｉめっき層２３のめっき工程では、めっき対象の表面で水素が多く発生する。したがって、水素の侵入経路を遮断することは特に効果的である。   In addition, when the internal electrode layer 12 has Ni as a main component, the hydrogen occlusion property of the internal electrode layer 12 becomes high. Therefore, when the internal electrode layer 12 contains Ni as a main component, it is particularly effective to suppress hydrogen intrusion from the external electrodes 20a and 20b. Further, in the plating process of the Cu plating layer 22 and the Ni plating layer 23, a large amount of hydrogen is generated on the surface to be plated. Therefore, it is particularly effective to block the hydrogen entry path.

また、Ｓｎは高い緻密性を有している。これは、Ｓｎが最密充填構造を有することに起因する。下地層２１上にＳｎめっき層３４が設けられていると、水素がＳｎめっき層３４よりも積層チップ１０側に閉じ込められることになる。すなわち、水素の影響が生じやすくなる。したがって、下地層２１上にＳｎめっき層３４が設けられている場合には、外部電極２０ａ，２０ｂからの水素侵入を抑制することが特に効果的である。   Sn has a high density. This is because Sn has a close-packed structure. When the Sn plating layer 34 is provided on the base layer 21, hydrogen is confined to the laminated chip 10 side than the Sn plating layer 34. That is, the influence of hydrogen tends to occur. Therefore, when the Sn plating layer 34 is provided on the foundation layer 21, it is particularly effective to suppress hydrogen intrusion from the external electrodes 20a and 20b.

続いて、積層セラミックコンデンサ１００の製造方法について説明する。図３は、積層セラミックコンデンサ１００の製造方法のフローを例示する図である。   Then, the manufacturing method of the multilayer ceramic capacitor 100 is demonstrated. FIG. 3 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

（原料粉末作製工程）
まず、誘電体層１１の主成分であるセラミック材料の粉末に、目的に応じて所定の添加化合物を添加する。添加化合物としては、Ｍｇ（マグネシウム），Ｍｎ（マンガン），Ｖ（バナジウム），Ｃｒ（クロム），希土類元素(Ｙ（イットリウム）,Ｓｍ（サマリウム），Ｅｕ（ユウロピウム），Ｇｄ（ガドリニウム），Ｔｂ（テルビウム），Ｄｙ（ジスプロシウム）,Ｈｏ（ホロミウム）,Ｅｒ(エルビウム)，Ｔｍ（ツリウム）およびＹｂ（イッテルビウム）)の酸化物、並びに、Ｃｏ（コバルト），Ｎｉ，Ｌｉ（リチウム），Ｂ，Ｎａ（ナトリウム），Ｋ（カリウム）およびＳｉの酸化物もしくはガラスが挙げられる。例えば、まず、セラミック材料の粉末に添加化合物を含む化合物を混合して仮焼を行う。続いて、得られたセラミック材料の粒子を添加化合物とともに湿式混合し、乾燥および粉砕してセラミック材料の粉末を調製する。 (Raw material powder production process)
First, a predetermined additive compound is added to the ceramic material powder as the main component of the dielectric layer 11 according to the purpose. As additive compounds, Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb ( (Terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), and Co (cobalt), Ni, Li (lithium), B, Na ( Sodium), K (potassium) and Si oxides or glasses. For example, first, a ceramic material powder is mixed with a compound containing an additive compound and calcined. Subsequently, the obtained ceramic material particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic material powder.

（積層工程）
次に、得られたセラミック材料の粉末に、ポリビニルブチラール（ＰＶＢ）樹脂等のバインダと、エタノール、トルエン等の有機溶剤と、可塑剤とを加えて湿式混合する。得られたスラリーを使用して、例えばダイコータ法やドクターブレード法により、基材上に例えば厚み０．８μｍ以下の帯状の誘電体グリーンシートを塗工して乾燥させる。 (Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained powder of ceramic material and wet mixed. Using the obtained slurry, for example, a band-shaped dielectric green sheet having a thickness of 0.8 μm or less is applied on a substrate by, for example, a die coater method or a doctor blade method and dried.

次に、誘電体グリーンシートの表面に、内部電極形成用導電ペーストをスクリーン印刷、グラビア印刷等により印刷することで、内部電極層１２のパターンを配置する。内部電極層形成用導電ペーストは、内部電極層１２の主成分金属の粉末と、バインダと、溶剤と、必要に応じてその他助剤とを含んでいる。バインダおよび溶剤は、上記したセラミックスラリーと異なるものを使用することが好ましい。また、内部電極形成用導電ペーストには、共材として、誘電体層１１の主成分であるセラミック材料を分散させてもよい。   Next, the pattern of the internal electrode layer 12 is arranged on the surface of the dielectric green sheet by printing the internal electrode forming conductive paste by screen printing, gravure printing or the like. The internal electrode layer-forming conductive paste contains the main component metal powder of the internal electrode layer 12, a binder, a solvent, and other auxiliary agents as required. It is preferable to use a binder and a solvent different from the above ceramic slurry. In addition, in the internal electrode forming conductive paste, a ceramic material that is a main component of the dielectric layer 11 may be dispersed as a co-material.

次に、内部電極層パターンが印刷された誘電体グリーンシートを所定の大きさに打ち抜いて、打ち抜かれた誘電体グリーンシートを、基材を剥離した状態で、内部電極層１２と誘電体層１１とが互い違いになるように、かつ内部電極層１２が誘電体層１１の長さ方向両端面に端縁が交互に露出して極性の異なる一対の外部電極に交互に引き出されるように、所定層数（例えば２００〜５００層）だけ積層する。積層したパターン形成シートの上下にカバー層１３となるカバーシートを圧着させ、所定チップ寸法（例えば１．０ｍｍ×０．５ｍｍ）にカットする。これにより、略直方体形状のセラミック積層体が得られる。   Next, the dielectric green sheet on which the internal electrode layer pattern is printed is punched to a predetermined size, and the punched dielectric green sheet is peeled off from the base electrode and the internal electrode layer 12 and the dielectric layer 11. And the internal electrode layers 12 are alternately exposed to a pair of external electrodes having different polarities so that the edges are alternately exposed on both end faces in the length direction of the dielectric layer 11. A number of layers (for example, 200 to 500 layers) are stacked. A cover sheet to be the cover layer 13 is pressure-bonded on the upper and lower sides of the laminated pattern forming sheet, and cut into a predetermined chip size (for example, 1.0 mm × 0.5 mm). Thereby, a substantially rectangular parallelepiped ceramic laminate is obtained.

（金属ペースト塗布工程）
次に、積層工程で得られたセラミック積層体を、２００℃〜５００℃のＮ２雰囲気中で脱バインダした後に、セラミック積層体の両端面から各側面にかけて、金属フィラー、共材、バインダ、溶剤およびＭｏ源を含む金属ペーストを塗布し、乾燥させる。この金属ペーストは、外部電極形成用金属ペーストである。このとき、Ｍｏ源の濃度が表面側で高くなるように塗布し、乾燥させることが好ましい。例えば、Ｍｏ源の濃度が異なる外部電極形成用金属ペーストを用意し、セラミック積層体の端面側のＭｏ源の濃度が低く、表面側のＭｏ源の濃度が高くなるようにしてもよい。 (Metal paste application process)
Next, after removing the binder in the N 2 atmosphere at 200 ° C. to 500 ° C. from the ceramic laminate obtained in the lamination step, the metal filler, the co-material, the binder, the solvent are applied from both end faces to each side face of the ceramic laminate. A metal paste containing Mo and Mo sources is applied and dried. This metal paste is a metal paste for forming an external electrode. At this time, it is preferable to apply and dry the Mo source so that the concentration of the Mo source is higher on the surface side. For example, external electrode forming metal pastes having different Mo source concentrations may be prepared so that the Mo source concentration on the end face side of the ceramic laminate is low and the Mo source concentration on the surface side is high.

Ｍｏ源の種類、形状等は特に限定されない。例えば、Ｍｏ源として、具体的には、酸化モリブデン（ＭｏＯ２，ＭｏＯ３）、塩化モリブデン（ＭｏＣｌ２，ＭｏＣｌ３，ＭｏＣｌ４）、水酸化モリブデン（Ｍｏ（ＯＨ）３，Ｍｏ（ＯＨ）５）、モリブデン酸バリウム（ＢａＭｏＯ４）、モリブデン酸アンモニウム（（ＮＨ４）６Ｍｏ７Ｏ２４・４Ｈ２Ｏ）、モリブデン−ニッケル合金等を用いることができる。また、共材にＭｏを予め固溶させておき、当該共材をＭｏ源として用いてもよい。 The type and shape of the Mo source are not particularly limited. For example, as the Mo source, specifically, molybdenum oxide (MoO 2 , MoO 3 ), molybdenum chloride (MoCl 2 , MoCl 3 , MoCl 4 ), molybdenum hydroxide (Mo (OH) 3 , Mo (OH) 5 ) Barium molybdate (BaMoO 4 ), ammonium molybdate ((NH 4 ) 6 Mo 7 O 24 · 4H 2 O), molybdenum-nickel alloy, or the like can be used. Alternatively, Mo may be previously dissolved in the common material, and the common material may be used as the Mo source.

（焼成工程）
次に、外部電極形成用金属ペーストが塗布されたセラミック積層体を、還元雰囲気中で１１００〜１３００℃で１０分〜２時間焼成する。このようにして、内部に焼結体からなる誘電体層１１と内部電極層１２とが交互に積層されてなる積層チップ１０と、積層方向上下の最外層として形成されるカバー層１３と、下地層２１とを有する焼結体が得られる。 (Baking process)
Next, the ceramic laminate coated with the external electrode forming metal paste is fired at 1100 to 1300 ° C. for 10 minutes to 2 hours in a reducing atmosphere. Thus, the laminated chip 10 in which the dielectric layers 11 and the internal electrode layers 12 made of a sintered body are alternately laminated, the cover layer 13 formed as the outermost layer above and below the lamination direction, A sintered body having the formation 21 is obtained.

（めっき処理工程）
その後、めっき処理工程を実施することによって、Ｃｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４を、下地層２１上に順に形成する。以上の工程を経て、積層セラミックコンデンサ１００が完成する。 (Plating process)
Thereafter, the Cu plating layer 22, the Ni plating layer 23, and the Sn plating layer 24 are sequentially formed on the base layer 21 by performing a plating process. Through the above steps, the multilayer ceramic capacitor 100 is completed.

図４（ａ）は、ＳＴＥＭ（Scanning Transmission Electron Microscope）を用いて下地層２１およびＣｕめっき層２２を観察した結果である。図４（ａ）に示すように、下地層２１とＣｕめっき層２２との間に界面２６が生じていることがわかる。   FIG. 4A shows the result of observing the base layer 21 and the Cu plating layer 22 using a STEM (Scanning Transmission Electron Microscope). As shown in FIG. 4A, it can be seen that an interface 26 is generated between the base layer 21 and the Cu plating layer 22.

図４（ｂ）は、ＳＴＥＭ−ＥＤＳ（Energy−Dispersive-Spectroscopy）を用いて下地層２１およびＣｕめっき層２２におけるＭｏの分布を測定した結果である。図４（ｂ）の測定領域は、図４（ａ）の測定領域と同範囲である。図４（ｂ）の例では、中央部分の網掛け部分がＭｏ濃度の比較的高い分布領域であり、介在物２５に相当する。網掛けになっていない領域がＭｏの検出されなかった領域である。図４（ａ）および図４（ｂ）の結果から、下地層２１のめっき層側表面に、Ｍｏを含む介在物２５が形成されていることがわかる。   FIG. 4B shows the result of measuring the Mo distribution in the underlayer 21 and the Cu plating layer 22 using STEM-EDS (Energy-Dispersive-Spectroscopy). The measurement region in FIG. 4B is the same range as the measurement region in FIG. In the example of FIG. 4B, the shaded portion at the center is a distribution region having a relatively high Mo concentration and corresponds to the inclusion 25. A region not shaded is a region where Mo was not detected. From the results of FIG. 4A and FIG. 4B, it can be seen that inclusions 25 containing Mo are formed on the surface of the base layer 21 on the plating layer side.

図４（ａ）と図４（ｂ）とを対比すると、Ｍｏが局在化していることがわかった。この結果から、ＮｉやＣｕとＭｏとは互いに固溶せずに金属間化合物を形成せず、互いに独立して分布していることがわかる。したがって、Ｍｏは水素透過係数が非常に低い単体のＭｏとして存在していることがわかる。以上のことから、外部電極２０ａ，２０ｂからの水素の侵入経路を遮断している（ブロッキング効果を発揮している）ことが裏付けられた。なお、Ｍｏが局在化する理由としては、Ｍｏ源を含む金属ペーストの焼き付けを、Ｍｏ源の融点より高い温度で行うことで、融解したＭｏ源が下地層２１の表面に析出したものと考えられる。   Comparing FIG. 4A and FIG. 4B, it was found that Mo was localized. From this result, it can be seen that Ni, Cu, and Mo do not form a solid solution with each other, do not form an intermetallic compound, and are distributed independently of each other. Therefore, it can be seen that Mo exists as a single Mo having a very low hydrogen permeability coefficient. From the above, it was confirmed that the hydrogen intrusion path from the external electrodes 20a and 20b is blocked (the blocking effect is exhibited). In addition, it is considered that Mo is localized because the molten Mo source is deposited on the surface of the underlayer 21 by baking the metal paste containing the Mo source at a temperature higher than the melting point of the Mo source. It is done.

次に、ＸＰＳ（X-ray Photoelectron Spectroscopy）とＡｒ(アルゴン)スパッタによる、下地層２１の表面から誘電体層１１に向かう深さ方向における、Ｍｏ濃度の測定結果について説明する。図５（ａ）は、測定箇所を例示する図である。図５（ａ）で例示するように、下地層２１の表面から誘電体層１１に向かう深さ方向におけるＢ線断面についてＮｉ濃度を基準としたＭｏ濃度を測定した。図５（ｂ）は、Ｂ線断面におけるＭｏ濃度の測定結果である。図５（ｂ）において、横軸は下地層２１の表面から誘電体層１１に向かう深さ方向の距離を表し、縦軸はＮｉ濃度を基準としたＭｏ濃度の正規化値である。具体的には、各測定地点においてＸＰＳによる組成分析をおこない、Ｎｉ濃度を基準としてＭｏの濃度を算出し、積層チップ１０の端面におけるＮｉ濃度を１とした場合の正規化値（ａｔ％）である。Ｂ線断面において、下地層２１の表面近傍にＭｏが存在していることがわかる。すなわち、下地層２１の表面においてＭｏが検出され、下地層２１の表面から誘電体層１１に向かう深さ方向において表面以外から検出限界以上のＭｏが検出されなかった。すなわち、下地層２１の表面にＭｏが局在していることが裏付けられている。加えて、深さ方向に２０ｎｍ間隔で測定を行ったが、最初の測定地点のみで検出限界以上のＭｏが検出されているため、Ｍｏの局在は深さ方向において２０ｎｍ以下の厚みであることも確認できた。   Next, the measurement result of the Mo concentration in the depth direction from the surface of the underlayer 21 toward the dielectric layer 11 by XPS (X-ray Photoelectron Spectroscopy) and Ar (argon) sputtering will be described. FIG. 5A is a diagram illustrating measurement locations. As illustrated in FIG. 5A, the Mo concentration based on the Ni concentration was measured for the B line cross section in the depth direction from the surface of the base layer 21 toward the dielectric layer 11. FIG. 5B is a measurement result of the Mo concentration in the B line cross section. In FIG. 5B, the horizontal axis represents the distance in the depth direction from the surface of the base layer 21 toward the dielectric layer 11, and the vertical axis represents the normalized value of the Mo concentration based on the Ni concentration. Specifically, composition analysis by XPS is performed at each measurement point, the concentration of Mo is calculated based on the Ni concentration, and the normalized value (at%) when the Ni concentration at the end face of the multilayer chip 10 is 1. is there. It can be seen that Mo is present in the vicinity of the surface of the underlayer 21 in the B line cross section. That is, Mo was detected on the surface of the underlayer 21, and Mo beyond the detection limit was not detected from other than the surface in the depth direction from the surface of the underlayer 21 toward the dielectric layer 11. That is, it is confirmed that Mo is localized on the surface of the base layer 21. In addition, measurement was performed at intervals of 20 nm in the depth direction, but Mo above the detection limit was detected only at the first measurement point, and therefore the localization of Mo has a thickness of 20 nm or less in the depth direction. Was also confirmed.

本実施形態に係る製造方法によれば、下地層２１のめっき層側の表面にＭｏを含む介在物２５が形成される。この場合、Ｃｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４を形成する場合に発生する水素が内部電極層１２に侵入することが抑制される。それにより、内部電極層１２への水素の吸蔵が抑制され、誘電体層１１の還元が抑制される。その結果、絶縁抵抗の低下が抑制される。また、Ｍｏを含む介在物２５が２０ｎｍ以下の厚みで形成されることで、下地層２１上に形成されるめっき層に対する密着性の低下が抑制される。   According to the manufacturing method according to the present embodiment, inclusions 25 containing Mo are formed on the surface of the base layer 21 on the plating layer side. In this case, hydrogen generated when the Cu plating layer 22, the Ni plating layer 23, and the Sn plating layer 24 are formed is prevented from entering the internal electrode layer 12. Thereby, the occlusion of hydrogen into the internal electrode layer 12 is suppressed, and the reduction of the dielectric layer 11 is suppressed. As a result, a decrease in insulation resistance is suppressed. Moreover, since the inclusion 25 containing Mo is formed with a thickness of 20 nm or less, a decrease in adhesion to the plating layer formed on the base layer 21 is suppressed.

なお、外部電極形成前の金属ペーストにＭｏ源を添加せずに、例えば金属ペースト塗布後に、スパッタ等でＭｏ源の膜を形成する方法も可能である。   It is also possible to form a Mo source film by sputtering or the like after applying the metal paste without adding the Mo source to the metal paste before forming the external electrode.

以下、実施形態に係る積層セラミックコンデンサを作製し、特性について調べた。   Hereinafter, the multilayer ceramic capacitor according to the embodiment was produced, and the characteristics were examined.

（実施例）
チタン酸バリウム粉末に必要な添加物を添加し、ボールミルで十分に湿式混合粉砕して誘電体材料を得た。誘電体材料に有機バインダおよび溶剤を加えてドクターブレード法にて誘電体グリーンシートを作製した。誘電体グリーンシートの塗工厚みを０．８μｍとし、有機バインダとしてポリビニルブチラール（ＰＶＢ）等を用い、溶剤としてエタノール、トルエン酸等を加えた。その他、可塑剤などを加えた。次に、内部電極層１２の主成分金属の粉末と、バインダと、溶剤と、必要に応じてその他助剤とを含んでいる内部電極形成用導電ペーストを作製した。内部電極形成用導電ペーストの有機バインダおよび溶剤には、誘電体グリーンシートとは異なるものを用いた。誘電体シートに内部電極形成用導電ペーストをスクリーン印刷した。内部電極形成用導電ペーストを印刷したシートを２５０枚重ね、その上下にカバーシートをそれぞれ積層した。その後、熱圧着によりセラミック積層体を得て、所定の形状に切断した。 (Example)
Necessary additives were added to the barium titanate powder and sufficiently wet-mixed and pulverized with a ball mill to obtain a dielectric material. An organic binder and a solvent were added to the dielectric material, and a dielectric green sheet was produced by a doctor blade method. The coating thickness of the dielectric green sheet was 0.8 μm, polyvinyl butyral (PVB) or the like was used as an organic binder, and ethanol, toluene acid or the like was added as a solvent. In addition, plasticizers were added. Next, a conductive paste for forming an internal electrode containing a powder of a main component metal of the internal electrode layer 12, a binder, a solvent, and other auxiliary agents as required was prepared. The organic binder and solvent for the internal electrode forming conductive paste were different from the dielectric green sheet. A conductive paste for forming internal electrodes was screen printed on the dielectric sheet. 250 sheets on which the internal electrode forming conductive paste was printed were stacked, and cover sheets were stacked on the top and bottom. Then, the ceramic laminated body was obtained by thermocompression bonding and cut into a predetermined shape.

得られたセラミック積層体をＮ２雰囲気中で脱バインダした後に、セラミック積層体の両端面から各側面にかけて、Ｎｉを主成分とする金属フィラー、共材、バインダ、溶剤およびＭｏ源を含む金属ペーストを塗布し、乾燥させた。Ｍｏ源として、ＭｏＯ３を用いた。実施例では、金属ペーストの固形分に対して０．１ｗｔ％のＭｏＯ３を添加した。その後、還元雰囲気中で１１００℃〜１３００℃で１０分〜２時間、金属ペーストをセラミック積層体と同時に焼成して焼結体を得た。 After removing the binder from the obtained ceramic laminate in an N 2 atmosphere, a metal paste containing a metal filler mainly composed of Ni, a co-material, a binder, a solvent, and a Mo source from both end faces to each side face of the ceramic laminate. Was applied and dried. MoO 3 was used as the Mo source. In the examples, 0.1 wt% of MoO 3 was added to the solid content of the metal paste. Thereafter, the metal paste was fired simultaneously with the ceramic laminate at 1100 ° C. to 1300 ° C. for 10 minutes to 2 hours in a reducing atmosphere to obtain a sintered body.

得られた焼結体の形状寸法は、長さ＝０．６ｍｍ、幅＝０．３ｍｍ、高さ０．３ｍｍであった。焼結体をＮ２雰囲気下８００℃の条件で再酸化処理を行った後、メッキ処理して下地層２１の表面にＣｕめっき層２２、Ｎｉめっき層２３およびＳｎめっき層２４を形成し、積層セラミックコンデンサ１００を得た。実施例に係るサンプルをそれぞれ１００個作成した。 The shape and size of the obtained sintered body were length = 0.6 mm, width = 0.3 mm, and height 0.3 mm. The sintered body was subjected to re-oxidation treatment at 800 ° C. under N 2 atmosphere, and then plated to form a Cu plating layer 22, a Ni plating layer 23, and a Sn plating layer 24 on the surface of the underlayer 21. A ceramic capacitor 100 was obtained. 100 samples of each example were prepared.

（比較例）
比較例では下地層２１用の金属ペーストにＭｏ源を添加しなかった。他は、実施例と同様の条件とした。比較例に係るサンプルをそれぞれ１００個作成した。 (Comparative example)
In the comparative example, the Mo source was not added to the metal paste for the base layer 21. The other conditions were the same as in the example. 100 samples according to comparative examples were prepared.

ＳＴＥＭを用いて下地層２１およびＣｕめっき層２２を観察した結果、実施例および比較例のいずれにおいても、下地層２１とＣｕめっき層２２との間に界面２６が生じていることが確認された。さらに、ＳＴＥＭ−ＥＤＳを用いて下地層２１およびＣｕめっき層２２におけるＭｏの分布を測定した結果、実施例ではＭｏを含む介在物２５が確認された。比較例では、介在物２５が確認されなかった。   As a result of observing the underlayer 21 and the Cu plating layer 22 using STEM, it was confirmed that an interface 26 was formed between the underlayer 21 and the Cu plating layer 22 in both the examples and the comparative examples. . Furthermore, as a result of measuring the distribution of Mo in the underlayer 21 and the Cu plating layer 22 using STEM-EDS, inclusions 25 containing Mo were confirmed in the examples. In the comparative example, the inclusion 25 was not confirmed.

実施例および比較例のそれぞれについて、温度＝８５℃、相対湿度８５％、１０Ｖの耐圧試験を１００ｈ時間行った。この場合に、６０秒間１００ＭΩ以下になるサンプルの発生率を調べた。表１は、その結果を示す。表１に示すように、比較例では、当該発生率が１８％以上と高くなった。これは、外部電極２０ａ，２０ｂを透過して内部電極層１２に水素が吸蔵され、当該水素によって誘電体層１１が還元されたからであると考えられる。これに対して、実施例では、当該発生率が大幅に低下した。これは、下地層２１のＣｕめっき層側表面にＭｏを含む介在物２５が形成されたことで外部電極２０ａ，２０ｂの水素透過が抑制され、内部電極層１２への水素吸蔵が抑制されたからであると考えられる。

Figure 2019212717
About each of an Example and a comparative example, the pressure | voltage resistant test of temperature = 85 degreeC, relative humidity 85%, and 10V was done for 100 hours. In this case, the occurrence rate of samples that were 100 MΩ or less for 60 seconds was examined. Table 1 shows the results. As shown in Table 1, in the comparative example, the incidence was as high as 18% or more. This is presumably because hydrogen was stored in the internal electrode layer 12 through the external electrodes 20a and 20b, and the dielectric layer 11 was reduced by the hydrogen. On the other hand, in the Example, the said incidence rate fell significantly. This is because the inclusion 25 containing Mo is formed on the surface of the base layer 21 on the Cu plating layer side, so that hydrogen permeation of the external electrodes 20a and 20b is suppressed, and hydrogen occlusion in the internal electrode layer 12 is suppressed. It is believed that there is.
Figure 2019212717

以上、本発明の実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

１０ 積層チップ
１１ 誘電体層
１２ 内部電極層
２０ａ，２０ｂ 外部電極
２１ 下地層
２２ Ｃｕめっき層
２３ Ｎｉめっき層
２４ Ｓｎめっき層
１００ 積層セラミックコンデンサ DESCRIPTION OF SYMBOLS 10 Multilayer chip 11 Dielectric layer 12 Internal electrode layer 20a, 20b External electrode 21 Underlayer 22 Cu plating layer 23 Ni plating layer 24 Sn plating layer 100 Multilayer ceramic capacitor

Claims (5)

セラミックを主成分とする誘電体層と、内部電極層と、が交互に積層され、積層された複数の前記内部電極層が交互に対向する２端面に露出するように形成され、略直方体形状を有する積層チップと、
前記２端面に形成された１対の外部電極と、を備え、
前記１対の外部電極は、下地層上にめっき層が形成された構造を有し、
前記下地層は、ＮｉおよびＣｕの少なくともいずれか一方を含む金属または合金を主成分とし、前記めっき層側の表面の少なくとも一部に、Ｍｏを含む介在物が備わることを特徴とする積層セラミックコンデンサ。 Dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and the plurality of laminated internal electrode layers are formed so as to be exposed at two opposite end faces, and have a substantially rectangular parallelepiped shape. A laminated chip having,
A pair of external electrodes formed on the two end faces,
The pair of external electrodes has a structure in which a plating layer is formed on a base layer,
The underlayer has a metal or alloy containing at least one of Ni and Cu as a main component, and an inclusion containing Mo is provided on at least a part of the surface on the plating layer side. . 前記めっき層は、Ｓｎめっき層を含むことを特徴とする請求項１記載の積層セラミックコンデンサ。   The multilayer ceramic capacitor according to claim 1, wherein the plating layer includes a Sn plating layer. 前記下地層の主成分金属は、Ｎｉであることを特徴とする請求項１または２に記載の積層セラミックコンデンサ。   The multilayer ceramic capacitor according to claim 1, wherein a main component metal of the underlayer is Ni. 前記内部電極層は、Ｎｉを主成分とすることを特徴とする請求項１〜３のいずれか一項に記載の積層セラミックコンデンサ。   The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layer contains Ni as a main component. 前記誘電体層の主成分セラミックは、ペロブスカイト構造を有することを特徴とする請求項１〜４のいずれか一項に記載の積層セラミックコンデンサ。   The multilayer ceramic capacitor according to claim 1, wherein the main component ceramic of the dielectric layer has a perovskite structure.
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