WO2024070428A1 - Ceramic electronic component and metho for producing ceramic electronic component - Google Patents

Ceramic electronic component and metho for producing ceramic electronic component Download PDF

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Publication number
WO2024070428A1
WO2024070428A1 PCT/JP2023/031319 JP2023031319W WO2024070428A1 WO 2024070428 A1 WO2024070428 A1 WO 2024070428A1 JP 2023031319 W JP2023031319 W JP 2023031319W WO 2024070428 A1 WO2024070428 A1 WO 2024070428A1
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internal electrode
electronic component
ceramic electronic
electrode layers
film portion
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PCT/JP2023/031319
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French (fr)
Japanese (ja)
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茶園広一
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太陽誘電株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • the present invention relates to ceramic electronic components and methods for manufacturing ceramic electronic components.
  • the present invention has been developed in consideration of the above problems, and aims to provide a ceramic electronic component and a manufacturing method thereof that can improve the continuity of the internal electrode layers.
  • the ceramic electronic component according to the present invention comprises a laminate in which multiple dielectric layers and multiple internal electrode layers are alternately stacked, and at least one of the internal electrode layers has multiple thin film sections with a thickness of 0.5 ⁇ m or less in the stacking direction, and a thick film section formed between two adjacent thin film sections and having a thickness in the stacking direction that is at least twice as thick as the thin film sections.
  • the thickness of the thin film portion in the lamination direction may be 0.3 ⁇ m or less.
  • the thickness of the multiple dielectric layers in the stacking direction may be 0.4 ⁇ m or less.
  • the thickness of the multiple dielectric layers in the stacking direction may be 0.3 ⁇ m or less.
  • the thick film portion may be formed by overlapping the ends of the two adjacent thin film portions in the stacking direction.
  • the thick film portion may include ends of the two adjacent thin film portions and a dielectric provided between the ends.
  • At least one of the internal electrode layers may have a plurality of the thick film portions at predetermined intervals in the extension direction.
  • the length of the thick film portion in the extension direction of at least one of the internal electrode layers may be greater than the thickness of the thin film portion in the stacking direction.
  • the multiple internal electrode layers are alternately exposed on two opposing end faces of the laminate, and in a cross section including the lamination direction and the direction in which the two end faces face each other, the thick film portion may appear as two overlapping layers.
  • the multiple internal electrode layers are alternately exposed on two opposing end faces of the laminate, and the laminate has end margins in which the internal electrode layers exposed on the same one of the two end faces face each other without an internal electrode layer exposed on a different end face, and capacitive sections in which the internal electrode layers exposed on different one of the two end faces face each other, and the number of the thick film sections per unit length in at least one of the internal electrode layers may be greater in the end margins than in the capacitive sections.
  • the multiple internal electrode layers may be alternately exposed on two opposing end faces of the laminate, and in a plan view of at least one of the internal electrode layers, the thick film portion may extend in a direction intersecting the direction in which the two end faces face each other.
  • At least one of the internal electrode layers may be composed of metal only.
  • the method for manufacturing ceramic electronic components according to the present invention is characterized in that a laminate in which multiple lamination units, on which internal electrode patterns are formed by a dry process, are stacked on a dielectric green sheet is fired, and in at least one of the internal electrode layers formed from the internal electrode patterns, multiple thin film sections with a thickness of 0.5 ⁇ m or less in the stacking direction and thick film sections formed between two adjacent thin film sections and having a thickness in the stacking direction that is at least twice as thick as the thin film sections are formed.
  • the present invention provides a ceramic electronic component and a manufacturing method thereof that can improve the continuity of the internal electrode layers.
  • FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor.
  • 2 is a cross-sectional view taken along line AA in FIG. 1.
  • 2 is a cross-sectional view taken along line BB in FIG. 1.
  • FIG. 4 is an enlarged cross-sectional view of the vicinity of an external electrode.
  • FIG. 13 is a diagram illustrating a continuity rate.
  • FIG. 2 is a cross-sectional view including the Z-axis direction.
  • FIG. 4 is a diagram illustrating a thick film portion.
  • FIG. 4 is a diagram illustrating a thick film portion.
  • FIG. 4 is a diagram illustrating a thick film portion.
  • 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor.
  • 4A and 4B are diagrams illustrating an internal electrode forming step.
  • FIG. 1 is a partially sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1.
  • FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1.
  • the multilayer ceramic capacitor 100 includes a laminate 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the laminate 10. Of the four faces of the laminate 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces.
  • the external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the laminate 10. However, the external electrodes 20a, 20b are spaced apart from each other.
  • the Z-axis direction is the stacking direction, and is the direction in which the internal electrode layers 12 face each other.
  • the X-axis direction is the length direction of the laminate 10, the direction in which the two end faces of the laminate 10 face each other, and the direction in which the external electrodes 20a and 20b face each other.
  • the Y-axis direction is the width direction of the internal electrode layers 12, and is the direction in which the two side faces other than the two end faces of the four side faces of the laminate 10 face each other.
  • the X-axis direction, Y-axis direction, and Z-axis direction are mutually perpendicular.
  • the laminate 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated.
  • the edges of each internal electrode layer 12 are alternately exposed to the end face of the laminate 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided.
  • each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b.
  • the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12.
  • the internal electrode layers 12 are arranged on both outermost layers in the lamination direction, and the outermost internal electrode layers 12 are covered by the cover layers 13.
  • the cover layers 13 are mainly composed of a ceramic material.
  • the cover layers 13 may have the same composition as the dielectric layers 11 or may have a different composition. Note that the configuration is not limited to those shown in Figures 1 to 3, as long as the internal electrode layer 12 is exposed on two different surfaces and is conductive to different external electrodes.
  • the size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.
  • the internal electrode layer 12 is mainly composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn), or alloys of these.
  • the main component of the internal electrode layer 12 may be precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these.
  • the internal electrode layer 12 is composed only of metal components, and does not contain ceramic particles as co-materials.
  • the dielectric layer 11 has a main phase of a ceramic material having a perovskite structure represented by the general formula ABO 3.
  • the perovskite structure includes ABO 3- ⁇ , which is not a stoichiometric composition.
  • the ceramic material can be selected from at least one of barium titanate (BaTiO 3 ), calcium zirconate (CaZrO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), magnesium titanate (MgTiO 3 ), and Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1) that forms a perovskite structure.
  • Ba1 -x- yCaxSryTi1 - zZrzO3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, barium calcium zirconate titanate, etc.
  • the dielectric layer 11 contains 90 at% or more of the main component ceramic.
  • the dielectric layer 11 may contain additives.
  • additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
  • Zr zirconium
  • Hf hafnium
  • Mg manganese
  • Mo molybden
  • the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, this region that generates capacitance is referred to as the capacitance section 14.
  • the capacitance section 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.
  • the region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is called the end margin 15.
  • the region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also an end margin 15.
  • the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween.
  • the end margin 15 is a region that does not generate electrical capacitance.
  • the side margin 16 is a region provided to cover the ends (ends in the Y-axis direction) of two side surfaces of the dielectric layer 11 and the internal electrode layer 12.
  • the side margin 16 is a region provided outside the capacitive section 14 in the Y-axis direction.
  • the side margin 16 is also a region that does not generate electrical capacitance.
  • FIG. 4 is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Hatching is omitted in FIG. 4.
  • a plating layer 22 may be provided on the outer surface of the external electrode 20a with the external electrode 20a as a base layer.
  • the external electrode 20a is mainly composed of Cu.
  • the external electrode 20a may also contain a glass component.
  • the plating layer 22 is mainly composed of a metal such as Cu, Ni, aluminum (Al), zinc (Zn), Sn, or an alloy of two or more of these.
  • the plating layer 22 may be a plating layer of a single metal component, or may be a plurality of plating layers of different metal components.
  • the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in this order from the external electrode 20a side.
  • the first plating layer 23 is, for example, a Cu plating layer.
  • the second plating layer 24 is, for example, a Ni plating layer.
  • the third plating layer 25 is, for example, a Sn plating layer.
  • FIG. 4 illustrates the external electrode 20a, the plating layer 22 may also be provided on the outer surface of the external electrode 20b.
  • the internal electrode layers 12 will be made thinner. However, making the internal electrode layers 12 thinner reduces the continuity of the internal electrode layers 12.
  • the continuity rate which is an index that represents the continuity of the internal electrode layers 12.
  • Fig. 5 is a diagram showing the continuity rate. As shown in Fig. 5, in an observation area of length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal parts are measured and added together, and the proportion of the metal parts, ⁇ Ln/L0, can be defined as the continuity rate of that layer. The closer this continuity rate is to 100%, the better the continuity of the internal electrode layer 12.
  • the multilayer ceramic capacitor 100 has a configuration that can improve the continuity of the internal electrode layers 12.
  • FIG. 6 is a cross-sectional view including the Z-axis direction.
  • FIG. 6 illustrates an XZ cross-section as an example.
  • the internal electrode layer 12 includes a thick film portion 30 that is partially thicker and a thin film portion 40 that is partially thinner.
  • the thick film portion 30 is formed between two adjacent thin film portions 40.
  • the thickness T2 of the thin film portion 40 in the stacking direction is 0.5 ⁇ m or less.
  • the thickness T1 of the thick film portion 30 in the stacking direction is more than twice as large as T2.
  • the provision of the thick film portion 30 suppresses discontinuity of the internal electrode layer 12. This improves the continuity of the internal electrode layer 12.
  • the entire internal electrode layer 12 is not made of a thick film portion, but the provision of the thick film portion 30 between two adjacent thin film portions 40 makes the internal electrode layer 12 thinner overall. This allows the number of layers of the internal electrode layer 12 to be increased without increasing the size.
  • the thick film portion 30 is formed thick. In this embodiment, it is preferable that the thick film portion 30 is 2.5 times or more thicker than the thin film portion 40, and it is more preferable that the thick film portion 30 is 3 times or more thicker.
  • the thickness T1 of the thick film portion 30 in the stacking direction is preferably 0.5 ⁇ m or more, more preferably 0.6 ⁇ m or more, and even more preferably 0.8 ⁇ m or more.
  • the thick film portion 30 is preferably no more than six times thicker than the thin film portion 40, more preferably no more than five times thicker, and even more preferably no more than four times thicker.
  • the thickness T1 of the thick film portion 30 in the stacking direction is preferably 3 ⁇ m or less, more preferably 2 ⁇ m or less, and even more preferably 1 ⁇ m or less.
  • the thickness T2 of the thin film portion 40 in the stacking direction is preferably 0.3 ⁇ m or less, and more preferably 0.25 ⁇ m or less.
  • the thickness of the dielectric layers 11 in the stacking direction is preferably 0.4 ⁇ m or less, more preferably 0.3 ⁇ m or less, and even more preferably 0.25 ⁇ m or less.
  • the thickness of one dielectric layer 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 points on each of 10 different dielectric layers 11, and deriving the average value of all the measurement points.
  • the direction in which each thick film portion 30 protrudes is on one side in the Z-axis direction.
  • the direction in which each thick film portion 30 protrudes is upward.
  • the thick film section 30 may be formed such that the ends of two adjacent thin film sections 40 overlap in the stacking direction. For example, as illustrated in FIG. 7, one end of two adjacent thin film sections 40 may overlap the other end in the stacking direction.
  • the two internal electrode layers appear to overlap in the thick film section 30 in the XZ cross section of FIG. 7.
  • the ends overlap in the stacking direction, so that the stresses generated at the ends escape in different directions, making it less likely for them to become the starting point of cracks due to external impact.
  • the ends of two adjacent thin film sections 40 may overlap, and the dielectric of the dielectric layer 11 may penetrate between these two ends. If the two ends completely overlap, no dielectric penetrates between the two ends. In this configuration, the dielectric layer 11 penetrates, which has the effect of increasing the contact area with the dielectric layer 11.
  • the multiple thick film portions 30 are provided at a predetermined interval in the extension direction of the internal electrode layer 12 (any direction in the XY plane, for example the X direction).
  • the interval between each of the multiple thick film portions 30 is approximately twice or more the thickness of the thin film portion 40. If it is less than this, it may be difficult to form the thin film portion 40.
  • the length of the thick film portion 30 is greater than the thickness of the thin film portion 40. Since the length of the discontinuous portion in the internal electrode layer 12 may be greater than the layer thickness, discontinuities can be suppressed by making the length of the thick film portion 30 greater than the thickness of the thin film portion 40.
  • the length of the thick film portion 30 can be defined as the length of a region that is at least twice as thick as the thin film portion 40.
  • the number of thick film portions 30 is greater in the end margins 15 than in the capacitance portions 14.
  • the number of thick film portions 30 is the number of thick film portions 30 per unit length in the extension direction of the internal electrode layer 12 (any direction in the XY plane, for example, the X direction). For example, it can be defined as the number of thick film portions 30 per 5 ⁇ m in the X direction.
  • the thick film portion 30 extends along a direction (e.g., the Y-axis direction) that intersects with the X-axis direction.
  • Figure 10 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.
  • a dielectric material for forming the dielectric layer 11 is prepared.
  • the A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles.
  • barium titanate is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant.
  • This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate.
  • additive compounds include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
  • a compound containing an additive compound is wet mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material.
  • the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.
  • a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed.
  • the obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried.
  • the substrate 51 is, for example, a polyethylene terephthalate (PET) film.
  • PET polyethylene terephthalate
  • a diagram illustrating the coating process is omitted.
  • the thickness of the dielectric green sheet 52 is adjusted to match the thickness of the dielectric layer 11 after firing. For example, the thickness of the dielectric green sheet 52 is set to 0.5 ⁇ m or less.
  • an internal electrode pattern 53 is formed on a dielectric green sheet 52.
  • Fig. 11(a) as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals.
  • the dielectric green sheet 52 on which the internal electrode patterns 53 are formed is taken as a lamination unit.
  • the thickness of the internal electrode pattern 53 is set to 0.5 ⁇ m or less.
  • the thickness of the internal electrode layer 12 obtained from the internal electrode pattern 53 is 0.5 ⁇ m or less.
  • a metal paste of the main component metal of the internal electrode layer 12 is used for the internal electrode pattern 53.
  • the film is formed by a dry process such as sputtering, vacuum deposition, or ion plating. Using these dry processes makes it easier to thin the internal electrode pattern 53, and further improves the flatness of the internal electrode pattern 53.
  • a large film may be formed on the end of the internal electrode pattern 53, or a film of an element that easily diffuses to the external electrode side, such as Ag (silver), As (arsenic), Au (gold), Co (cobalt), Cr (chromium), Cu (copper), Fe (iron), In (indium), Ir (iridium), Mg (magnesium), Mo (molybdenum), Os (osmium), Pd (palladium), Pt (platinum), Re (rhenium), Rh (rhodium), Ru (ruthenium), Se (selenium), Sn (tin), Te (tellurium), W (tungsten), Y (yttrium), or Zn (zinc), may be formed on the end of the internal electrode pattern 53.
  • an element that easily diffuses to the external electrode side such as Ag (silver), As (arsenic), Au (gold), Co (cobalt), Cr (chromium), Cu (copper), Fe (iron), In (indium), Ir
  • the lamination units are laminated as shown in Fig. 11(b).
  • a predetermined number of cover sheets 54 e.g., 2 to 10 layers
  • cover sheet 54 may be of the same composition as the dielectric green sheet 52, or may have a different additive.
  • the ceramic laminate thus obtained is subjected to a binder removal process in a N2 atmosphere at 250°C to 500°C, after which a metal paste that will become the underlayer of the external electrodes 20a, 20b is applied by a dipping method, and then fired for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10-12 MPa to 10-9 MPa and 1100°C to 1300°C.
  • a metal paste that will become the underlayer of the external electrodes 20a, 20b is applied by a dipping method, and then fired for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10-12 MPa to 10-9 MPa and 1100°C to 1300°C.
  • Each compound that constitutes the dielectric green sheet is sintered and grains grow.
  • a laminate 10 is obtained in which the dielectric layers 11 and the internal electrode layers 12 made of sintered bodies are alternately laminated, and a cover layer is formed as the outermost layer.
  • Reoxidation treatment process In order to return oxygen to the barium titanate, which is the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere, a heat treatment may be performed in a mixed gas of N2 and water vapor at about 1000°C or in the air at 500°C to 700°C, to the extent that the internal electrode layer 12 is not oxidized. This process is called a reoxidation treatment process.
  • the external electrodes 20a, 20b are used as an underlayer to perform a metal coating of copper, nickel, tin, or the like by plating.
  • the thickness of each of the Ni plating layer and the Sn plating layer is preferably 2 ⁇ m or more and 15 ⁇ m or less.
  • a sputtering process may be performed instead of the plating process.
  • the internal electrode pattern 53 formed by the dry process and the dielectric green sheet 52 are fired simultaneously.
  • stress is generated based on the difference between the shrinkage rate of the dielectric green sheet 52 and the shrinkage rate of the internal electrode pattern 53.
  • the shrinkage rate of the dielectric green sheet 52 is about 15% greater than the shrinkage rate of the internal electrode pattern 53.
  • the internal electrode pattern 53 is subjected to stress due to the shrinkage of the dielectric green sheet 52.
  • the internal electrode pattern 53 by printing a conductive paste containing metal powder and an organic binder by screen printing.
  • the metal powder is composed of multiple particles of 100 nm or more, the stress due to the shrinkage of the dielectric is dispersed for each particle, and no deformation occurs.
  • the internal electrode pattern 53 is formed by a dry process such as sputtering, the internal electrode pattern 53 is composed of fine particles of several nm to several tens of nm, and when fired, the particles are not arranged in layers and become closer to a plate shape. In this case, the stress due to the shrinkage of the dielectric is not dispersed and deformation occurs. This deformation forms the thick film portion 30.
  • the thick film portion 30, which is partially thick, and the thin film portion 40, which is partially thin, are formed in the internal electrode layer 12.
  • the thick film portion 30 is provided between two adjacent thin film portions 40, the internal electrode layer 12 is thinned as a whole.
  • the external electrodes 20a, 20b are fired simultaneously when the laminate 10 is fired, but this is not limited to the above.
  • a conductive paste may be baked onto both ends of the laminate 10 to form the external electrodes 20a, 20b.
  • the conductive paste may be applied to the surface of the laminate, or a dried film of the conductive paste may be transferred onto the laminate and then fired.
  • the conductive paste may be formed on the laminate by various methods and then fired to form the electrodes.
  • the sinterability of the end margin 15 increases and it shrinks, so that the number of thick film portions 30 per unit length can be made greater in the end margin 15 than in the capacitance portion 14.
  • a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited to this.
  • other multilayer ceramic electronic components such as varistors and thermistors may also be used.
  • the multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.
  • Example 1 Barium titanate was used as the main component ceramic of the ceramic raw material powder for forming the dielectric layer.
  • the average particle size of barium titanate was 0.1 ⁇ m.
  • ethanol, toluene, and IPA isopropyl alcohol
  • IPA isopropyl alcohol
  • the mixture was dispersed for a predetermined time using a bead mill.
  • Polyvinyl butyral (PVB) and a plasticizer were added as an organic binder to the obtained slurry and kneaded.
  • a dielectric green sheet was produced using a reverse coater.
  • An internal electrode pattern was formed on the dielectric green sheet by sputtering.
  • the mask was then removed using the lift-off method to obtain a dielectric green sheet with the internal electrode pattern formed.
  • the thick film portion can be measured based on a photograph of a cross section of a laminated body after firing taken with a scanning electron microscope (SEM).
  • SEM scanning electron microscope
  • the laminated ceramic capacitor Prior to observation with the SEM, the laminated ceramic capacitor can be cut, for example, by ion milling, to obtain a smooth cross section suitable for SEM observation.
  • Ten or more observations of one observation site (for example, one photograph magnified 30,000 times with an SEM) are made, and the portion where the internal electrodes overlap is the thick film portion, and the rest is the thin film portion.
  • the thicknesses of ten points in each of the thin film portion and thick film portion are measured, and the averages are taken as the respective thicknesses.
  • the thickness of the dielectric layer was also measured at ten points in the observation site, and the averages were taken as the thickness of the dielectric layer.
  • the thickness of the thin film portion was 0.5 ⁇ m.
  • the thickness of the thick film portion was 1.0 ⁇ m.
  • the thickness of the dielectric layer was 0.5 ⁇ m.
  • Example 2 Compared to Example 1, the sputtering time when forming the internal electrode pattern was shortened, and the amount of metal sprayed from the sputtering source was reduced. As a result, the thickness of the thin film portion was 0.3 ⁇ m. The thickness of the thick film portion was 0.6 ⁇ m. The other conditions were the same as those of Example 1.
  • the internal electrode pattern was formed by screen printing so that the thickness of the internal electrode layer after firing was 0.5 ⁇ m. In the comparative example, no thick film portion or thin film portion was confirmed in the internal electrode layer after firing.

Abstract

A ceramic electronic component including a multilayer structure comprising a plurality of dielectric layers alternating with a plurality of inner electrode layers, wherein at least any one of the inner electrode layers comprises a plurality of thin-film portions having a stacking-direction thickness of 0.5 μm or smaller and a thick-film portion formed between two adjacent thin-film portions and having a stacking-direction thickness which is at least twice that of the thin-film portion.　

Description

セラミック電子部品、およびセラミック電子部品の製造方法Ceramic electronic component and method for manufacturing ceramic electronic component
　本発明は、セラミック電子部品、およびセラミック電子部品の製造方法に関する。 The present invention relates to ceramic electronic components and methods for manufacturing ceramic electronic components.
　積層セラミックコンデンサなどのセラミック電子部品について、小型大容量化に伴い、誘電体層が薄層化および多積層化された構造が開示されている（例えば、特許文献１参照）。 For ceramic electronic components such as multilayer ceramic capacitors, structures have been disclosed in which the dielectric layers are made thinner and multi-layered in order to accommodate the trend toward smaller size and larger capacity (see, for example, Patent Document 1).
特開２０１６－１４３７０９号広報JP2016-143709Publication
　しかしながら、内部電極層を薄層化しようとすると、内部電極層の連続性が低下するおそれがある。 However, if an attempt is made to thin the internal electrode layer, there is a risk that the continuity of the internal electrode layer will decrease.
　本発明は、上記課題に鑑みなされたものであり、内部電極層の連続性を向上させることができるセラミック電子部品およびその製造方法を提供することを目的とする。 The present invention has been developed in consideration of the above problems, and aims to provide a ceramic electronic component and a manufacturing method thereof that can improve the continuity of the internal electrode layers.
　本発明に係るセラミック電子部品は、複数の誘電体層と複数の内部電極層とが交互に積層された積層体を備え、少なくともいずれかの内部電極層は、積層方向の厚さが０.５μｍ以下の複数の薄膜部と、隣り合う２つの薄膜部間に形成されかつ積層方向の厚さが前記薄膜部に比べて２倍以上厚い厚膜部と、を有することを特徴とする。 The ceramic electronic component according to the present invention comprises a laminate in which multiple dielectric layers and multiple internal electrode layers are alternately stacked, and at least one of the internal electrode layers has multiple thin film sections with a thickness of 0.5 μm or less in the stacking direction, and a thick film section formed between two adjacent thin film sections and having a thickness in the stacking direction that is at least twice as thick as the thin film sections.
　上記セラミック電子部品において、前記薄膜部の積層方向の厚さは、０．３μｍ以下であってもよい。 In the above ceramic electronic component, the thickness of the thin film portion in the lamination direction may be 0.3 μm or less.
　上記セラック電子部品において、前記複数の誘電体層の積層方向の厚さは、０．４μｍ以下であってもよい。 In the above shellac electronic component, the thickness of the multiple dielectric layers in the stacking direction may be 0.4 μm or less.
　上記セラミック電子部品において、前記複数の誘電体層の積層方向の厚さは、０．３μｍ以下であってもよい。 In the above ceramic electronic component, the thickness of the multiple dielectric layers in the stacking direction may be 0.3 μm or less.
　上記セラミック電子部品において、前記厚膜部は、前記隣り合う２つの薄膜部のそれぞれの端部が積層方向に重なって形成されていてもよい。 In the above ceramic electronic component, the thick film portion may be formed by overlapping the ends of the two adjacent thin film portions in the stacking direction.
　上記セラミック電子部品において、前記厚膜部は、前記隣り合う２つの薄膜部のそれぞれの端部と、前記それぞれの端部の間に設けられる誘電体と、を備えていてもよい。 In the above ceramic electronic component, the thick film portion may include ends of the two adjacent thin film portions and a dielectric provided between the ends.
　上記セラミック電子部品において、前記少なくともいずれかの内部電極層は、延在方向において、所定の間隔で複数の前記厚膜部を備えていてもよい。 In the ceramic electronic component, at least one of the internal electrode layers may have a plurality of the thick film portions at predetermined intervals in the extension direction.
　上記セラミック電子部品において、前記少なくともいずれかの内部電極層の延在方向における前記厚膜部の長さは、積層方向における前記薄膜部の厚みよりも大きくてもよい。 In the ceramic electronic component, the length of the thick film portion in the extension direction of at least one of the internal electrode layers may be greater than the thickness of the thin film portion in the stacking direction.
　上記セラミック電子部品において、前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、積層方向と前記２端面が対向する方向とを含む断面において、前記厚膜部は２層の層が重なって見えてもよい。 In the ceramic electronic component, the multiple internal electrode layers are alternately exposed on two opposing end faces of the laminate, and in a cross section including the lamination direction and the direction in which the two end faces face each other, the thick film portion may appear as two overlapping layers.
　上記セラミック電子部品において、前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、前記積層体は、前記２端面のうち同じ端面に対して露出する内部電極層同士が異なる端面に露出する内部電極層を介さずに対向するエンドマージンと、前記２端面のうち異なる端面に露出する内部電極層同士が対向する容量部と、を有し、前記少なくともいずれかの内部電極層における前記厚膜部の単位長さ辺りの個数は、前記容量部よりも前記エンドマージンの方が多くてもよい。 In the ceramic electronic component, the multiple internal electrode layers are alternately exposed on two opposing end faces of the laminate, and the laminate has end margins in which the internal electrode layers exposed on the same one of the two end faces face each other without an internal electrode layer exposed on a different end face, and capacitive sections in which the internal electrode layers exposed on different one of the two end faces face each other, and the number of the thick film sections per unit length in at least one of the internal electrode layers may be greater in the end margins than in the capacitive sections.
　上記セラミック電子部品において、前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、前記少なくともいずれかの内部電極層に対する平面視において、前記厚膜部は、前記２端面が対向する方向に対して交差する方向に延びていてもよい。 In the ceramic electronic component, the multiple internal electrode layers may be alternately exposed on two opposing end faces of the laminate, and in a plan view of at least one of the internal electrode layers, the thick film portion may extend in a direction intersecting the direction in which the two end faces face each other.
　上記セラミック電子部品において、前記少なくともいずれかの内部電極層は、金属のみで構成されていてもよい。 In the above ceramic electronic component, at least one of the internal electrode layers may be composed of metal only.
　本発明に係るセラミック電子部品の製造方法は、誘電体グリーンシート上に、ドライプロセスで内部電極パターンが成膜された積層単位が複数積層された積層体を焼成することで、前記内部電極パターンから形成される少なくともいずれかの内部電極層に、積層方向の厚さが０.５μｍ以下の複数の薄膜部と、隣り合う２つの薄膜部間に形成されかつ積層方向の厚さが前記薄膜部に比べて２倍以上厚い厚膜部と、を形成することを特徴とする。 The method for manufacturing ceramic electronic components according to the present invention is characterized in that a laminate in which multiple lamination units, on which internal electrode patterns are formed by a dry process, are stacked on a dielectric green sheet is fired, and in at least one of the internal electrode layers formed from the internal electrode patterns, multiple thin film sections with a thickness of 0.5 μm or less in the stacking direction and thick film sections formed between two adjacent thin film sections and having a thickness in the stacking direction that is at least twice as thick as the thin film sections are formed.
　本発明によれば、内部電極層の連続性を向上させることができるセラミック電子部品およびその製造方法を提供することができる。 The present invention provides a ceramic electronic component and a manufacturing method thereof that can improve the continuity of the internal electrode layers.
積層セラミックコンデンサの部分断面斜視図である。FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. 図１のＡ－Ａ線断面図である。2 is a cross-sectional view taken along line AA in FIG. 1. 図１のＢ－Ｂ線断面図である。2 is a cross-sectional view taken along line BB in FIG. 1. 外部電極付近の拡大断面図である。FIG. 4 is an enlarged cross-sectional view of the vicinity of an external electrode. 連続率を例示する図である。FIG. 13 is a diagram illustrating a continuity rate. Ｚ軸方向を含む断面図である。FIG. 2 is a cross-sectional view including the Z-axis direction. 厚膜部を例示する図である。FIG. 4 is a diagram illustrating a thick film portion. 厚膜部を例示する図である。FIG. 4 is a diagram illustrating a thick film portion. 厚膜部を例示する図である。FIG. 4 is a diagram illustrating a thick film portion. 積層セラミックコンデンサの製造方法のフローを例示する図である。1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. （ａ）および（ｂ）は内部電極形成工程を例示する図である。4A and 4B are diagrams illustrating an internal electrode forming step.
　以下、図面を参照しつつ、実施形態について説明する。 The following describes the embodiment with reference to the drawings.
（実施形態）
　図１は、実施形態に係る積層セラミックコンデンサ１００の部分断面斜視図である。図２は、図１のＡ－Ａ線断面図である。図３は、図１のＢ－Ｂ線断面図である。図１～図３で例示するように、積層セラミックコンデンサ１００は、略直方体形状を有する積層体１０と、積層体１０のいずれかの対向する２端面に設けられた外部電極２０ａ，２０ｂとを備える。なお、積層体１０の当該２端面以外の４面のうち、積層方向の上面および下面以外の２面を側面と称する。外部電極２０ａ，２０ｂは、積層体１０の積層方向の上面、下面および２側面に延在している。ただし、外部電極２０ａ，２０ｂは、互いに離間している。 (Embodiment)
FIG. 1 is a partially sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminate 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the laminate 10. Of the four faces of the laminate 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the laminate 10. However, the external electrodes 20a, 20b are spaced apart from each other.
　なお、図１～図３において、Ｚ軸方向は、積層方向であり、各内部電極層１２が対向する方向である。Ｘ軸方向は、積層体１０の長さ方向であって、積層体１０の２端面が対向する方向であり、外部電極２０ａと外部電極２０ｂとが対向する方向である。Ｙ軸方向は、内部電極層１２の幅方向であり、積層体１０の４側面のうち２端面以外の２側面が対向する方向である。Ｘ軸方向と、Ｙ軸方向と、Ｚ軸方向とは、互いに直交している。 In addition, in Figures 1 to 3, the Z-axis direction is the stacking direction, and is the direction in which the internal electrode layers 12 face each other. The X-axis direction is the length direction of the laminate 10, the direction in which the two end faces of the laminate 10 face each other, and the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction is the width direction of the internal electrode layers 12, and is the direction in which the two side faces other than the two end faces of the four side faces of the laminate 10 face each other. The X-axis direction, Y-axis direction, and Z-axis direction are mutually perpendicular.
　積層体１０は、誘電体として機能するセラミック材料を含む誘電体層１１と、内部電極層１２とが、交互に積層された構成を有する。各内部電極層１２の端縁は、積層体１０の外部電極２０ａが設けられた端面と、外部電極２０ｂが設けられた端面とに、交互に露出している。それにより、各内部電極層１２は、外部電極２０ａと外部電極２０ｂとに、交互に導通している。その結果、積層セラミックコンデンサ１００は、複数の誘電体層１１が内部電極層１２を介して積層された構成を有する。また、誘電体層１１と内部電極層１２との積層において、積層方向の両方の最外層には内部電極層１２が配置され、当該最外層の内部電極層１２は、カバー層１３によって覆われている。カバー層１３は、セラミック材料を主成分とする。例えば、カバー層１３は、誘電体層１１と組成が同じであっても、異なっていても構わない。なお、内部電極層１２が異なる２つの面に露出して、異なる外部電極に導通していれば、図１から図３の構成に限られない。 The laminate 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated. The edges of each internal electrode layer 12 are alternately exposed to the end face of the laminate 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the lamination of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on both outermost layers in the lamination direction, and the outermost internal electrode layers 12 are covered by the cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the cover layers 13 may have the same composition as the dielectric layers 11 or may have a different composition. Note that the configuration is not limited to those shown in Figures 1 to 3, as long as the internal electrode layer 12 is exposed on two different surfaces and is conductive to different external electrodes.
　積層セラミックコンデンサ１００のサイズは、例えば、長さ０．２５ｍｍ、幅０．１２５ｍｍ、高さ０．１２５ｍｍであり、または長さ０．４ｍｍ、幅０．２ｍｍ、高さ０．２ｍｍ、または長さ０．６ｍｍ、幅０．３ｍｍ、高さ０．３ｍｍであり、または長さ１．０ｍｍ、幅０．５ｍｍ、高さ０．５ｍｍであり、または長さ３．２ｍｍ、幅１．６ｍｍ、高さ１．６ｍｍであり、または長さ４．５ｍｍ、幅３．２ｍｍ、高さ２．５ｍｍであるが、これらのサイズに限定されるものではない。 The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.
　内部電極層１２は、ニッケル（Ｎｉ）、銅（Ｃｕ）、スズ（Ｓｎ）等の卑金属やこれらの合金を主成分とする。内部電極層１２の主成分として、白金（Ｐｔ）、パラジウム（Ｐｄ）、銀（Ａｇ）、金（Ａｕ）などの貴金属やこれらを含む合金を用いてもよい。内部電極層１２は、金属成分だけで構成されており、共材などのセラミック粒子を含んでいない。 The internal electrode layer 12 is mainly composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn), or alloys of these. The main component of the internal electrode layer 12 may be precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these. The internal electrode layer 12 is composed only of metal components, and does not contain ceramic particles as co-materials.
　誘電体層１１は、例えば、一般式ＡＢＯ３で表されるペロブスカイト構造を有するセラミック材料を主相とする。なお、当該ペロブスカイト構造は、化学量論組成から外れたＡＢＯ３－αを含む。例えば、当該セラミック材料として、チタン酸バリウム（ＢａＴｉＯ３），ジルコン酸カルシウム（ＣａＺｒＯ３），チタン酸カルシウム（ＣａＴｉＯ３），チタン酸ストロンチウム（ＳｒＴｉＯ３），チタン酸マグネシウム（ＭｇＴｉＯ３），ペロブスカイト構造を形成するＢａ１-ｘ－ｙＣａｘＳｒｙＴｉ１－ｚＺｒｚＯ３(０≦ｘ≦１，０≦ｙ≦１，０≦ｚ≦１)等のうち少なくとも１つから選択して用いることができる。Ｂａ１-ｘ－ｙＣａｘＳｒｙＴｉ１－ｚＺｒｚＯ３は、チタン酸バリウムストロンチウム、チタン酸バリウムカルシウム、ジルコン酸バリウム、チタン酸ジルコン酸バリウム、チタン酸ジルコン酸カルシウムおよびチタン酸ジルコン酸バリウムカルシウムなどである。例えば、誘電体層１１において、主成分セラミックは、９０ａｔ％以上含まれている。 The dielectric layer 11 has a main phase of a ceramic material having a perovskite structure represented by the general formula ABO 3. The perovskite structure includes ABO 3-α , which is not a stoichiometric composition. For example, the ceramic material can be selected from at least one of barium titanate (BaTiO 3 ), calcium zirconate (CaZrO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), magnesium titanate (MgTiO 3 ), and Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0≦x≦1, 0≦y≦1, 0≦z≦1) that forms a perovskite structure. Ba1 -x- yCaxSryTi1 - zZrzO3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, barium calcium zirconate titanate, etc. For example, the dielectric layer 11 contains 90 at% or more of the main component ceramic.
　誘電体層１１には、添加物が添加されていてもよい。誘電体層１１への添加物として、ジルコニウム（Ｚｒ）、ハフニウム（Ｈｆ）、マグネシウム(Ｍｇ）、マンガン(Ｍｎ）、モリブデン（Ｍｏ）、バナジウム(Ｖ）、クロム(Ｃｒ）、希土類元素(イットリウム(Ｙ）、サマリウム（Ｓｍ）、ユーロピウム（Ｅｕ）、ガドリニウム（Ｇｄ）、テルビウム（Ｔｂ）、ジスプロシウム（Ｄｙ）、ホルミウム（Ｈｏ）、エルビウム（Ｅｒ)、ツリウム（Ｔｍ）およびイッテルビウム（Ｙｂ）)の酸化物、または、コバルト(Ｃｏ）、ニッケル(Ｎｉ）、リチウム（Ｌｉ）、ホウ素（Ｂ）、ナトリウム（Ｎａ）、カリウム（Ｋ）もしくはケイ素（Ｓｉ）を含む酸化物、または、コバルト、ニッケル、リチウム、ホウ素、ナトリウム、カリウムもしくはケイ素を含むガラスが挙げられる。 The dielectric layer 11 may contain additives. Examples of additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
　図２で例示するように、外部電極２０ａに接続された内部電極層１２と外部電極２０ｂに接続された内部電極層１２とが対向する領域は、積層セラミックコンデンサ１００において電気容量を生じる領域である。そこで、当該電気容量を生じる領域を、容量部１４と称する。すなわち、容量部１４は、異なる外部電極に接続された隣接する内部電極層１２同士が対向する領域である。 As illustrated in FIG. 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, this region that generates capacitance is referred to as the capacitance section 14. In other words, the capacitance section 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.
　外部電極２０ａに接続された内部電極層１２同士が、外部電極２０ｂに接続された内部電極層１２を介さずに対向する領域を、エンドマージン１５と称する。また、外部電極２０ｂに接続された内部電極層１２同士が、外部電極２０ａに接続された内部電極層１２を介さずに対向する領域も、エンドマージン１５である。すなわち、エンドマージン１５は、同じ外部電極に接続された内部電極層１２が異なる外部電極に接続された内部電極層１２を介さずに対向する領域である。エンドマージン１５は、電気容量を生じない領域である。 The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also an end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin 15 is a region that does not generate electrical capacitance.
　図３で例示するように、積層体１０において、サイドマージン１６は、誘電体層１１および内部電極層１２の２側面側の端部（Ｙ軸方向の端部）を覆うように設けられた領域である。すなわち、サイドマージン１６は、Ｙ軸方向において、容量部１４の外側に設けられた領域である。サイドマージン１６も、電気容量を生じない領域である。 As illustrated in FIG. 3, in the laminate 10, the side margin 16 is a region provided to cover the ends (ends in the Y-axis direction) of two side surfaces of the dielectric layer 11 and the internal electrode layer 12. In other words, the side margin 16 is a region provided outside the capacitive section 14 in the Y-axis direction. The side margin 16 is also a region that does not generate electrical capacitance.
　図４は、外部電極２０ａ付近の拡大断面図である。図４では、ハッチを省略している。図４で例示するように、外部電極２０ａの外表面に、外部電極２０ａを下地層として、めっき層２２が設けられていてもよい。外部電極２０ａは、Ｃｕを主成分とする。外部電極２０ａは、ガラス成分を含んでいてもよい。めっき層２２は、Ｃｕ、Ｎｉ、アルミニウム（Ａｌ）、亜鉛（Ｚｎ）、Ｓｎなどの金属またはこれらの２以上の合金を主成分とする。めっき層２２は、単一金属成分のめっき層でもよく、互いに異なる金属成分の複数のめっき層でもよい。例えば、めっき層２２は、外部電極２０ａ側から順に、第１めっき層２３、第２めっき層２４および第３めっき層２５が形成された構造を有する。第１めっき層２３は、例えば、Ｃｕめっき層である。第２めっき層２４は、例えば、Ｎｉめっき層である。第３めっき層２５は、例えば、Ｓｎめっき層である。なお、図４では、外部電極２０ａについて例示しているが、外部電極２０ｂの外表面にも同様に、めっき層２２が設けられていてもよい。 FIG. 4 is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Hatching is omitted in FIG. 4. As illustrated in FIG. 4, a plating layer 22 may be provided on the outer surface of the external electrode 20a with the external electrode 20a as a base layer. The external electrode 20a is mainly composed of Cu. The external electrode 20a may also contain a glass component. The plating layer 22 is mainly composed of a metal such as Cu, Ni, aluminum (Al), zinc (Zn), Sn, or an alloy of two or more of these. The plating layer 22 may be a plating layer of a single metal component, or may be a plurality of plating layers of different metal components. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in this order from the external electrode 20a side. The first plating layer 23 is, for example, a Cu plating layer. The second plating layer 24 is, for example, a Ni plating layer. The third plating layer 25 is, for example, a Sn plating layer. Although FIG. 4 illustrates the external electrode 20a, the plating layer 22 may also be provided on the outer surface of the external electrode 20b.
　このような構造において、積層数を増やして小型大容量化しようとすると、内部電極層１２を薄層化することになる。しかしながら、内部電極層１２を薄層化しようとすると、内部電極層１２の連続性が低下する。ここで、内部電極層１２の連続性を表す指標である連続率について説明する。 In this type of structure, if an attempt is made to increase the number of layers to make the device smaller and with greater capacity, the internal electrode layers 12 will be made thinner. However, making the internal electrode layers 12 thinner reduces the continuity of the internal electrode layers 12. Here, we will explain the continuity rate, which is an index that represents the continuity of the internal electrode layers 12.
　図５は、連続率を表す図である。図５で例示するように、ある内部電極層１２における長さＬ０の観察領域において、その金属部分の長さＬ１，Ｌ２，・・・，Ｌｎを測定して合計し、金属部分の割合であるΣＬｎ／Ｌ０をその層の連続率と定義することができる。この連続率が１００％に近いほど、内部電極層１２の連続性が良好ということになる。 Fig. 5 is a diagram showing the continuity rate. As shown in Fig. 5, in an observation area of length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal parts are measured and added together, and the proportion of the metal parts, ΣLn/L0, can be defined as the continuity rate of that layer. The closer this continuity rate is to 100%, the better the continuity of the internal electrode layer 12.
　本実施形態に係る積層セラミックコンデンサ１００は、内部電極層１２の連続性を向上させることができる構成を有している。 The multilayer ceramic capacitor 100 according to this embodiment has a configuration that can improve the continuity of the internal electrode layers 12.
　図６は、Ｚ軸方向を含む断面図である。図６では、一例として、ＸＺ断面が例示されている。図６で例示するように、内部電極層１２は、部分的に厚くなっている厚膜部３０と、部分的に薄くなっている薄膜部４０とを備えている。厚膜部３０は、隣り合う２つの薄膜部４０の間に形成されている。薄膜部４０の積層方向における厚さＴ２は、０．５μｍ以下である。厚膜部３０の積層方向における厚さＴ１は、Ｔ２に比べて２倍以上となっている。 FIG. 6 is a cross-sectional view including the Z-axis direction. FIG. 6 illustrates an XZ cross-section as an example. As illustrated in FIG. 6, the internal electrode layer 12 includes a thick film portion 30 that is partially thicker and a thin film portion 40 that is partially thinner. The thick film portion 30 is formed between two adjacent thin film portions 40. The thickness T2 of the thin film portion 40 in the stacking direction is 0.5 μm or less. The thickness T1 of the thick film portion 30 in the stacking direction is more than twice as large as T2.
　この構成によれば、厚膜部３０が設けられることで、内部電極層１２の途切れが抑制される。それにより、内部電極層１２の連続性が向上する。なお、内部電極層１２の全体が厚膜部になっているのではなく、２つの隣り合う薄膜部４０の間に厚膜部３０が設けられていることで、内部電極層１２の全体としては薄層化されている。それにより、大型化させずに内部電極層１２の積層数を増やすことができる。 With this configuration, the provision of the thick film portion 30 suppresses discontinuity of the internal electrode layer 12. This improves the continuity of the internal electrode layer 12. Note that the entire internal electrode layer 12 is not made of a thick film portion, but the provision of the thick film portion 30 between two adjacent thin film portions 40 makes the internal electrode layer 12 thinner overall. This allows the number of layers of the internal electrode layer 12 to be increased without increasing the size.
　内部電極層１２の途切れを抑制する観点から、厚膜部３０は、厚く形成されていることが好ましい。本実施形態においては、厚膜部３０は、薄膜部４０に比べて、２．５倍以上の厚さを有していることが好ましく、３倍以上の厚さを有していることがより好ましい。 From the viewpoint of suppressing discontinuity of the internal electrode layer 12, it is preferable that the thick film portion 30 is formed thick. In this embodiment, it is preferable that the thick film portion 30 is 2.5 times or more thicker than the thin film portion 40, and it is more preferable that the thick film portion 30 is 3 times or more thicker.
　また、厚膜部３０の積層方向における厚さＴ１は、０．５μｍ以上であることが好ましく、０．６μｍ以上であることがより好ましく、０．８μｍ以上であることがさらに好ましい。 Furthermore, the thickness T1 of the thick film portion 30 in the stacking direction is preferably 0.5 μm or more, more preferably 0.6 μm or more, and even more preferably 0.8 μm or more.
　一方で、厚膜部３０が厚すぎると、誘電体層１１を介して上下に隣り合う内部電極層１２が互いに近づいて絶縁破壊電圧が低下するおそれがある。そこで、厚膜部３０の厚さに上限を設けることが好ましい。本実施形態においては、厚膜部３０は、薄膜部４０に比べて、６倍以下の厚さを有していることが好ましく、５倍以下の厚さを有していることがより好ましく、４倍以下の厚さを有していることがさらに好ましい。 On the other hand, if the thick film portion 30 is too thick, the internal electrode layers 12 adjacent to each other above and below via the dielectric layer 11 may approach each other, resulting in a decrease in the breakdown voltage. Therefore, it is preferable to set an upper limit on the thickness of the thick film portion 30. In this embodiment, the thick film portion 30 is preferably no more than six times thicker than the thin film portion 40, more preferably no more than five times thicker, and even more preferably no more than four times thicker.
　また、厚膜部３０の積層方向における厚さＴ１は、３μｍ以下であることが好ましく、２μｍ以下であることがより好ましく、１μｍ以下であることがさらに好ましい。 Furthermore, the thickness T1 of the thick film portion 30 in the stacking direction is preferably 3 μm or less, more preferably 2 μm or less, and even more preferably 1 μm or less.
　積層数を増やす観点から、薄膜部４０の積層方向の厚さに上限を設けることが好ましい。本実施形態においては、薄膜部４０の積層方向の厚さＴ２は、０．３μｍ以下であることが好ましく、０．２５μｍ以下であることがより好ましい。 From the viewpoint of increasing the number of layers, it is preferable to set an upper limit on the thickness of the thin film portion 40 in the stacking direction. In this embodiment, the thickness T2 of the thin film portion 40 in the stacking direction is preferably 0.3 μm or less, and more preferably 0.25 μm or less.
　積層数を増やす観点から、誘電体層１１の積層方向の厚さに上限を設けることが好ましい。本実施形態においては、誘電体層１１の積層方向の厚さは、０．４μｍ以下であることが好ましく、０．３μｍ以下であることがより好ましく、０．２５μｍ以下であることがさらに好ましい。誘電体層１１の１層の厚みは、積層セラミックコンデンサ１００の断面をＳＥＭ（走査型電子顕微鏡）で観察し、異なる１０層の誘電体層１１についてそれぞれ１０点ずつ厚みを測定し、全測定点の平均値を導出することによって測定することができる。 From the viewpoint of increasing the number of layers, it is preferable to set an upper limit on the thickness of the dielectric layers 11 in the stacking direction. In this embodiment, the thickness of the dielectric layers 11 in the stacking direction is preferably 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.25 μm or less. The thickness of one dielectric layer 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 points on each of 10 different dielectric layers 11, and deriving the average value of all the measurement points.
　例えば、１層の内部電極層１２において、各厚膜部３０が突出している方向は、Ｚ軸方向のいずれか一方側になっている。例えば、図６の例では、各厚膜部３０が突出する方向は、上向きになっている。複数の内部電極層１２に着目した場合には、各内部電極層１２において各厚膜部３０が突出している方向は、Ｚ軸方向のいずれか一方にそろっている。 For example, in one internal electrode layer 12, the direction in which each thick film portion 30 protrudes is on one side in the Z-axis direction. For example, in the example of FIG. 6, the direction in which each thick film portion 30 protrudes is upward. When attention is paid to multiple internal electrode layers 12, the direction in which each thick film portion 30 protrudes in each internal electrode layer 12 is aligned on one side in the Z-axis direction.
　厚膜部３０は、隣り合う２つの薄膜部４０のそれぞれの端部が積層方向に重なって形成されていてもよい。例えば、図７で例示するように、隣り合う２つの薄膜部４０の一方の端部が、他方の端部に対して、積層方向に重なり合っていてもよい。この構成では、図７のＸＺ断面において、厚膜部３０で２層の内部電極層が重なって見えるようになる。この構成では端部が積層方向に重なることにより、端部に発生する互いの応力が別の方向に逃げるため、外部からの衝撃に対してクラックの起点になりにくい。 The thick film section 30 may be formed such that the ends of two adjacent thin film sections 40 overlap in the stacking direction. For example, as illustrated in FIG. 7, one end of two adjacent thin film sections 40 may overlap the other end in the stacking direction. In this configuration, the two internal electrode layers appear to overlap in the thick film section 30 in the XZ cross section of FIG. 7. In this configuration, the ends overlap in the stacking direction, so that the stresses generated at the ends escape in different directions, making it less likely for them to become the starting point of cracks due to external impact.
　また、図７で例示するように、厚膜部３０において、隣り合う２つの薄膜部４０の端部同士が重なっており、これら２つの端部の間に誘電体層１１の誘電体が入り込んでいてもよい。当該２つの端部が完全に重なり合っていれば、当該２つの端部の間に誘電体は入り込んでいない。この構成では、誘電体層１１が入り込むことによって、誘電体層１１との間の接触面積を増やせるという効果が得られる。 Also, as illustrated in FIG. 7, in the thick film section 30, the ends of two adjacent thin film sections 40 may overlap, and the dielectric of the dielectric layer 11 may penetrate between these two ends. If the two ends completely overlap, no dielectric penetrates between the two ends. In this configuration, the dielectric layer 11 penetrates, which has the effect of increasing the contact area with the dielectric layer 11.
　また、内部電極層１２の延在方向（ＸＹ平面のいずれかの方向であって、一例としてＸ方向）において、複数の厚膜部３０が所定の間隔を空けて設けられていることが好ましい。この場合、複数の厚膜部３０が設けられることで、内部電極層１２の途切れをより抑制できるようになる。例えば、複数の厚膜部３０の各間隔は、薄膜部４０の厚さの２倍以上程度である。これ以下の場合、薄膜部４０の形成が難しくなる可能性がある。 Furthermore, it is preferable that the multiple thick film portions 30 are provided at a predetermined interval in the extension direction of the internal electrode layer 12 (any direction in the XY plane, for example the X direction). In this case, by providing multiple thick film portions 30, it becomes possible to further suppress discontinuities in the internal electrode layer 12. For example, the interval between each of the multiple thick film portions 30 is approximately twice or more the thickness of the thin film portion 40. If it is less than this, it may be difficult to form the thin film portion 40.
　また、内部電極層１２の延在方向（ＸＹ平面のいずれかの方向であって、一例としてＸ方向）において、厚膜部３０の長さは、薄膜部４０の厚みよりも大きくなっていることが好ましい。内部電極層１２における途切れ部の長さが層厚よりも大きくなることがあるため、厚膜部３０の長さが薄膜部４０の厚みよりも大きくなっていることで途切れを抑制できるようになる。なお、厚膜部３０の長さは、薄膜部４０の２倍以上の厚さになっている領域の長さと定義することができる。 Furthermore, in the extension direction of the internal electrode layer 12 (any direction in the XY plane, for example the X direction), it is preferable that the length of the thick film portion 30 is greater than the thickness of the thin film portion 40. Since the length of the discontinuous portion in the internal electrode layer 12 may be greater than the layer thickness, discontinuities can be suppressed by making the length of the thick film portion 30 greater than the thickness of the thin film portion 40. The length of the thick film portion 30 can be defined as the length of a region that is at least twice as thick as the thin film portion 40.
　また、図８で例示するように、特定の内部電極層１２に着目した場合に、厚膜部３０の個数は、容量部１４よりもエンドマージン１５の方が多いことが好ましい。例えば、内部電極層１２をスパッタリングなどのドライプロセスで形成する場合に端部の連続率が低くなる傾向にあるため、内部電極層１２をドライプロセスで形成する場合においても途切れを抑制して連続性を向上させることができる。ここで、厚膜部３０の個数とは、内部電極層１２の延在方向（ＸＹ平面のいずれかの方向であって、一例としてＸ方向）の単位長さあたりの厚膜部３０の個数である。例えば、Ｘ方向における５μｍあたりの厚膜部３０の個数などと定義することができる。 Furthermore, as illustrated in FIG. 8, when focusing on a specific internal electrode layer 12, it is preferable that the number of thick film portions 30 is greater in the end margins 15 than in the capacitance portions 14. For example, when the internal electrode layer 12 is formed by a dry process such as sputtering, the continuity rate of the end portion tends to be low. Therefore, even when the internal electrode layer 12 is formed by a dry process, discontinuities can be suppressed and continuity can be improved. Here, the number of thick film portions 30 is the number of thick film portions 30 per unit length in the extension direction of the internal electrode layer 12 (any direction in the XY plane, for example, the X direction). For example, it can be defined as the number of thick film portions 30 per 5 μm in the X direction.
　また、図９で例示するように、内部電極層１２に対する平面視において、厚膜部３０は、Ｘ軸方向に対して交差する方向（例えばＹ軸方向）に沿って延びている。 Also, as illustrated in FIG. 9, in a plan view of the internal electrode layer 12, the thick film portion 30 extends along a direction (e.g., the Y-axis direction) that intersects with the X-axis direction.
　続いて、積層セラミックコンデンサ１００の製造方法について説明する。図１０は、積層セラミックコンデンサ１００の製造方法のフローを例示する図である。 Next, we will explain the manufacturing method of the multilayer ceramic capacitor 100. Figure 10 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.
　（原料粉末作製工程）
　まず、誘電体層１１を形成するための誘電体材料を用意する。誘電体層１１に含まれるＡサイト元素およびＢサイト元素は、通常はＡＢＯ３の粒子の焼結体の形で誘電体層１１に含まれる。例えば、チタン酸バリウムは、ペロブスカイト構造を有する正方晶化合物であって、高い誘電率を示す。このチタン酸バリウムは、一般的に、二酸化チタンなどのチタン原料と炭酸バリウムなどのバリウム原料とを反応させてチタン酸バリウムを合成することで得ることができる。誘電体層１１の主成分セラミックの合成方法としては、従来種々の方法が知られており、例えば固相法、ゾル－ゲル法、水熱法等が知られている。本実施形態においては、これらのいずれも採用することができる。 (Raw material powder preparation process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, barium titanate is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.
　得られたセラミック粉末に、目的に応じて所定の添加化合物を添加する。添加化合物としては、ジルコニウム、ハフニウム、マグネシウム、マンガン、モリブデン、バナジウム、クロム、希土類元素(イットリウム、サマリウム、ユーロピウム、ガドリニウム、テルビウム、ジスプロシウム、ホルミウム、エルビウム、ツリウムおよびイッテルビウム)の酸化物、または、コバルト、ニッケル、リチウム、ホウ素、ナトリウム、カリウムもしくはケイ素を含む酸化物、または、コバルト、ニッケル、リチウム、ホウ素、ナトリウム、カリウムもしくはケイ素を含むガラスが挙げられる。 　A specific additive compound is added to the obtained ceramic powder according to the purpose. Examples of additive compounds include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
　例えば、セラミック原料粉末に添加化合物を含む化合物を湿式混合し、乾燥および粉砕してセラミック材料を調製する。例えば、上記のようにして得られたセラミック材料について、必要に応じて粉砕処理して粒径を調節し、あるいは分級処理と組み合わせることで粒径を整えてもよい。以上の工程により、誘電体材料が得られる。 For example, a compound containing an additive compound is wet mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.
（塗工工程）
　次に、得られた原料粉末に、ポリビニルブチラール（ＰＶＢ）樹脂等のバインダと、エタノール、トルエン等の有機溶剤と、可塑剤とを加えて湿式混合する。得られたスラリを使用して、例えばダイコータ法やドクターブレード法により、基材５１上に誘電体グリーンシート５２を塗工して乾燥させる。基材５１は、例えば、ポリエチレンテレフタレート（ＰＥＴ）フィルムである。塗工工程を例示する図は省略した。誘電体グリーンシート５２の厚みは、焼成後の誘電体層１１の厚みに合わせて調整する。例えば、誘電体グリーンシート５２の厚みを、０．５μｍ以下とする。 (Coating process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a polyethylene terephthalate (PET) film. A diagram illustrating the coating process is omitted. The thickness of the dielectric green sheet 52 is adjusted to match the thickness of the dielectric layer 11 after firing. For example, the thickness of the dielectric green sheet 52 is set to 0.5 μm or less.
（内部電極形成工程）
　次に、図１１（ａ）で例示するように、誘電体グリーンシート５２上に、内部電極パターン５３を成膜する。図１１（ａ）では、一例として、誘電体グリーンシート５２上に４層の内部電極パターン５３が所定の間隔を空けて成膜されている。内部電極パターン５３が成膜された誘電体グリーンシート５２を、積層単位とする。例えば、内部電極パターン５３の厚みを、０．５μｍ以下とする。それにより、内部電極パターン５３から得られる内部電極層１２の厚みが０．５μｍ以下となる。 (Internal electrode formation process)
Next, as illustrated in Fig. 11(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In Fig. 11(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is taken as a lamination unit. For example, the thickness of the internal electrode pattern 53 is set to 0.5 µm or less. As a result, the thickness of the internal electrode layer 12 obtained from the internal electrode pattern 53 is 0.5 µm or less.
　内部電極パターン５３には、内部電極層１２の主成分金属の金属ペーストを用いる。成膜の手法は、スパッタリング法、真空蒸着法、イオンプレーティング法などのドライプロセスである。これらのドライプロセスを用いることで、内部電極パターン５３の薄層化が容易となり、さらに内部電極パターン５３の平坦性が向上する。なお、厚膜部３０が形成されやすいように内部電極パターン５３の端部を大きく成膜したり、内部電極パターン５３の端部に、Ａｇ（銀）、Ａｓ（砒素）、Ａｕ（金）、Ｃｏ（コバルト）、Ｃｒ（クロム）、Ｃｕ（銅）、Ｆｅ（鉄）、Ｉｎ（インジウム）、Ｉｒ（イリジウム）、Ｍｇ（マグネシウム）、Ｍｏ（モリブデン）、Ｏｓ（オスミウム）、Ｐｄ（パラジウム）、Ｐｔ（白金）、Ｒｅ（レニウム）、Ｒｈ（ロジウム）、Ｒｕ（ルテニウム）、Ｓｅ（セレン）、Ｓｎ（スズ）、Ｔｅ（テルル）、Ｗ（タングステン）、Ｙ（イットリウム）、Ｚｎ（亜鉛）など、外部電極側に拡散しやすい元素の成膜を追加してもよい。 For the internal electrode pattern 53, a metal paste of the main component metal of the internal electrode layer 12 is used. The film is formed by a dry process such as sputtering, vacuum deposition, or ion plating. Using these dry processes makes it easier to thin the internal electrode pattern 53, and further improves the flatness of the internal electrode pattern 53. In addition, to make it easier to form the thick film portion 30, a large film may be formed on the end of the internal electrode pattern 53, or a film of an element that easily diffuses to the external electrode side, such as Ag (silver), As (arsenic), Au (gold), Co (cobalt), Cr (chromium), Cu (copper), Fe (iron), In (indium), Ir (iridium), Mg (magnesium), Mo (molybdenum), Os (osmium), Pd (palladium), Pt (platinum), Re (rhenium), Rh (rhodium), Ru (ruthenium), Se (selenium), Sn (tin), Te (tellurium), W (tungsten), Y (yttrium), or Zn (zinc), may be formed on the end of the internal electrode pattern 53.
（圧着工程）
　次に、誘電体グリーンシート５２を基材５１から剥がしつつ、図１１（ｂ）で例示するように、積層単位を積層する。次に、積層単位が積層されることで得られた積層体の上下にカバーシート５４を所定数（例えば２～１０層）だけ積層して熱圧着させ、所定チップ寸法にカットする。図１１（ｂ）の例では、点線に沿ってカットする。カバーシート５４は、誘電体グリーンシート５２と同じ成分であってもよく、添加物が異なっていてもよい。 (Compression process)
Next, while peeling the dielectric green sheet 52 from the substrate 51, the lamination units are laminated as shown in Fig. 11(b). Next, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are laminated on the top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and cut to a predetermined chip size. In the example of Fig. 11(b), cutting is performed along the dotted lines. The cover sheet 54 may be of the same composition as the dielectric green sheet 52, or may have a different additive.
（焼成工程）
　このようにして得られたセラミック積層体を、２５０℃～５００℃のＮ２雰囲気で脱バインダ処理した後に外部電極２０ａ，２０ｂの下地層となる金属ペーストをディップ法で塗布し、酸素分圧が１０－１２ＭＰａ～１０－９ＭＰａ、１１００℃～１３００℃の還元雰囲気で、１０分～２時間の焼成を行なう。誘電体グリーンシートを構成する各化合物が焼結して粒成長する。このようにして、焼結体からなる誘電体層１１と内部電極層１２とが交互に積層され、最外層として形成されるカバー層とを有する積層体１０が得られる。 (Firing process)
The ceramic laminate thus obtained is subjected to a binder removal process in a N2 atmosphere at 250°C to 500°C, after which a metal paste that will become the underlayer of the external electrodes 20a, 20b is applied by a dipping method, and then fired for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10-12 MPa to 10-9 MPa and 1100°C to 1300°C. Each compound that constitutes the dielectric green sheet is sintered and grains grow. In this way, a laminate 10 is obtained in which the dielectric layers 11 and the internal electrode layers 12 made of sintered bodies are alternately laminated, and a cover layer is formed as the outermost layer.
（再酸化処理工程）
　還元雰囲気で焼成された誘電体層１１の部分的に還元された主相であるチタン酸バリウムに酸素を戻すために、内部電極層１２を酸化させない程度に、約１０００℃でＮ２と水蒸気の混合ガス中、もしくは５００℃～７００℃の大気中での熱処理が行われることがある。この工程は、再酸化処理工程とよばれる。 (Reoxidation treatment process)
In order to return oxygen to the barium titanate, which is the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere, a heat treatment may be performed in a mixed gas of N2 and water vapor at about 1000°C or in the air at 500°C to 700°C, to the extent that the internal electrode layer 12 is not oxidized. This process is called a reoxidation treatment process.
（めっき処理工程）
　その後、外部電極２０ａ，２０ｂを下地層として用いて、めっき処理により、銅、ニッケル、スズ等の金属コーティングを行う。Ｎｉめっき層とＳｎめっき層との２層構造とする場合、Ｎｉめっき層とＳｎめっき層それぞれの厚みは、２μｍ以上１５μｍ以下であることが好ましい。めっき処理の代わりに、スパッタリング処理を行なってもよい。以上の工程により、積層セラミックコンデンサ１００が完成する。 (Plating process)
Thereafter, the external electrodes 20a, 20b are used as an underlayer to perform a metal coating of copper, nickel, tin, or the like by plating. When a two-layer structure of a Ni plating layer and a Sn plating layer is used, the thickness of each of the Ni plating layer and the Sn plating layer is preferably 2 μm or more and 15 μm or less. A sputtering process may be performed instead of the plating process. Through the above steps, the multilayer ceramic capacitor 100 is completed.
　本実施形態に係る製造方法によれば、ドライプロセスで成膜した内部電極パターン５３と、誘電体グリーンシート５２とを同時に焼成することになる。焼成の際に、誘電体グリーンシート５２の収縮率と内部電極パターン５３の収縮率との差異に基づく応力が発生する。例えば、誘電体グリーンシート５２の収縮率は、内部電極パターン５３の収縮率より１５％程度大きくなる。この場合、内部電極パターン５３は、誘電体グリーンシート５２の収縮により応力を受ける。 According to the manufacturing method of this embodiment, the internal electrode pattern 53 formed by the dry process and the dielectric green sheet 52 are fired simultaneously. During firing, stress is generated based on the difference between the shrinkage rate of the dielectric green sheet 52 and the shrinkage rate of the internal electrode pattern 53. For example, the shrinkage rate of the dielectric green sheet 52 is about 15% greater than the shrinkage rate of the internal electrode pattern 53. In this case, the internal electrode pattern 53 is subjected to stress due to the shrinkage of the dielectric green sheet 52.
　金属粉末と有機バインダとを含む導電ペーストをスクリーン印刷によって印刷することで内部電極パターン５３を成膜することが考えられる。しかしながら、この場合には、金属粉体が１００ｎｍ以上の複数の粒子で構成されるため、誘電体の収縮による応力が粒子毎に分散され、変形が生じない。しかしながら、内部電極パターン５３をスパッタリング等のドライプロセスで形成する場合、内部電極パターン５３は数ｎｍから数十ｎｍの微細粒子で構成され、焼成すると粒子が層上に並ばず、板状に近くなる。この場合、誘電体の収縮による応力が分散されず、変形してしまう。この変形が、厚膜部３０を形成する。したがって、内部電極層１２に、部分的に厚くなっている厚膜部３０と、部分的に薄くなっている薄膜部４０とが形成される。それにより、内部電極層１２の途切れが抑制され、内部電極層１２の連続性が向上する。一方で、２つの隣り合う薄膜部４０の間に厚膜部３０が設けられるようになるため、内部電極層１２の全体としては薄層化される。 It is conceivable to form the internal electrode pattern 53 by printing a conductive paste containing metal powder and an organic binder by screen printing. However, in this case, since the metal powder is composed of multiple particles of 100 nm or more, the stress due to the shrinkage of the dielectric is dispersed for each particle, and no deformation occurs. However, when the internal electrode pattern 53 is formed by a dry process such as sputtering, the internal electrode pattern 53 is composed of fine particles of several nm to several tens of nm, and when fired, the particles are not arranged in layers and become closer to a plate shape. In this case, the stress due to the shrinkage of the dielectric is not dispersed and deformation occurs. This deformation forms the thick film portion 30. Therefore, the thick film portion 30, which is partially thick, and the thin film portion 40, which is partially thin, are formed in the internal electrode layer 12. As a result, discontinuities in the internal electrode layer 12 are suppressed, and the continuity of the internal electrode layer 12 is improved. On the other hand, since the thick film portion 30 is provided between two adjacent thin film portions 40, the internal electrode layer 12 is thinned as a whole.
　なお、上記の例では積層体１０を焼成する際に外部電極２０ａ，２０ｂを同時に焼成しているが、それに限られない。例えば、積層体１０を焼成した後に、積層体１０の両端部に導電ペーストを焼き付けて外部電極２０ａ，２０ｂを形成してもよい。また、導電性ペーストを積層体の表面に塗布するか、または導電性ペーストを乾燥させた乾燥膜を積層体上に転写した後に、焼成してもよい。その他、様々な方法により導電ペーストを積層体上に形成した後、これを焼成して形成することができる。 In the above example, the external electrodes 20a, 20b are fired simultaneously when the laminate 10 is fired, but this is not limited to the above. For example, after firing the laminate 10, a conductive paste may be baked onto both ends of the laminate 10 to form the external electrodes 20a, 20b. Alternatively, the conductive paste may be applied to the surface of the laminate, or a dried film of the conductive paste may be transferred onto the laminate and then fired. In addition, the conductive paste may be formed on the laminate by various methods and then fired to form the electrodes.
　なお、誘電体グリーンシート５１において、Ｓｉ（ケイ素）およびＢ（ホウ素）の合計濃度と、容量部１４に相当する領域と比較してエンドマージン１５に相当する領域において高くしておくことにより、エンドマージン１５の焼結性が高くなって収縮するため、単位長さあたりにおいて、厚膜部３０の個数を、容量部１４よりもエンドマージン１５の方において多くすることができる。 In addition, by making the total concentration of Si (silicon) and B (boron) higher in the region corresponding to the end margin 15 in the dielectric green sheet 51 compared to the region corresponding to the capacitance portion 14, the sinterability of the end margin 15 increases and it shrinks, so that the number of thick film portions 30 per unit length can be made greater in the end margin 15 than in the capacitance portion 14.
　なお、上記各実施形態においては、積層セラミック電子部品の一例として積層セラミックコンデンサについて説明したが、それに限られない。例えば、バリスタやサーミスタなどの、他の積層セラミック電子部品を用いてもよい。 In the above embodiments, a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited to this. For example, other multilayer ceramic electronic components such as varistors and thermistors may also be used.
　以下、実施形態に係る積層セラミックコンデンサを作製し、特性について調べた。 The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.
（実施例１）
　誘電体層を形成するためのセラミック原料粉末の主成分セラミックとして、チタン酸バリウムを用いた。チタン酸バリウムの平均粒子径は、０．１μｍであった。次に、エタノール、トルエン、ＩＰＡ（イソプロピルアルコール）が３：２：１となるように混合し、添加物が配合されたチタン酸バリウムを得た。その後、ビーズミルを使用して所定時間分散した。得られたスラリに、有機バインダとしてポリビニルブチラール（ＰＶＢ）および可塑剤を添加し混錬した。その後、リバースコータを用いて、誘電体グリーンシートを作成した。 Example 1
Barium titanate was used as the main component ceramic of the ceramic raw material powder for forming the dielectric layer. The average particle size of barium titanate was 0.1 μm. Next, ethanol, toluene, and IPA (isopropyl alcohol) were mixed in a ratio of 3:2:1 to obtain barium titanate containing additives. Then, the mixture was dispersed for a predetermined time using a bead mill. Polyvinyl butyral (PVB) and a plasticizer were added as an organic binder to the obtained slurry and kneaded. Then, a dielectric green sheet was produced using a reverse coater.
　誘電体グリーンシート上に、スパッタリングで内部電極パターンを形成した。その後、リフトオフ法を用いてマスクを除去し、内部電極パターンが形成された誘電体グリーンシートを得た。 An internal electrode pattern was formed on the dielectric green sheet by sputtering. The mask was then removed using the lift-off method to obtain a dielectric green sheet with the internal electrode pattern formed.
　内部電極パターンが形成された誘電体グリーンシートを２００枚重ね、その上下にカバーシートをそれぞれ積層した。その後、熱圧着により、焼成前の積層体を得て、所定の形状に切断した。その後、Ｎ２雰囲気中で脱バインダした後に焼成して焼結体を得た。焼成温度は、１２２０℃とした。金属導電ペースト中の金属成分が酸化しないように、還元雰囲気にて焼成を行った。その後、焼成後の積層体の２端面に外部電極を形成し、１００５タイプ（長さ１．０ｍｍ、幅０．５ｍｍ、高さ０．５ｍｍ）の積層セラミックコンデンサを得た。焼成後の内部電極層１２において、厚膜部と薄膜部とが確認された。 200 dielectric green sheets on which the internal electrode patterns were formed were stacked, and cover sheets were laminated on the top and bottom of each. Then, a pre-fired laminate was obtained by thermocompression bonding, and cut into a predetermined shape. Then, the laminate was debindered in a N2 atmosphere and fired to obtain a sintered body. The firing temperature was 1220°C. Firing was performed in a reducing atmosphere so that the metal components in the metal conductive paste would not oxidize. Then, external electrodes were formed on two end faces of the fired laminate, and a 1005 type (length 1.0 mm, width 0.5 mm, height 0.5 mm) multilayer ceramic capacitor was obtained. In the internal electrode layer 12 after firing, a thick film portion and a thin film portion were confirmed.
　例えば、厚膜部は、走査型電子顕微鏡（ＳＥＭ）で焼成後の積層体の一部断面を撮影し、その写真に基づいて測定することができる。ＳＥＭで観察するのに先立ち、積層セラミックコンデンサを例えばイオンミリング法により切削することで、ＳＥＭの観察に適した平滑断面を得ることができる。一ヶ所の観察部位（例えばＳＥＭで３００００倍に拡大したときの写真１枚）を１０以上観察し、内部電極が重なっている部分を厚膜部とし、その他を薄膜部とする。その観察部位で、薄膜部と、厚膜部との領域それぞれで、１０か所の厚さを測定し、その平均をそれぞれの厚さとした。誘電体層の厚さも、観察部位中、１０か所の厚さを測定し、その平均を誘電体層の厚さとした。薄膜部の厚みは、０．５μｍであった。厚膜部の厚みは、１．０μｍであった。誘電体層の厚みは、０．５μｍであった。 For example, the thick film portion can be measured based on a photograph of a cross section of a laminated body after firing taken with a scanning electron microscope (SEM). Prior to observation with the SEM, the laminated ceramic capacitor can be cut, for example, by ion milling, to obtain a smooth cross section suitable for SEM observation. Ten or more observations of one observation site (for example, one photograph magnified 30,000 times with an SEM) are made, and the portion where the internal electrodes overlap is the thick film portion, and the rest is the thin film portion. In the observation site, the thicknesses of ten points in each of the thin film portion and thick film portion are measured, and the averages are taken as the respective thicknesses. The thickness of the dielectric layer was also measured at ten points in the observation site, and the averages were taken as the thickness of the dielectric layer. The thickness of the thin film portion was 0.5 μm. The thickness of the thick film portion was 1.0 μm. The thickness of the dielectric layer was 0.5 μm.
（実施例２）
　実施例１と比較して、内部電極パターンを成膜する際のスパッタ時間を短縮し、スパッタ源からの金属の噴射量を抑えた。これにより、薄膜部の厚みは、０．３μｍであった。厚膜部の厚みは、０．６μｍであった。その他の条件は、実施例１と同じとした。 Example 2
Compared to Example 1, the sputtering time when forming the internal electrode pattern was shortened, and the amount of metal sprayed from the sputtering source was reduced. As a result, the thickness of the thin film portion was 0.3 μm. The thickness of the thick film portion was 0.6 μm. The other conditions were the same as those of Example 1.
（比較例）
　比較例では、焼成後の内部電極層の厚さが０．５μｍとなるように、内部電極パターンをスクリーン印刷で形成した。比較例では、焼成後の内部電極層において、厚膜部および薄膜部が確認されなかった。 Comparative Example
In the comparative example, the internal electrode pattern was formed by screen printing so that the thickness of the internal electrode layer after firing was 0.5 μm. In the comparative example, no thick film portion or thin film portion was confirmed in the internal electrode layer after firing.
（連続率の測定）
　焼成後の内部電極層の連続率を測定した。ＸＺ断面のＳＥＭ画像において、視野を５０μｍ×５０μｍとし、図５の手法で測定した。結果を表１に示す。表１に示すように、実施例１，２の連続率は比較例の連続率よりも高くなった。これは、内部電極層に厚膜部を形成したことで、内部電極層の途切れが抑制されたからであると考えられる。
Figure JPOXMLDOC01-appb-T000001
 (Measurement of continuity rate)
The continuity ratio of the internal electrode layer after firing was measured. In the SEM image of the XZ cross section, the field of view was set to 50 μm × 50 μm, and the measurement was performed using the method in FIG. 5. The results are shown in Table 1. As shown in Table 1, the continuity ratios of Examples 1 and 2 were higher than that of the comparative example. This is thought to be because the formation of the thick film portion in the internal electrode layer suppressed discontinuity of the internal electrode layer.
Figure JPOXMLDOC01-appb-T000001
　以上、本発明の実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。 　Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as described in the claims.
　１０　積層体
　１１　誘電体層
　１２　内部電極層
　１３　カバー層
　１４　容量部
　１５　エンドマージン
　１６　サイドマージン
　２０ａ，２０ｂ　外部電極
　３０　厚膜部
　４０　薄膜部
　５１　基材
　５２　誘電体グリーンシート
　５３　内部電極パターン
　５４　カバーシート
　１００　積層セラミックコンデンサ
　 REFERENCE SIGNS LIST 10 laminate 11 dielectric layer 12 internal electrode layer 13 cover layer 14 capacitance portion 15 end margin 16 side margin 20a, 20b external electrode 30 thick film portion 40 thin film portion 51 substrate 52 dielectric green sheet 53 internal electrode pattern 54 cover sheet 100 multilayer ceramic capacitor

Claims (13)

  1. 　複数の誘電体層と複数の内部電極層とが交互に積層された積層体を備え、
    　少なくともいずれかの内部電極層は、積層方向の厚さが０.５μｍ以下の複数の薄膜部と、隣り合う２つの薄膜部間に形成されかつ積層方向の厚さが前記薄膜部に比べて２倍以上厚い厚膜部と、を有することを特徴とするセラミック電子部品。     A laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated,
    A ceramic electronic component, characterized in that at least any one of the internal electrode layers has a plurality of thin film portions having a thickness of 0.5 μm or less in the stacking direction, and a thick film portion formed between two adjacent thin film portions and having a thickness in the stacking direction that is at least twice as thick as the thin film portions.
  2. 　前記薄膜部の積層方向の厚さは、０．３μｍ以下であることを特徴とする請求項１に記載のセラミック電子部品。 The ceramic electronic component according to claim 1, characterized in that the thickness of the thin film portion in the lamination direction is 0.3 μm or less.
  3. 　前記複数の誘電体層の積層方向の厚さは、０．４μｍ以下であることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that the thickness of the multiple dielectric layers in the stacking direction is 0.4 μm or less.
  4. 　前記複数の誘電体層の積層方向の厚さは、０．３μｍ以下であることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that the thickness of the plurality of dielectric layers in the stacking direction is 0.3 μm or less.
  5. 　前記厚膜部は、前記隣り合う２つの薄膜部のそれぞれの端部が積層方向に重なって形成されていることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that the thick film portion is formed by overlapping the respective ends of the two adjacent thin film portions in the stacking direction.
  6. 　前記厚膜部は、前記隣り合う２つの薄膜部のそれぞれの端部と、前記それぞれの端部の間に設けられる誘電体と、を備えていることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that the thick film portion comprises ends of the two adjacent thin film portions and a dielectric provided between the ends.
  7. 　前記少なくともいずれかの内部電極層は、延在方向において、所定の間隔で複数の前記厚膜部を備えていることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that at least one of the internal electrode layers has a plurality of the thick film portions at a predetermined interval in the extension direction.
  8. 　前記少なくともいずれかの内部電極層の延在方向における前記厚膜部の長さは、積層方向における前記薄膜部の厚みよりも大きいことを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that the length of the thick film portion in the extension direction of at least one of the internal electrode layers is greater than the thickness of the thin film portion in the stacking direction.
  9. 　前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、
    　積層方向と前記２端面が対向する方向とを含む断面において、前記厚膜部は２層の層が重なって見えることを特徴とする請求項１または請求項２に記載のセラミック電子部品。     The plurality of internal electrode layers are alternately exposed on two opposing end surfaces of the laminate,
    3. The ceramic electronic component according to claim 1, wherein the thick film portion appears as two overlapping layers in a cross section including a lamination direction and a direction in which the two end faces face each other.
  10. 　前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、
    　前記積層体は、前記２端面のうち同じ端面に対して露出する内部電極層同士が異なる端面に露出する内部電極層を介さずに対向するエンドマージンと、前記２端面のうち異なる端面に露出する内部電極層同士が対向する容量部と、を有し、
    　前記少なくともいずれかの内部電極層における前記厚膜部の単位長さ辺りの個数は、前記容量部よりも前記エンドマージンの方が多いことを特徴とする請求項１または請求項２に記載のセラミック電子部品。     The plurality of internal electrode layers are alternately exposed on two opposing end surfaces of the laminate,
    the laminate has an end margin in which the internal electrode layers exposed on the same one of the two end faces face each other without an internal electrode layer exposed on a different end face therebetween, and a capacitance section in which the internal electrode layers exposed on the different one of the two end faces face each other,
    3. The ceramic electronic component according to claim 1, wherein the number of the thick film portions per unit length in at least any of the internal electrode layers is greater in the end margins than in the capacitive portions.
  11. 　前記積層体の対向する２端面に、前記複数の内部電極層が交互に露出しており、
    　前記少なくともいずれかの内部電極層に対する平面視において、前記厚膜部は、前記２端面が対向する方向に対して交差する方向に延びていることを特徴とする請求項１または請求項２に記載のセラミック電子部品。     The plurality of internal electrode layers are alternately exposed on two opposing end surfaces of the laminate,
    3. The ceramic electronic component according to claim 1, wherein, in a plan view of at least any one of the internal electrode layers, the thick film portion extends in a direction intersecting a direction in which the two end faces face each other.
  12. 　前記少なくともいずれかの内部電極層は、金属のみで構成されていることを特徴とする請求項１または請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 1 or 2, characterized in that at least one of the internal electrode layers is made of metal only.
  13. 　誘電体グリーンシート上に、ドライプロセスで内部電極パターンが成膜された積層単位が複数積層された積層体を焼成することで、前記内部電極パターンから形成される少なくともいずれかの内部電極層に、積層方向の厚さが０.５μｍ以下の複数の薄膜部と、隣り合う２つの薄膜部間に形成されかつ積層方向の厚さが前記薄膜部に比べて２倍以上厚い厚膜部と、を形成することを特徴とするセラミック電子部品の製造方法。
    　     A method for manufacturing a ceramic electronic component, comprising the steps of: firing a laminate in which a plurality of lamination units, each having an internal electrode pattern formed by a dry process, are laminated on a dielectric green sheet; and forming, in at least any one of the internal electrode layers formed from the internal electrode pattern, a plurality of thin film portions each having a thickness of 0.5 μm or less in a lamination direction, and a thick film portion formed between two adjacent thin film portions and having a thickness in the lamination direction that is at least twice as thick as the thin film portions.
PCT/JP2023/031319 2022-09-27 2023-08-29 Ceramic electronic component and metho for producing ceramic electronic component WO2024070428A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878274A (en) * 1994-08-31 1996-03-22 Taiyo Yuden Co Ltd Production of ceramic electronic parts
JP2016143764A (en) * 2015-02-02 2016-08-08 太陽誘電株式会社 Multilayer capacitor
JP2021158132A (en) * 2020-03-25 2021-10-07 太陽誘電株式会社 Method for manufacturing multilayer ceramic electronic component and multilayer ceramic electronic component

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878274A (en) * 1994-08-31 1996-03-22 Taiyo Yuden Co Ltd Production of ceramic electronic parts
JP2016143764A (en) * 2015-02-02 2016-08-08 太陽誘電株式会社 Multilayer capacitor
JP2021158132A (en) * 2020-03-25 2021-10-07 太陽誘電株式会社 Method for manufacturing multilayer ceramic electronic component and multilayer ceramic electronic component

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