JP2019186337A - 多層配線構造体及びその製造方法 - Google Patents
多層配線構造体及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
図1は、本発明の第1の実施形態による多層配線構造体1の構造を説明するための略断面図である。
図20は、本発明の第2の実施形態による多層配線構造体2の構造を説明するための略断面図である。
図21は、本発明の第3の実施形態による多層配線構造体3の構造を説明するための略断面図である。
6 基板
8 絶縁膜
11,14,21,31,41,51 下層シード層
12,15,22,32,42,52 上層シード層
13,16,23,33,43,53 主導体層
61〜64 層間絶縁膜
61a〜64a,61b 開口部
61c 中央部
71 結晶
72 界面
C キャパシタ
D 容量絶縁膜
L インダクタ
L1〜L5 配線層
P1a〜P1c,P2a,P2b,P3a,P3b,P4a,P4b,P5a 導体パターン
R1〜R3 フォトレジスト
R2a,R2b 開口部
Claims (9)
- 第1及び第2の配線層を含む複数の配線層が積層されてなる多層配線構造体であって、
前記第1の配線層に設けられ、第1の主導体層を含む第1の導体パターンと、
前記第1の配線層を覆い、前記第1の導体パターンの一部を露出させる開口部を有する層間絶縁膜と、
前記第2の配線層に設けられ、前記開口部を介して前記第1の導体パターンに接続された第2の導体パターンと、を備え、
前記第2の導体パターンは、前記層間絶縁膜と接するシード層と、前記シード層上に設けられ、前記第1の主導体層と同じ金属材料からなる第2の主導体層とを含み、
前記シード層は、前記開口部の底部の少なくとも一部において除去されており、これにより、前記開口部の底部の少なくとも一部において前記第1の主導体層と前記第2の主導体層が前記シード層を介することなく接していることを特徴とする多層配線構造体。 - 前記開口部の内壁面及び底部の外周縁部は前記シード層で覆われており、前記外周縁部に囲まれた中央部において、前記第1の主導体層と前記第2の主導体層が前記シード層を介することなく接していることを特徴とする請求項1に記載の多層配線構造体。
- 前記第1及び第2の主導体層は、銅(Cu)からなることを特徴とする請求項1又は2に記載の多層配線構造体。
- 前記シード層は、クロム(Cr)、ニッケル(Ni)、チタン(Ti)、タングステン(W)、タンタル(Ta)又はこれらのいずれかを含む合金若しくは積層体からなることを特徴とする請求項3に記載の多層配線構造体。
- 前記第1の主導体層と前記第2の主導体層が接している部分においては、前記第1及び第2の主導体層を構成する銅(Cu)の結晶が前記開口部の底部を規定する界面を横切って存在していることを特徴とする請求項3又は4に記載の多層配線構造体。
- 第1及び第2の配線層を含む複数の配線層が積層されてなる多層配線構造体の製造方法であって、
前記第1の配線層に第1の主導体層を含む第1の導体パターンを形成する第1の工程と、
前記第1の配線層を覆う層間絶縁膜を形成する第2の工程と、
前記層間絶縁膜に前記第1の主導体層の一部を露出させる開口部を形成する第3の工程と、
前記層間絶縁膜上及び前記開口部内にシード層を形成する第4の工程と、
前記開口部の底部に形成されたシード層の少なくとも一部を除去することによって、前記第1の主導体層を露出させる第5の工程と、
前記シード層上及び前記第1の主導体層の露出した部分上に、前記第1の主導体層と同じ金属材料からなる第2の主導体層を形成する第6の工程と、を備えることを特徴とする多層配線構造体の製造方法。 - 前記第5の工程においては、前記第1の主導体層と前記シード層の接触部分が残るよう、前記開口部の底部に形成されたシード層を部分的に除去することを特徴とする請求項6に記載の多層配線構造体の製造方法。
- 前記第6の工程においては、前記シード層を介した給電による電解めっきによって前記第2の主導体層を形成することを特徴とする請求項7に記載の多層配線構造体の製造方法。
- 前記シード層は、クロム(Cr)、ニッケル(Ni)、チタン(Ti)、タングステン(W)、タンタル(Ta)又はこれらのいずれかを含む合金若しくは積層体からなる下層シード層と、銅(Cu)からなる上層シード層を含むことを特徴とする請求項8に記載の多層配線構造体の製造方法。
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JP2018073953A JP6747467B2 (ja) | 2018-04-06 | 2018-04-06 | 多層配線構造体及びその製造方法 |
US16/374,556 US10426032B1 (en) | 2018-04-06 | 2019-04-03 | Multilayer wiring structure and its manufacturing method |
CN201910271674.8A CN110349927B (zh) | 2018-04-06 | 2019-04-04 | 多层配线结构体及其制造方法 |
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WO2023032421A1 (ja) * | 2021-08-31 | 2023-03-09 | Tdk株式会社 | Lc複合電子部品 |
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DE102021100457B4 (de) | 2021-01-08 | 2023-10-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Rückseiten- oder vorderseiten-substratdurchkontaktierungslandung (tsv-landung) auf metall |
JP2023069390A (ja) * | 2021-11-05 | 2023-05-18 | イビデン株式会社 | 配線基板 |
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JP2001127155A (ja) | 1999-10-29 | 2001-05-11 | Hitachi Ltd | ビルドアップ基板、及びその製法 |
JP2005142330A (ja) * | 2003-11-06 | 2005-06-02 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2005166757A (ja) * | 2003-11-28 | 2005-06-23 | Advanced Lcd Technologies Development Center Co Ltd | 配線構造体、配線構造体の形成方法、薄膜トランジスタ、薄膜トランジスタの形成方法、及び表示装置 |
US8436252B2 (en) * | 2009-06-30 | 2013-05-07 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
JP5436259B2 (ja) * | 2010-02-16 | 2014-03-05 | 日本特殊陶業株式会社 | 多層配線基板の製造方法及び多層配線基板 |
JP2012059801A (ja) * | 2010-09-07 | 2012-03-22 | Teramikros Inc | 半導体装置及び半導体装置の製造方法 |
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- 2019-04-03 US US16/374,556 patent/US10426032B1/en active Active
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Cited By (1)
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WO2023032421A1 (ja) * | 2021-08-31 | 2023-03-09 | Tdk株式会社 | Lc複合電子部品 |
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JP6747467B2 (ja) | 2020-08-26 |
US20190313528A1 (en) | 2019-10-10 |
CN110349927A (zh) | 2019-10-18 |
CN110349927B (zh) | 2022-11-11 |
US10426032B1 (en) | 2019-09-24 |
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