JP2019114686A - Electronic component built-in substrate, sheet substrate - Google Patents

Electronic component built-in substrate, sheet substrate Download PDF

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Publication number
JP2019114686A
JP2019114686A JP2017247790A JP2017247790A JP2019114686A JP 2019114686 A JP2019114686 A JP 2019114686A JP 2017247790 A JP2017247790 A JP 2017247790A JP 2017247790 A JP2017247790 A JP 2017247790A JP 2019114686 A JP2019114686 A JP 2019114686A
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Japan
Prior art keywords
substrate
electronic component
layer
upper substrate
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017247790A
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Japanese (ja)
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JP6917295B2 (en
Inventor
悟志 松澤
Satoshi Matsuzawa
悟志 松澤
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017247790A priority Critical patent/JP6917295B2/en
Priority to US16/210,050 priority patent/US10727175B2/en
Publication of JP2019114686A publication Critical patent/JP2019114686A/en
Application granted granted Critical
Publication of JP6917295B2 publication Critical patent/JP6917295B2/en
Active legal-status Critical Current
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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Abstract

To restrain reliability decline.SOLUTION: An electronic component built-in substrate 1 has a lower substrate 10 and an upper substrate 20. A semiconductor element 31 is mounted on the lower substrate 10. The upper substrate 20 is placed above the lower substrate 10, and is connected by a substrate connection member 40. An encapsulation resin 50 for encapsulating the semiconductor element 31 and the substrate connection member 40 is formed between the lower substrate 10 and the upper substrate 20. The upper substrate 20 has a substrate body 21, and a solder resist layer 25 formed on the undersurface 21b of the substrate body 21, and a discharge groove 27 extending at least from the immediately above region A1 facing the semiconductor element 31 to the lateral face 20d of the upper substrate 20 is formed in the solder resist layer 25.SELECTED DRAWING: Figure 1

Description

電子部品内蔵基板、シート基板に関する。   The present invention relates to an electronic component built-in substrate and a sheet substrate.

従来、半導体チップ等の電子部品を有した基板の小型化や省スペース化等のため、半導体チップ等の電子部品が埋め込まれた所謂電子部品内蔵基板が提案されている。電子部品内蔵基板は、半導体チップが実装された第１の基板に、はんだボールを介して第２の基板が積層され、第１の基板と第２の基板との間を樹脂封止されている（例えば、特許文献１参照）。   Conventionally, a so-called electronic component built-in substrate in which an electronic component such as a semiconductor chip is embedded has been proposed in order to miniaturize a substrate having an electronic component such as a semiconductor chip or to save space. In the electronic component built-in substrate, the second substrate is stacked via solder balls on the first substrate on which the semiconductor chip is mounted, and resin sealing is performed between the first substrate and the second substrate. (See, for example, Patent Document 1).

国際公開第２００７／０６９６０６号WO 2007/069606

ところで、第１の基板と第２の基板との間の間隔（Ｇａｐ）を狭くして電子部品内蔵基板を薄型化することが考えられる。すると、半導体チップと第２の基板との間に樹脂が十分に充填されず、半導体チップと第２の基板との間にボイドが発生する虞がある。ボイドが発生すると、例えば、ボイドが吸湿して膨張し、ボイドの近傍の樹脂に剥がれが生じる場合があり、電子部品内蔵基板の信頼性を低下させる。   By the way, it is conceivable to narrow the gap (gap) between the first substrate and the second substrate to make the electronic component built-in substrate thinner. Then, the resin is not sufficiently filled between the semiconductor chip and the second substrate, and a void may be generated between the semiconductor chip and the second substrate. If a void is generated, for example, the void may absorb moisture and expand to cause peeling of the resin in the vicinity of the void, which may lower the reliability of the electronic component built-in substrate.

本発明の一観点によれば、電子部品内蔵基板は、下基板と、前記下基板上に実装された電子部品と、前記電子部品及び前記下基板の上方に設けられた上基板と、前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、を有し、前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、前記ソルダーレジスト層には、少なくとも前記電子部品と対向する直上領域から、前記上基板の側面まで延びる溝が形成されている。   According to one aspect of the present invention, the electronic component built-in substrate includes a lower substrate, an electronic component mounted on the lower substrate, an upper substrate provided above the electronic component and the lower substrate, and the lower substrate. A substrate connecting member provided between a substrate and the upper substrate for connecting the lower substrate and the upper substrate, and filled between the lower substrate and the upper substrate, the electronic component and the substrate connecting member And the upper substrate has a substrate body and a solder resist layer formed on the lower surface of the substrate body, and the solder resist layer contains at least the electronic component and the like. A groove is formed extending from the directly above opposite region to the side surface of the upper substrate.

また、本発明の別の一観点によれば、シート基板は、複数の電子部品内蔵基板と、隣接する２つの前記電子部品内蔵基板の間に設定された切断領域と、を有し、前記電子部品内蔵基板は、下基板と、前記下基板上に実装された電子部品と、前記電子部品及び前記下基板の上方に設けられた上基板と、前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、を有し、前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層を有し、前記ソルダーレジスト層には、少なくとも前記電子部品と対向する直上領域から、前記切断領域まで延びる溝が形成されている。   Further, according to another aspect of the present invention, the sheet substrate has a plurality of electronic component built-in substrates and a cutting area set between two adjacent electronic component built-in substrates, The component-embedded substrate is provided between a lower substrate, an electronic component mounted on the lower substrate, an upper substrate provided above the electronic component and the lower substrate, and the lower substrate and the upper substrate. A substrate connecting member for connecting the lower substrate and the upper substrate, and a sealing resin which is filled between the lower substrate and the upper substrate and seals the electronic component and the substrate connecting member. The upper substrate includes a substrate body and a solder resist layer formed on the lower surface of the substrate body, and the solder resist layer extends from at least a region directly opposite the electronic component to the cutting region. A groove is formed.

本発明の一開示によれば、信頼性の低下を抑制できる。   According to one disclosure of the present invention, a decrease in reliability can be suppressed.

（ａ）は電子部品内蔵基板を示す概略断面図、（ｂ）は第２基板を示す概略平面図。(A) is a schematic sectional drawing which shows an electronic component built-in substrate, (b) is a schematic plan view which shows a 2nd board | substrate. （ａ）は上基板を形成するワーク基板を示す概略平面図、（ｂ）はワーク基板の概略断面図。(A) is a schematic plan view which shows the workpiece substrate which forms an upper substrate, (b) is a schematic sectional drawing of a workpiece substrate. （ａ）は封止樹脂形成後のシート基板を示す概略平面図、（ｂ）はシート基板の概略断面図。(A) is a schematic plan view which shows the sheet | seat board | substrate after sealing resin formation, (b) is a schematic sectional drawing of a sheet | seat board | substrate. （ａ）（ｂ）は比較例の電子部品内蔵基板を示す概略断面図、（ｃ）は本実施形態の電子部品内蔵基板の作用を示す概略平面図。(A) and (b) are schematic sectional drawings which show the electronic component built-in board | substrate of a comparative example, (c) is a schematic plan view which shows an effect | action of the electronic component built-in board | substrate of this embodiment. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 図５の第２基板を含むワーク基板の一部を示す概略平面図。FIG. 6 is a schematic plan view showing a part of a work substrate including the second substrate of FIG. 5; 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 図９の第２基板を含むワーク基板の一部を示す概略平面図。FIG. 10 is a schematic plan view showing a part of a work substrate including the second substrate of FIG. 9; 変形例のワーク基板を示す概略断面図。The schematic sectional drawing which shows the workpiece substrate of a modification. 変形例の電子部品内蔵基板を示す概略断面図。The schematic sectional drawing which shows the electronic component built-in board | substrate of a modification.

以下、一実施形態を説明する。
なお、添付図面は、理解を容易にするために構成要素を拡大して示している場合がある。構成要素の寸法比率は実際のものと、または別の図面中のものと異なる場合がある。また、断面図では、理解を容易にするために、一部の構成要素のハッチングを省略している場合がある。 Hereinafter, one embodiment will be described.
The attached drawings may show components in an enlarged manner for easy understanding. The dimensional proportions of the components may differ from the actual ones or from one in another drawing. In addition, in the cross-sectional view, hatching of some components may be omitted to facilitate understanding.

図１（ａ）に示すように、電子部品内蔵基板１は、下基板１０、上基板２０、半導体素子３１、アンダーフィル樹脂３２、基板接続部材４０、封止樹脂５０を有している。電子部品内蔵基板１において、下基板１０と上基板２０とが、下基板１０と上基板２０とを電気的に接続する基板接続部材４０を介して積層されている。   As shown in FIG. 1A, the electronic component built-in substrate 1 has a lower substrate 10, an upper substrate 20, a semiconductor element 31, an underfill resin 32, a substrate connecting member 40, and a sealing resin 50. In the electronic component built-in substrate 1, the lower substrate 10 and the upper substrate 20 are stacked via a substrate connecting member 40 that electrically connects the lower substrate 10 and the upper substrate 20.

下基板１０は、基板本体１１、配線層１２、ソルダーレジスト層１３、配線層１４、ソルダーレジスト層１５を有している。
配線層１２は、基板本体１１の上面に形成されている。配線層１４は、基板本体１１の下面に形成されている。配線層１２，１４の材料としては、例えば銅（Ｃｕ）等を用いることができる。 The lower substrate 10 includes a substrate body 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15.
The wiring layer 12 is formed on the upper surface of the substrate body 11. The wiring layer 14 is formed on the lower surface of the substrate body 11. As a material of the wiring layers 12 and 14, for example, copper (Cu) or the like can be used.

基板本体１１は、配線層１２と配線層１４とを相互に電気的に接続する構造を有していれば十分である。このため、基板本体１１の内部には配線層が形成されていてもよく、配線層が形成されていなくてもよい。なお、基板本体１１の内部に配線層が形成される場合には、複数の配線層が絶縁層を介して積層され、絶縁層に形成されたビアと配線層によって上記配線層１２と配線層１４を電気的に接続する。内部に形成される配線層やビアの材料としては、たとえば銅や銅合金を用いることができる。絶縁層の材料としては、たとえばエポキシ樹脂やポリイミド樹脂などの絶縁性樹脂、又はこれら樹脂にシリカやアルミナ等のフィラーを混入した樹脂材を用いることができる。基板本体１１としては、例えばコア基板を有するコア付きビルドアップ基板やコア基板を有さないコアレス基板等を用いることができる。また、基板本体１１として、シリコン基板やセラミック基板等を用いてもよい。   It is sufficient for the substrate body 11 to have a structure for electrically connecting the wiring layer 12 and the wiring layer 14 to each other. For this reason, a wiring layer may be formed inside the substrate main body 11, and the wiring layer may not be formed. When the wiring layer is formed inside the substrate body 11, a plurality of wiring layers are stacked via the insulating layer, and the wiring layer 12 and the wiring layer 14 are formed by the via and the wiring layer formed in the insulating layer. Electrically connected. For example, copper or a copper alloy can be used as a material of the wiring layer or via formed inside. As a material of the insulating layer, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with the resin can be used. As the substrate body 11, for example, a cored build-up substrate having a core substrate, a coreless substrate not having a core substrate, or the like can be used. Alternatively, a silicon substrate, a ceramic substrate or the like may be used as the substrate body 11.

ソルダーレジスト層１３は、基板本体１１の上面と配線層１２の一部を覆うように設けられている。ソルダーレジスト層１３は、配線層１２の一部をパッド１６として露出する開口部１３Ｙと、配線層１２の一部を接続パッド１７として露出する開口部１３Ｘとを有している。ソルダーレジスト層１３の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。   The solder resist layer 13 is provided to cover the top surface of the substrate body 11 and a part of the wiring layer 12. The solder resist layer 13 has an opening 13 Y exposing a part of the wiring layer 12 as a pad 16 and an opening 13 X exposing a part of the wiring layer 12 as a connection pad 17. As a material of the solder resist layer 13, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、必要に応じて、開口部１３Ｘ，１３Ｙから露出する配線層１２上にＯＳＰ（Organic Solderability Preservative）処理を施してＯＳＰ膜を形成し、そのＯＳＰ膜に上記半導体素子３１を接続するようにしてもよい。また、開口部１３Ｘ，１３Ｙから露出する配線層１２上に金属層を形成してもよい。金属層の例としては、金（Ａｕ）層や、ニッケル（Ｎｉ）層／Ａｕ層（配線層１２上にＮｉ層とＡｕ層をこの順番で積層した金属層）や、Ｎｉ層／パラジウム（Ｐｄ）層／Ａｕ層（配線層１２上にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。これらＮｉ層、Ａｕ層、Ｐｄ層としては、例えば無電解めっき法により形成された金属層（無電解めっき金属層）を用いることができる。また、上記Ａｕ層はＡｕ又はＡｕ合金からなる金属層、上記Ｎｉ層はＮｉ又はＮｉ合金からなる金属層、上記Ｐｄ層はＰｄ又はＰｄ合金からなる金属層である。   If necessary, an OSP (Organic Solderability Preservative) treatment is performed on the wiring layer 12 exposed from the openings 13X and 13Y to form an OSP film, and the semiconductor element 31 is connected to the OSP film. It is also good. In addition, a metal layer may be formed on the wiring layer 12 exposed from the openings 13X and 13Y. Examples of the metal layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are stacked in this order on the wiring layer 12), a Ni layer / palladium (Pd) Layer / Au layer (a metal layer in which a Ni layer, a Pd layer and an Au layer are laminated in this order on the wiring layer 12) and the like can be mentioned. As the Ni layer, the Au layer, and the Pd layer, for example, a metal layer (electroless plating metal layer) formed by electroless plating can be used. The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

パッド１６は、バンプ３３を介して半導体素子３１に接続されている。すなわち、半導体素子３１は、下基板１０に対してフリップチップ実装されている。半導体素子３１としては、たとえばＣＰＵ(Central Processing Unit)チップやＧＰＵ(Graphics Processing Unit)チップなどのロジックチップを用いることができる。また、半導体素子３１としては、たとえばＤＲＡＭ(Dynamic Random Access Memory)チップ、ＳＲＡＭ(Static Random Access Memory)チップやフラッシュメモリチップなどのメモリチップを用いることもできる。   The pad 16 is connected to the semiconductor element 31 via the bump 33. That is, the semiconductor element 31 is flip chip mounted on the lower substrate 10. As the semiconductor element 31, for example, a logic chip such as a central processing unit (CPU) chip or a graphics processing unit (GPU) chip can be used. Further, as the semiconductor element 31, for example, a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, or a flash memory chip can be used.

バンプ３３としては、パッド１６上のバンプ、半導体素子３１のパッド上のバンプ、又は双方のバンプを用いることができる。バンプ３３としては、例えば、金バンプやはんだバンプを用いることができる。はんだバンプの材料としては、例えば、鉛（Ｐｂ）を含む合金、錫（Ｓｎ）とＡｕの合金、ＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。   As the bumps 33, bumps on the pads 16, bumps on the pads of the semiconductor element 31, or both bumps can be used. As the bumps 33, for example, gold bumps or solder bumps can be used. As the material of the solder bump, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. may be used it can.

なお、下基板１０に半導体素子３１を実装したが、これに限らず、他の電子部品（例えば、キャパシタ、インダクタ等）を下基板１０に実装してもよい。また、複数の電子部品を下基板１０に実装してもよい。   Although the semiconductor element 31 is mounted on the lower substrate 10, the present invention is not limited to this, and other electronic components (for example, a capacitor, an inductor, etc.) may be mounted on the lower substrate 10. Further, a plurality of electronic components may be mounted on the lower substrate 10.

アンダーフィル樹脂３２は、下基板１０の上面と半導体素子３１との間に充填されている。アンダーフィル樹脂３２の材料としては、例えばエポキシ樹脂などの絶縁性樹脂を用いることができる。   The underfill resin 32 is filled between the upper surface of the lower substrate 10 and the semiconductor element 31. As a material of the underfill resin 32, for example, an insulating resin such as an epoxy resin can be used.

ソルダーレジスト層１５は、基板本体１１の下面と配線層１４の一部を覆うように形成されている。ソルダーレジスト層１５は、配線層１４の一部を外部接続パッド１８として露出する開口部１５Ｘを有している。ソルダーレジスト層１５の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。   The solder resist layer 15 is formed to cover the lower surface of the substrate body 11 and a part of the wiring layer 14. The solder resist layer 15 has an opening 15 </ b> X that exposes a part of the wiring layer 14 as the external connection pad 18. As a material of the solder resist layer 15, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

外部接続パッド１８には、この電子部品内蔵基板１をマザーボード等の実装基板（図示略）に実装する際に使用される外部接続端子６０が接続されている。外部接続端子６０は、例えば、はんだボールである。なお、外部接続端子６０として、はんだバンプやリードピン等を外部接続パッド１８に接続してもよい。   An external connection terminal 60 used when mounting the electronic component built-in substrate 1 on a mounting substrate (not shown) such as a motherboard is connected to the external connection pad 18. The external connection terminal 60 is, for example, a solder ball. A solder bump, a lead pin or the like may be connected to the external connection pad 18 as the external connection terminal 60.

なお、必要に応じて、ソルダーレジスト層１５の開口部１５Ｘから露出する配線層１４の表面にＯＳＰ処理を施してＯＳＰ膜を形成し、そのＯＳＰ膜に外部接続端子６０を接続してもよい。また、開口部１５Ｘから露出する配線層１４の表面に金属層を形成し、その金属層に外部接続端子６０を接続してもよい。金属層の例としては、Ａｕ層や、Ｎｉ層／Ａｕ層（配線層１４の表面にＮｉ層とＡｕ層をこの順番で積層した金属層）、Ｎｉ層／Ｐｄ層／Ａｕ層（配線層１４の表面にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。なお、開口部１５Ｘから露出する配線層１４（あるいは、配線層１４上にＯＳＰ膜や金属層が形成されている場合には、それらＯＳＰ膜又は金属層）自体を、外部接続端子としてもよい。   If necessary, an OSP process may be performed on the surface of the wiring layer 14 exposed from the opening 15X of the solder resist layer 15 to form an OSP film, and the external connection terminal 60 may be connected to the OSP film. Alternatively, a metal layer may be formed on the surface of the wiring layer 14 exposed from the opening 15X, and the external connection terminal 60 may be connected to the metal layer. Examples of the metal layer include an Au layer, a Ni layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order on the surface of the wiring layer 14), a Ni layer / Pd layer / Au layer (wiring layer 14) And a metal layer in which a Ni layer, a Pd layer and an Au layer are laminated in this order on the surface of Note that the wiring layer 14 exposed from the opening 15X (or, if an OSP film or a metal layer is formed on the wiring layer 14, the OSP film or the metal layer) itself may be used as the external connection terminal.

上基板２０は、基板本体２１、ソルダーレジスト層２３、配線層２４、ソルダーレジスト層２５を有している。
ソルダーレジスト層２３は、基板本体２１の上面を覆うように設けられている。ソルダーレジスト層２３の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。 The upper substrate 20 has a substrate body 21, a solder resist layer 23, a wiring layer 24, and a solder resist layer 25.
The solder resist layer 23 is provided so as to cover the upper surface of the substrate body 21. As a material of the solder resist layer 23, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、上基板２０において、基板本体２１の上面に配線層が形成されていてもよい。その場合、ソルダーレジスト層２３に、配線層の一部をパッドとして露出する開口部を形成することもできる。そして、必要に応じて、ソルダーレジスト層２３から配線層にＩＳＰ膜や金属層を形成することもできる。   A wiring layer may be formed on the upper surface of the substrate body 21 in the upper substrate 20. In that case, an opening may be formed in the solder resist layer 23 to expose a part of the wiring layer as a pad. Then, if necessary, an ISP film or a metal layer can be formed from the solder resist layer 23 to the wiring layer.

配線層２４は、基板本体２１の下面に形成されている。配線層２４の材料としては、例えば銅（Ｃｕ）等を用いることができる。
基板本体２１としては、内部に配線層が形成されていてもよく、配線層が形成されていなくてもよい。なお、基板本体２１の内部に配線層が形成される場合には、複数の配線層が絶縁層を介して積層され、絶縁層に形成されたビアと配線層によって内部の配線層が配線層２４と電気的に接続される。内部に形成される配線層やビアの材料としては、たとえば銅や銅合金を用いることができる。絶縁層の材料としては、たとえばエポキシ樹脂やポリイミド樹脂などの絶縁性樹脂、又はこれら樹脂にシリカやアルミナ等のフィラーを混入した樹脂材を用いることができる。基板本体２１としては、例えばコア基板を有するコア付きビルドアップ基板やコア基板を有さないコアレス基板等を用いることができる。また、基板本体２１として、シリコン基板やセラミック基板等を用いてもよい。 The wiring layer 24 is formed on the lower surface of the substrate body 21. As a material of the wiring layer 24, for example, copper (Cu) or the like can be used.
As the substrate body 21, a wiring layer may be formed inside, or the wiring layer may not be formed. In the case where a wiring layer is formed inside the substrate body 21, a plurality of wiring layers are stacked via the insulating layer, and the wiring layer inside is formed by the via and the wiring layer formed in the insulating layer. And electrically connected. For example, copper or a copper alloy can be used as a material of the wiring layer or via formed inside. As a material of the insulating layer, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with the resin can be used. For example, a cored buildup substrate having a core substrate, a coreless substrate not having a core substrate, or the like can be used as the substrate body 21. Alternatively, a silicon substrate, a ceramic substrate or the like may be used as the substrate body 21.

ソルダーレジスト層２５は、基板本体２１の下面と配線層２４の一部を覆うように形成されている。ソルダーレジスト層２５は、配線層２４の一部を接続パッド２６として露出する開口部２５Ｘと、後述する排出溝２７を有している。ソルダーレジスト層２５の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。   The solder resist layer 25 is formed to cover the lower surface of the substrate body 21 and a part of the wiring layer 24. The solder resist layer 25 has an opening 25 </ b> X that exposes a part of the wiring layer 24 as the connection pad 26 and a discharge groove 27 described later. As a material of the solder resist layer 25, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、必要に応じて、ソルダーレジスト層２５の開口部２５Ｘから露出する配線層２４の表面にＯＳＰ処理を施してＯＳＰ膜を形成してもよい。また、開口部２５Ｘから露出する配線層２４上に金属層を形成してもよい。金属層の例としては、Ａｕ層や、Ｎｉ層／Ａｕ層（配線層２４の表面にＮｉ層とＡｕ層をこの順番で積層した金属層）、Ｎｉ層／Ｐｄ層／Ａｕ層（配線層２４の表面にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。   If necessary, an OSP process may be performed on the surface of the wiring layer 24 exposed from the opening 25X of the solder resist layer 25 to form an OSP film. In addition, a metal layer may be formed on the wiring layer 24 exposed from the opening 25X. Examples of the metal layer include an Au layer, a Ni layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order on the surface of the wiring layer 24), a Ni layer / Pd layer / Au layer (wiring layer 24) And a metal layer in which a Ni layer, a Pd layer and an Au layer are laminated in this order on the surface of

下基板１０の接続パッド１７は、基板接続部材４０を介して上基板２０の接続パッド２６に接続されている。
基板接続部材４０は、下基板１０と上基板２０とを電気的に接続する機能を有する。また、基板接続部材４０は、下基板１０と上基板２０との間に所定の間隔（離間距離，ギャップ）を規定値とする機能を有する。 The connection pad 17 of the lower substrate 10 is connected to the connection pad 26 of the upper substrate 20 via the substrate connection member 40.
The substrate connecting member 40 has a function of electrically connecting the lower substrate 10 and the upper substrate 20. Further, the substrate connecting member 40 has a function of setting a predetermined distance (separation distance, gap) between the lower substrate 10 and the upper substrate 20 as a prescribed value.

基板接続部材４０としては、例えばコア付きはんだボールを用いることができる。基板接続部材４０は、略球状のコア４１と、コア４１の外周面を被覆するはんだ４２とを有する。コア４１の材料としては、例えばＣｕ等の金属からなる金属コアや、樹脂からなる樹脂コアを用いることができる。はんだ４２としては、Ｐｂを含む合金、ＳｎとＣｕの合金、ＳｎとＳｂの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等のはんだ材料を用いることができる。   As the substrate connecting member 40, for example, a cored solder ball can be used. The substrate connecting member 40 has a substantially spherical core 41 and a solder 42 covering the outer peripheral surface of the core 41. As a material of the core 41, for example, a metal core made of a metal such as Cu or a resin core made of a resin can be used. As the solder 42, a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, or the like can be used.

なお、基板接続部材４０は、コア４１及びはんだ４２を備えたコア付きのはんだボールには限定されず、例えば、コアを有していないはんだボール等を用いることもできる。又、銅ポスト等の金属ポストや金バンプ等の金属バンプを用いることもできる。コアを有していない、はんだボール等を用いた場合には、電子部品内蔵基板１の製造時に、所定の治具を用いて、下基板１０と上基板２０との間隔を設定できる。   The substrate connecting member 40 is not limited to a cored solder ball provided with the core 41 and the solder 42. For example, a solder ball having no core may be used. Alternatively, metal posts such as copper posts or metal bumps such as gold bumps can be used. When a solder ball or the like not having a core is used, the distance between the lower substrate 10 and the upper substrate 20 can be set using a predetermined jig when the electronic component built-in substrate 1 is manufactured.

封止樹脂５０は、下基板１０と上基板２０との間の空間に充填されている。この封止樹脂５０は、半導体素子３１、基板接続部材４０、アンダーフィル樹脂３２を封止する。この封止樹脂５０により、上基板２０が下基板１０に対して固定される。封止樹脂５０は、下基板１０と上基板２０とを接着する接着剤として機能する。また、封止樹脂５０は、半導体素子３１、基板接続部材４０を保護する保護層として機能する。また、封止樹脂５０は、電子部品内蔵基板１全体の機械的強度を高める。   The sealing resin 50 is filled in the space between the lower substrate 10 and the upper substrate 20. The sealing resin 50 seals the semiconductor element 31, the substrate connecting member 40, and the underfill resin 32. The upper substrate 20 is fixed to the lower substrate 10 by the sealing resin 50. The sealing resin 50 functions as an adhesive for bonding the lower substrate 10 and the upper substrate 20. In addition, the sealing resin 50 functions as a protective layer that protects the semiconductor element 31 and the substrate connecting member 40. Further, the sealing resin 50 enhances the mechanical strength of the entire electronic component built-in substrate 1.

封止樹脂５０の材料としては、例えば、エポキシ系樹脂やポリイミド系樹脂などの絶縁性樹脂を用いることができる。また、封止樹脂５０の材料としては、例えば、エポキシ系樹脂やポリイミド系樹脂にシリカ等のフィラーを混入した樹脂材を用いることができる。フィラーとしては、シリカ以外に、例えば、酸化チタン、酸化アルミニウム、窒化アルミニウム、炭化珪素、チタン酸カルシウム、ゼオライト等の無機化合物、又は、有機化合物等を用いることができる。また、封止樹脂５０としては、例えば、トランスファーモールド法、コンプレッションモールド法やインジェクションモールド法などにより形成されたモールド樹脂を用いることができる。   As a material of the sealing resin 50, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used. Moreover, as a material of the sealing resin 50, for example, a resin material in which a filler such as silica is mixed into an epoxy resin or a polyimide resin can be used. As the filler, in addition to silica, for example, inorganic compounds such as titanium oxide, aluminum oxide, aluminum nitride, silicon carbide, calcium titanate, zeolite, or organic compounds can be used. Further, as the sealing resin 50, for example, a mold resin formed by a transfer molding method, a compression molding method, an injection molding method, or the like can be used.

図１（ａ）に示すように、上基板２０において、封止樹脂５０により覆われるソルダーレジスト層２５には、複数の排出溝２７が形成されている。例えば、複数の排出溝２７は、基板本体２１の下面２１ｂを露出するように形成されている。なお、排出溝２７の深さをソルダーレジスト層２５の厚さよりも小さくして基板本体２１の下面２１ｂが薄いソルダーレジスト層２５により覆われるようにしてもよい。また、排出溝２７により、基板本体２１の下面に形成された配線層２４が露出されてもよい。   As shown in FIG. 1A, in the upper substrate 20, a plurality of discharge grooves 27 are formed in the solder resist layer 25 covered by the sealing resin 50. For example, the plurality of discharge grooves 27 are formed to expose the lower surface 21 b of the substrate body 21. The depth of the discharge groove 27 may be smaller than the thickness of the solder resist layer 25 so that the lower surface 21 b of the substrate body 21 is covered with the thin solder resist layer 25. Further, the wiring layer 24 formed on the lower surface of the substrate main body 21 may be exposed by the discharge groove 27.

図１（ｂ）に示すように、上基板２０は、矩形状に形成されている。図１（ｂ）において、図１（ａ）の半導体素子３１と対向する直上領域Ａ１を一点鎖線にて示している。上基板２０のソルダーレジスト層２５は、接続パッド２６を露出する複数の開口部２５Ｘを有している。この開口部２５Ｘは、半導体素子３１より外側に形成されている。   As shown in FIG. 1B, the upper substrate 20 is formed in a rectangular shape. In FIG. 1B, the directly above region A1 facing the semiconductor element 31 of FIG. 1A is indicated by an alternate long and short dash line. The solder resist layer 25 of the upper substrate 20 has a plurality of openings 25 X exposing the connection pads 26. The opening 25X is formed outside the semiconductor element 31.

上基板２０は、側面２０ａ，２０ｂ，２０ｃ，２０ｄを有している。側面２０ａ，２０ｂは、互いに対向する第１の側面対を構成し、側面２０ｃ，２０ｄは、互いに対向する第２の側面対を構成する。本実施形態において、開口部２５Ｘは、上基板２０の互いに対向する２対の側面２０ａ，２０ｂ，２０ｃ，２０ｄのうちの１対の側面２０ａ，２０ｂに沿って一列に配列されている。これらの開口部２５Ｘから露出する接続パッド２６に、図１（ａ）に示す基板接続部材４０が接続される。   The upper substrate 20 has side surfaces 20a, 20b, 20c and 20d. The side surfaces 20a and 20b constitute a first side pair facing each other, and the side surfaces 20c and 20d constitute a second side pair facing each other. In the present embodiment, the openings 25X are arranged in a line along a pair of side surfaces 20a, 20b of the two pairs of side surfaces 20a, 20b, 20c, 20d opposed to each other in the upper substrate 20. The substrate connection member 40 shown in FIG. 1A is connected to the connection pads 26 exposed from the openings 25X.

複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１から、開口部２５Ｘの配列方向（図１（ｂ）において上方）に沿って延びるように形成されている。そして、複数の排出溝２７は、上基板２０の互いに対向する２対の辺のうち、上述の開口部２５Ｘが沿っていない１対の側面２０ｃ，２０ｄのうちの一方の側面２０ｄまで延びている。   The plurality of discharge grooves 27 are formed to extend along the arrangement direction of the openings 25X (upward in FIG. 1B) from the region A1 directly above the semiconductor element 31. The plurality of discharge grooves 27 extend to one side surface 20d of the pair of side surfaces 20c and 20d along which the opening 25X does not extend, out of the two pairs of opposing sides of the upper substrate 20. .

また、本実施形態において、複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１内の先端２７ａから側面２０ｄの端部２７ｂに向けて徐々に幅広となるように形成されている。そして、複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１に多くの排出溝２７を配置するように、側面２０ｄに向けて広がる放射状に形成されている。   Further, in the present embodiment, the plurality of discharge grooves 27 are formed so as to gradually widen from the tip end 27a in the immediately upper region A1 facing the semiconductor element 31 to the end 27b of the side surface 20d. The plurality of discharge grooves 27 are formed radially extending toward the side surface 20 d such that many discharge grooves 27 are disposed in the area A <b> 1 immediately above the semiconductor element 31.

上述したように、図１（ａ）に示す封止樹脂５０は、半導体素子３１を実装し基板接続部材４０により互いに接続した下基板１０と上基板２０とを、例えば封止金型内に配設し、封止金型内に樹脂を注入して形成される。このとき、樹脂は、図１（ｂ）に示す上基板２０に対して下方から注入される。つまり、複数の排出溝２７は、幅が細い先端２７ａを樹脂の注入側として、その樹脂の注入方向に沿って幅広となるように形成されている。   As described above, the sealing resin 50 shown in FIG. 1A arranges the lower substrate 10 and the upper substrate 20 which are mounted on the semiconductor element 31 and connected to each other by the substrate connecting member 40, for example, in a sealing mold. Then, the resin is injected into the sealing mold and formed. At this time, the resin is injected from below to the upper substrate 20 shown in FIG. That is, the plurality of discharge grooves 27 are formed to be wider along the injection direction of the resin, with the thin end 27a as the injection side of the resin.

図２（ａ）及び図２（ｂ）は、上基板２０を形成するワーク基板１２０を示す。なお、図２（ａ）及び図２（ｂ）において、図１（ａ）に示す電子部品内蔵基板１の各部材を形成する部材等については同じ符号を付して説明する。   FIGS. 2A and 2B show a work substrate 120 on which the upper substrate 20 is formed. In FIG. 2A and FIG. 2B, the members forming the respective members of the electronic component built-in substrate 1 shown in FIG. 1A will be described with the same reference numerals.

このワーク基板１２０は、複数（図２（ａ）では６つ）の上基板２０として個片化される領域（以下、単に上基板２０を用いる）を含む大判の基板である。
ワーク基板１２０には、上基板２０がマトリックス状（図２（ａ）では、２×３）に配置されている。ワーク基板１２０には、シート切断の工程において上基板２０を個片化するための切断領域Ａ２が設定されている。切断領域Ａ２は、各上基板２０を囲むように設定されている。 The work substrate 120 is a large-sized substrate including a plurality of regions (six in FIG. 2A) to be singulated as the upper substrate 20 (hereinafter, the upper substrate 20 is simply used).
The upper substrate 20 is arranged on the work substrate 120 in a matrix (2 × 3 in FIG. 2A). In the work substrate 120, a cutting area A2 for dividing the upper substrate 20 in the sheet cutting process is set. The cutting area A2 is set to surround each upper substrate 20.

図２（ｂ）に示すように、ワーク基板１２０は、基板本体１２１と、基板本体１２１の下面のソルダーレジスト層１２５とを有している。なお、ワーク基板１２０は、上述の上基板２０の配線層２４に対応する配線層と、上基板２０のソルダーレジスト層２３に対応するソルダーレジスト層とを有しているが、図２（ｂ）では省略している。   As shown in FIG. 2B, the work substrate 120 has a substrate body 121 and a solder resist layer 125 on the lower surface of the substrate body 121. The work substrate 120 has a wiring layer corresponding to the wiring layer 24 of the upper substrate 20 described above and a solder resist layer corresponding to the solder resist layer 23 of the upper substrate 20, as shown in FIG. 2 (b). It is omitted.

ソルダーレジスト層１２５には、上述したように、図１（ａ）に示す配線層２４の一部を接続パッド２６として露出する開口部２５Ｘと、直上領域Ａ１から延びる複数の排出溝２７が形成されている。ワーク基板１２０において、排出溝２７は、各上基板２０における直上領域Ａ１の内側から、各上基板２０の外側の切断領域Ａ２まで延びるように形成されている。排出溝２７と開口部２５Ｘは、例えば、フォトリソグラフィ法により形成される。   In the solder resist layer 125, as described above, the opening 25X exposing a part of the wiring layer 24 shown in FIG. 1A as the connection pad 26 and a plurality of discharge grooves 27 extending from the directly above area A1 are formed. ing. In the work substrate 120, the discharge grooves 27 are formed to extend from the inside of the immediately upper area A1 of each upper substrate 20 to the cutting area A2 of the outer side of each upper substrate 20. The discharge groove 27 and the opening 25X are formed, for example, by photolithography.

ワーク基板１２０は、側面１２０ａ，１２０ｂ，１２０ｃ，１２０ｄを有している。側面１２０ａ，１２０ｂは、互いに対向する第１の側面対を構成し、側面１２０ｃ，１２０ｄは、互いに対向する第２の側面対を構成する。本実施形態のワーク基板１２０において、開口部２５Ｘは、ワーク基板１２０の互いに対向する２対の側面１２０ａ，１２０ｂ，１２０ｃ，１２０ｄのうちの１対の側面１２０ａ，１２０ｂと平行に配列されている。ワーク基板１２０は、これらの開口部２５Ｘから露出する接続パッド２６を有している。   The work substrate 120 has side surfaces 120a, 120b, 120c, and 120d. The side surfaces 120a and 120b constitute a first side pair opposed to each other, and the side surfaces 120c and 120d constitute a second side pair opposed to each other. In the work substrate 120 of the present embodiment, the openings 25X are arranged in parallel with one pair of side surfaces 120a and 120b of the two pairs of side surfaces 120a, 120b, 120c and 120d facing each other of the work substrate 120. The work substrate 120 has connection pads 26 exposed from the openings 25X.

複数の排出溝２７は、図１に示す半導体素子３１の直上領域Ａ１から、開口部２５Ｘの配列方向（図２（ａ）において左右方向）に沿って延びるように形成されている。そして、複数の排出溝２７は、ワーク基板１２０の互いに対向する２対の辺のうち、上述の開口部２５Ｘが沿っていない１対の側面１２０ｃ，１２０ｄのうちの一方の側面１２０ｄに向って、隣接する上基板２０の間の切断領域Ａ２まで延びている。   The plurality of discharge grooves 27 are formed to extend from the region A1 immediately above the semiconductor element 31 shown in FIG. 1 along the arrangement direction of the openings 25X (the left-right direction in FIG. 2A). The plurality of discharge grooves 27 are directed toward one side surface 120d of the pair of side surfaces 120c and 120d along which the opening 25X does not extend, of the two pairs of opposing sides of the work substrate 120. It extends to the cutting area A2 between the adjacent upper substrates 20.

また、本実施形態のワーク基板１２０において、複数の排出溝２７は、図１（ａ）に示す半導体素子３１と対向する直上領域Ａ１内の先端２７ａから切断領域Ａ２の端部２７ｂに向けて徐々に幅広となるように形成されている。そして、複数の排出溝２７は、直上領域Ａ１に多くの排出溝２７を配置するように、側面１２０ｄ側の切断領域Ａ２に向けて広がる放射状に形成されている。   Further, in the work substrate 120 of the present embodiment, the plurality of discharge grooves 27 are gradually moved from the tip 27a in the immediately above area A1 facing the semiconductor element 31 shown in FIG. 1A toward the end 27b of the cutting area A2. It is formed to be wide. The plurality of discharge grooves 27 are radially formed so as to expand toward the cutting area A2 on the side surface 120d so as to arrange the many discharge grooves 27 in the directly above area A1.

図３（ａ）及び図３（ｂ）は、シート切断前のシート基板１００を示す。シート基板１００には複数（図３（ａ）では６つ）の電子部品内蔵基板１がマトリックス状に形成されている。なお、図３（ａ）及び図３（ｂ）において、図１（ａ）に示す電子部品内蔵基板１の各部材を形成する部材等については同じ符号を付して説明する。なお、図３（ａ）及び図３（ｂ）では、図１（ａ）に示す半導体素子３１を接続するバンプ３３、アンダーフィル樹脂３２、等が省略されている。   FIG. 3A and FIG. 3B show the sheet substrate 100 before cutting the sheet. A plurality of (six in FIG. 3A) electronic component embedded substrates 1 are formed in a matrix on the sheet substrate 100. In FIG. 3A and FIG. 3B, the members forming the respective members of the electronic component built-in substrate 1 shown in FIG. 1A will be described with the same reference numerals. In FIG. 3A and FIG. 3B, the bumps 33 connecting the semiconductor element 31 shown in FIG. 1A, the underfill resin 32, and the like are omitted.

このシート基板１００は、図２（ａ）及び図２（ｂ）に示すワーク基板１２０と、図１（ａ）に示す下基板１０を形成するワーク基板１１０とが、図３（ａ）に示す基板接続部材４０により接続されている。図３（ｂ）に示すように、下基板１０の上面に半導体素子３１が実装されている。上基板２０のソルダーレジスト層１２５に形成された排出溝２７は、半導体素子３１の直上領域から、一点鎖線にて示す切断領域Ａ２まで延びている。そして、下基板１０を形成するワーク基板１１０と、上基板２０を形成するワーク基板１２０の間に、封止樹脂５０が形成されている。   In this sheet substrate 100, a work substrate 120 shown in FIGS. 2 (a) and 2 (b) and a work substrate 110 forming the lower substrate 10 shown in FIG. 1 (a) are shown in FIG. 3 (a). It is connected by the board connection member 40. As shown in FIG. 3 (b), the semiconductor element 31 is mounted on the upper surface of the lower substrate 10. The discharge groove 27 formed in the solder resist layer 125 of the upper substrate 20 extends from a region immediately above the semiconductor element 31 to a cutting region A2 indicated by an alternate long and short dash line. A sealing resin 50 is formed between the work substrate 110 forming the lower substrate 10 and the work substrate 120 forming the upper substrate 20.

封止樹脂５０は、半導体素子３１を実装し基板接続部材４０により互いに接続したワーク基板１１０と上述のワーク基板１２０とを、例えば封止金型内に配設し、封止金型内に樹脂を注入して形成される。このとき、樹脂は、図３（ａ）に示すように、ワーク基板１２０に対して側面１２０ｃの側から注入される。つまり、複数の排出溝２７は、幅が細い先端２７ａを樹脂の注入側として、その樹脂の注入方向にそって幅広となるように形成されている。   The sealing resin 50 arranges the work substrate 110 and the above-mentioned work substrate 120 which are mounted on the semiconductor element 31 and connected to each other by the substrate connecting member 40, for example, in the sealing die and the resin in the sealing die. Injection. At this time, as shown in FIG. 3A, the resin is injected from the side surface 120c side with respect to the work substrate 120. That is, the plurality of discharge grooves 27 are formed to be wider along the injection direction of the resin, with the tip 27a having a narrow width as the injection side of the resin.

封止樹脂５０を形成したシート基板１００は、シート切断にて切断領域Ａ２が切断され、図１（ａ）に示す電子部品内蔵基板１が形成される。
（作用）
図１（ａ）に示すように、電子部品内蔵基板１は、下基板１０と上基板２０とを有している。下基板１０には半導体素子３１が実装されている。上基板２０は下基板１０の上方に配置され、基板接続部材４０により接続されている。下基板１０と上基板２０との間には、半導体素子３１と基板接続部材４０を封止する封止樹脂５０が形成されている。上基板２０は、基板本体２１と、基板本体２１の下面２１ｂに形成されたソルダーレジスト層２５とを有し、ソルダーレジスト層２５には、少なくとも半導体素子３１と対向する直上領域Ａ１から、上基板２０の側面２０ｄまで延びる排出溝２７が形成されている。この排出溝２７により、封止樹脂５０の形成時に生じるボイドの残存を抑制する。これを、比較例と比較して説明する。 In the sheet substrate 100 on which the sealing resin 50 is formed, the cutting area A2 is cut by sheet cutting, and the electronic component built-in substrate 1 shown in FIG. 1A is formed.
(Action)
As shown in FIG. 1A, the electronic component built-in substrate 1 has a lower substrate 10 and an upper substrate 20. A semiconductor element 31 is mounted on the lower substrate 10. The upper substrate 20 is disposed above the lower substrate 10 and connected by the substrate connecting member 40. A sealing resin 50 for sealing the semiconductor element 31 and the substrate connecting member 40 is formed between the lower substrate 10 and the upper substrate 20. The upper substrate 20 has a substrate body 21 and a solder resist layer 25 formed on the lower surface 21b of the substrate body 21. The solder resist layer 25 includes at least a region directly above the semiconductor element 31 from the upper substrate A1. A discharge groove 27 extending to the side surface 20 d of 20 is formed. The discharge groove 27 suppresses the remaining of the void generated when the sealing resin 50 is formed. This will be described in comparison with a comparative example.

図４（ａ）、図４（ｂ）は、比較例の電子部品内蔵基板２００，２１０を示す。
図４（ａ）に示す電子部品内蔵基板１は、下基板１０と上基板２０との間の距離（ギャップ）は、半導体素子３１と上基板２０との間に封止樹脂５０を十分に充填するように設定されている。図４（ｂ）に示す電子部品内蔵基板１は、小型化のため、図４（ａ）に示す電子部品内蔵基板１のギャップＧ１と比べ、下基板１０と上基板２０との間のギャップＧ２が狭く設定されている。この電子部品内蔵基板１では、半導体素子３１と上基板２０との間に十分に封止樹脂５０が充填されず、上基板２０の下面にボイド（気泡）Ｂ１が発生する。 FIG. 4A and FIG. 4B show electronic component built-in substrates 200 and 210 of the comparative example.
In the electronic component built-in substrate 1 shown in FIG. 4A, the distance (gap) between the lower substrate 10 and the upper substrate 20 is sufficiently filled with the sealing resin 50 between the semiconductor element 31 and the upper substrate 20. It is set to The electronic component built-in substrate 1 shown in FIG. 4B is smaller in size than the gap G1 of the electronic component built-in substrate 1 shown in FIG. 4A, the gap G2 between the lower substrate 10 and the upper substrate 20. Is set narrow. In the electronic component built-in substrate 1, the sealing resin 50 is not sufficiently filled between the semiconductor element 31 and the upper substrate 20, and a void (air bubble) B1 is generated on the lower surface of the upper substrate 20.

図４（ｃ）は、図３（ａ）に示すシート基板１００の一部を示す。なお、図４（ｃ）では、上基板２０を形成するワーク基板１２０を、ソルダーレジスト層１２５の側から示している。このワーク基板１２０と、図３（ｂ）に示す下基板１０を形成するワーク基板１１０との間に封止樹脂５０を形成する。封止樹脂５０は、封止金型内において、図４（ｃ）に示すワーク基板１２０の左型から注入される。このとき、図４（ｂ）に示す電子部品内蔵基板１と同様に、ボイドＢ１が発生する場合がある。ボイドＢ１は、上基板２０の下面、つまり排出溝２７に入り、注入される封止樹脂５０によって排出溝２７内を移動する。そして、ボイドＢ１は、切断領域Ａ２まで延びる排出溝２７の端部２７ｂに留まる。封止樹脂５０を硬化した後、この切断領域Ａ２を切断して上基板２０を含む電子部品内蔵基板１が個片化される。これにより、ボイドの残存が抑制された電子部品内蔵基板１が得られる。   FIG. 4C shows a part of the sheet substrate 100 shown in FIG. In FIG. 4C, the work substrate 120 on which the upper substrate 20 is to be formed is shown from the solder resist layer 125 side. The sealing resin 50 is formed between the work substrate 120 and the work substrate 110 forming the lower substrate 10 shown in FIG. The sealing resin 50 is injected from the left mold of the work substrate 120 shown in FIG. 4C in the sealing mold. At this time, as in the case of the electronic component built-in substrate 1 shown in FIG. 4B, the void B1 may occur. The void B1 enters the lower surface of the upper substrate 20, that is, the discharge groove 27, and moves in the discharge groove 27 by the injected sealing resin 50. Then, the void B1 remains at the end 27b of the discharge groove 27 extending to the cutting area A2. After the sealing resin 50 is cured, the cut area A2 is cut to separate the electronic component built-in substrate 1 including the upper substrate 20. Thereby, the electronic component built-in substrate 1 in which the remaining of the void is suppressed is obtained.

以上記述したように、本実施形態によれば、以下の効果を奏する。
（１）電子部品内蔵基板１は、下基板１０と上基板２０とを有している。下基板１０には半導体素子３１が実装されている。上基板２０は下基板１０の上方に配置され、基板接続部材４０により接続されている。下基板１０と上基板２０との間には、半導体素子３１と基板接続部材４０を封止する封止樹脂５０が形成されている。上基板２０は、基板本体２１と、基板本体２１の下面２１ｂに形成されたソルダーレジスト層２５とを有し、ソルダーレジスト層２５には、少なくとも半導体素子３１と対向する直上領域Ａ１から、上基板２０の側面２０ｄまで延びる排出溝２７が形成されている。 As described above, according to this embodiment, the following effects can be obtained.
(1) The electronic component built-in substrate 1 has the lower substrate 10 and the upper substrate 20. A semiconductor element 31 is mounted on the lower substrate 10. The upper substrate 20 is disposed above the lower substrate 10 and connected by the substrate connecting member 40. A sealing resin 50 for sealing the semiconductor element 31 and the substrate connecting member 40 is formed between the lower substrate 10 and the upper substrate 20. The upper substrate 20 has a substrate body 21 and a solder resist layer 25 formed on the lower surface 21b of the substrate body 21. The solder resist layer 25 includes at least a region directly above the semiconductor element 31 from the upper substrate A1. A discharge groove 27 extending to the side surface 20 d of 20 is formed.

この排出溝２７により、封止樹脂５０の形成時に生じるボイドＢ１は、注入される封止樹脂５０によって、半導体素子３１に対する直上領域Ａ１から上基板２０の側面２０ｄに向けて移動する。このため、ボイドＢ１の残存が抑制された電子部品内蔵基板１が得られる。ボイドＢ１は、近傍の樹脂の剥がれを生じさせ、信頼性を低下させる。これに対し、本実施形態の電子部品内蔵基板１は、ボイドＢ１の残存が抑制されるため、信頼性の低下を抑制できる。   The void B1 generated at the time of formation of the sealing resin 50 is moved from the region A1 directly above the semiconductor element 31 toward the side surface 20d of the upper substrate 20 by the discharging groove 27 due to the injected sealing resin 50. Therefore, the electronic component built-in substrate 1 in which the remaining of the void B1 is suppressed can be obtained. The void B1 causes the peeling of the resin in the vicinity and reduces the reliability. On the other hand, in the electronic component built-in substrate 1 of the present embodiment, since the remaining of the void B1 is suppressed, the decrease in reliability can be suppressed.

（２）複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１内の先端２７ａから側面２０ｄの端部２７ｂに向けて徐々に幅広となるように形成されている。従って、封止樹脂５０の形成工程において、複数のボイドＢ１が発生しても、端部２７ｂが幅広に形成されているため、その端部２７ｂに続く切断領域Ａ２に多くのボイドＢ１を収容することができる。このため、ボイドＢ１が電子部品内蔵基板１の中に残存し難くなる。   (2) The plurality of discharge grooves 27 are formed so as to gradually widen from the tip 27a in the directly over area A1 facing the semiconductor element 31 to the end 27b of the side surface 20d. Therefore, even if a plurality of voids B1 are generated in the step of forming the sealing resin 50, the end 27b is formed wide, so that many voids B1 are accommodated in the cutting area A2 following the end 27b. be able to. As a result, the void B1 is less likely to remain in the electronic component built-in substrate 1.

（３）複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１に多くの排出溝２７を配置するように、側面２０ｄに向けて広がる放射状に形成されている。これにより、半導体素子３１に対する直上領域Ａ１に多くの排出溝２７を形成することができ、よりボイドＢ１を排出し易くなる。   (3) The plurality of discharge grooves 27 are radially formed so as to spread toward the side surface 20 d such that many discharge grooves 27 are disposed in the area A <b> 1 directly above the semiconductor element 31. As a result, many discharge grooves 27 can be formed in the area A1 immediately above the semiconductor element 31, and the void B1 can be more easily discharged.

（変形例）
尚、上記各実施形態は、以下の態様で実施してもよい。
・上記実施形態に対し、上基板２０の構成や、排出溝２７の本数、形状、等を適宜変更してもよい。 (Modification)
The above embodiments may be implemented in the following manner.
The configuration of the upper substrate 20, the number of the discharge grooves 27, the shape, and the like of the above embodiment may be changed as appropriate.

図５は変形例の上基板３００を示し、図６は、図５の上基板３００を形成するワーク基板３１０の一部を示す。上基板３００のソルダーレジスト層３０１には、４つの排出溝３０２が形成されている。各排出溝３０２は、直上領域Ａ１から側面３００ｄまで延び、互いに平行に形成されている。   FIG. 5 shows an upper substrate 300 of a modification, and FIG. 6 shows a part of a work substrate 310 forming the upper substrate 300 of FIG. In the solder resist layer 301 of the upper substrate 300, four discharge grooves 302 are formed. The respective discharge grooves 302 extend from the directly over area A1 to the side surface 300d, and are formed in parallel with each other.

図７に示すように、上基板３２０のソルダーレジスト層３２１には、５つの排出溝３２２が形成されている。これらの排出溝３２２は、上記実施形態と同様に、直上領域Ａ１から側面３２０ｄに向って放射状に形成されている。また、各排出溝３２２は、全体に亘って同一幅にて形成されている。   As shown in FIG. 7, five discharge grooves 322 are formed in the solder resist layer 321 of the upper substrate 320. The discharge grooves 322 are formed radially from the directly above area A1 to the side surface 320d, as in the above embodiment. Moreover, each discharge groove 322 is formed with the same width over the whole.

図８に示すように、上基板３３０のソルダーレジスト層３３１には、４つの排出溝３３２が形成されている。各排出溝３３２は、また、直上領域Ａ１から側面３３０ｄまで延び、互いに平行に形成されている。また、各排出溝３３２は、全体に亘って同一幅にて形成されている。   As shown in FIG. 8, four discharge grooves 332 are formed in the solder resist layer 331 of the upper substrate 330. The respective discharge grooves 332 also extend from the directly over area A1 to the side surface 330d, and are formed in parallel with each other. Further, each discharge groove 332 is formed to have the same width throughout.

図９に示すように、上基板３４０のソルダーレジスト層３４１には、４つの排出溝３４２が形成されている。各排出溝３４２は、直上領域Ａ１を通り、一対の側面３４０ｃ，３４０ｄの一方の側面３４０ｃから他方の側面３４０ｄまで延び、互いに平行に形成されている。また、各排出溝３４２は、全体に亘って同一幅にて形成されている。   As shown in FIG. 9, four discharge grooves 342 are formed in the solder resist layer 341 of the upper substrate 340. The respective discharge grooves 342 pass through the directly above area A1, extend from one side surface 340c of the pair of side surfaces 340c and 340d to the other side surface 340d, and are formed in parallel to each other. Further, each discharge groove 342 is formed to have the same width throughout.

図１０は、図９の上基板３４０を形成するワーク基板３５０の一部を示す。このワーク基板３５０において、排出溝３４２は、上基板３４０を通過して、側面３４０ｃ（上基板３４０となる領域の辺）の側の切断領域Ａ２から、側面３４０ｄの側の切断領域Ａ２まで延びるように形成されている。さらに、複数の上基板３４０に対して、排出溝３４２が連続するように形成されている。   FIG. 10 shows a portion of a work substrate 350 forming the upper substrate 340 of FIG. In the work substrate 350, the discharge groove 342 passes from the upper substrate 340 and extends from the cutting region A2 on the side of the side surface 340c (the side of the region to be the upper substrate 340) to the cutting region A2 on the side of the side surface 340d. Is formed. Furthermore, the discharge grooves 342 are formed to be continuous with the plurality of upper substrates 340.

図１１は、変形例のワーク基板３６０を示す。このワーク基板３６０は、図１（ａ）に示す上基板２０を形成するために用いられる。このワーク基板３６０のソルダーレジスト層３６１には、上基板２０の周囲の切断領域Ａ２に、環状の溝部３６２が形成されている。溝部３６２は、各上基板２０の排出溝２７と連続するように形成されている。   FIG. 11 shows a work substrate 360 of a modification. The work substrate 360 is used to form the upper substrate 20 shown in FIG. In the solder resist layer 361 of the work substrate 360, an annular groove 362 is formed in the cutting area A2 around the upper substrate 20. The groove 362 is formed to be continuous with the discharge groove 27 of each upper substrate 20.

ソルダーレジスト層を複数の層構造とし、複数層の一部に排出溝を形成してもよい。一例を図１２に示す。
図１２に示すように、上基板３７０のソルダーレジスト層３７１は、基板本体２１の下面２１ｂと配線層２４の一部を覆う第１レジスト層３７２と、第１レジスト層３７２の一部を覆う第２レジスト層３７３を有している。第２レジスト層３７３には、第１レジスト層３７２の開口部３７２Ｘにより露出された接続パッド２６を露出する開口部３７３Ｘと、第１レジスト層３７２の下面３７２ｂの一部を露出するように形成された排出溝３７４とを有している。 The solder resist layer may have a plurality of layer structures, and discharge grooves may be formed in part of the plurality of layers. An example is shown in FIG.
As shown in FIG. 12, the solder resist layer 371 of the upper substrate 370 is a first resist layer 372 covering a portion of the lower surface 21 b of the substrate body 21 and the wiring layer 24, and a portion covering the first resist layer 372. 2 has a resist layer 373. The second resist layer 373 is formed to expose an opening 373 X for exposing the connection pad 26 exposed by the opening 372 X of the first resist layer 372 and a part of the lower surface 372 b of the first resist layer 372. And a discharge groove 374.

・上記実施形態では、シート基板１００に複数の電子部品内蔵基板１をマトリックス状に形成したが、一列状に電子部品内蔵基板１を形成したシート基板としてもよい。
・接続パッド２６は上記実施形態の形状に限定されず、例えば、四角形状、つまり開口部２５Ｘの形状を四角形状としてもよい。 In the above embodiment, the plurality of electronic component built-in substrates 1 are formed in a matrix on the sheet substrate 100, but may be a sheet substrate in which the electronic component built-in substrates 1 are formed in one line.
-The connection pad 26 is not limited to the shape of the said embodiment, For example, it is good also as quadrilateral shape, ie, the shape of the opening part 25X, may be made into square shape.

・接続パッド２６の配列は上記実施形態に限定されず、例えば、ソルダーレジスト層２５に複数列の開口部２５Ｘを形成し、複数列の接続パッド２６を形成してもよい。また、半導体素子３１を囲むように開口部２５Ｘを形成して接続パッド２６を配列してもよい。   The arrangement of the connection pads 26 is not limited to the above embodiment. For example, a plurality of rows of openings 25X may be formed in the solder resist layer 25, and a plurality of rows of connection pads 26 may be formed. Alternatively, the connection pad 26 may be arranged by forming the opening 25X so as to surround the semiconductor element 31.

１０ 下基板
２０ 上基板
２１ 基板本体
２５ ソルダーレジスト層
２７ 排出溝（溝）
３１ 半導体素子（電子部品）
４０ 基板接続部材
１００ シート基板
１１０、１２０ ワーク基板
Ａ１ 直上領域
Ａ２ 切断領域 10 lower substrate 20 upper substrate 21 substrate main body 25 solder resist layer 27 discharge groove (groove)
31 Semiconductor devices (electronic parts)
40 board connecting member 100 sheet board 110, 120 work board A1 directly above area A2 cutting area

Claims (7)

下基板と、
前記下基板上に実装された電子部品と、
前記電子部品及び前記下基板の上方に設けられた上基板と、
前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、
前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、
を有し、
前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、
前記ソルダーレジスト層には、少なくとも前記電子部品と対向する直上領域から、前記上基板の側面まで延びる溝が形成されていること、
を特徴とする電子部品内蔵基板。 Lower substrate,
An electronic component mounted on the lower substrate;
An upper substrate provided above the electronic component and the lower substrate;
A substrate connecting member provided between the lower substrate and the upper substrate and connecting the lower substrate and the upper substrate;
A sealing resin filled between the lower substrate and the upper substrate and sealing the electronic component and the substrate connecting member;
Have
The upper substrate has a substrate body and a solder resist layer formed on the lower surface of the substrate body,
In the solder resist layer, a groove extending from at least a region directly opposite to the electronic component to a side surface of the upper substrate is formed.
Electronic component built-in substrate characterized by 前記上基板は、互いに対向する２対の第１の側面対及び第２の側面対を有し、
前記基板接続部材は、前記第１の側面対に沿って配列され、
前記溝は、前記第２の側面対のうちの一方の側面まで延びるように形成されていること、
を特徴とする請求項１に記載の電子部品内蔵基板。 The upper substrate has two pairs of first side pairs and second side pairs facing each other,
The substrate connecting members are arranged along the first pair of side surfaces,
The groove is formed to extend to one side of the second side pair,
An electronic component built-in substrate according to claim 1, characterized in that 前記溝は、前記直上領域内の先端から前記側面に向けて徐々に幅広となるように形成されていること、を特徴とする請求項１又は２に記載の電子部品内蔵基板。   3. The electronic component built-in substrate according to claim 1, wherein the groove is formed so as to gradually widen from the end in the region directly above to the side surface. 前記溝は、前記直上領域内の先端から前記側面まで等しい幅にて形成されていること、を特徴とする請求項１又は２に記載の電子部品内蔵基板。   3. The electronic component built-in substrate according to claim 1, wherein the groove is formed with an equal width from the tip end in the region directly above to the side surface. 前記ソルダーレジスト層には、複数の前記溝が形成され、複数の前記溝の互いの間隔が前記側面に向って徐々に広くなるように設定されていること、を特徴とする請求項１〜４のいずれか１項に記載の電子部品内蔵基板。   5. The plurality of grooves are formed in the solder resist layer, and the distance between the plurality of grooves is set to gradually widen toward the side surface. The electronic component built-in substrate according to any one of the above. 前記上基板は、互いに対向する２対の第１の側面対及び第２の側面対を有し、
前記基板接続部材は、前記第１の側面対に沿って配列され、
前記溝は、前記第２の側面対の内の一方の側面から、前記直上領域を通過し、前記第２の側面対の他方の側面まで延びるように形成されていること、
を特徴とする請求項１に記載の電子部品内蔵基板。 The upper substrate has two pairs of first side pairs and second side pairs facing each other,
The substrate connecting members are arranged along the first pair of side surfaces,
The groove is formed to extend from one side surface of the second pair of side surfaces, through the area immediately above, and to the other side surface of the second pair of side surfaces.
An electronic component built-in substrate according to claim 1, characterized in that 複数の電子部品内蔵基板と、
隣接する２つの前記電子部品内蔵基板の間に設定された切断領域と、
を有し、
前記電子部品内蔵基板は、
下基板と、
前記下基板上に実装された電子部品と、
前記電子部品及び前記下基板の上方に設けられた上基板と、
前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、
前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、
を有し、
前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、
前記ソルダーレジスト層には、少なくとも前記電子部品と対向する直上領域から、前記切断領域まで延びる溝が形成されていること、
を特徴とするシート基板。 Multiple electronic component built-in boards,
A cutting area set between two adjacent electronic component built-in substrates;
Have
The electronic component built-in substrate is
Lower substrate,
An electronic component mounted on the lower substrate;
An upper substrate provided above the electronic component and the lower substrate;
A substrate connecting member provided between the lower substrate and the upper substrate and connecting the lower substrate and the upper substrate;
A sealing resin filled between the lower substrate and the upper substrate and sealing the electronic component and the substrate connecting member;
Have
The upper substrate has a substrate body and a solder resist layer formed on the lower surface of the substrate body,
The solder resist layer is formed with a groove extending from at least a region directly opposite to the electronic component to the cutting region;
Sheet substrate characterized by
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