JP2019068052A - リングインリング構成可能キャパシタンス・スティフナ及びその組立て方法 - Google Patents
リングインリング構成可能キャパシタンス・スティフナ及びその組立て方法 Download PDFInfo
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- JP2019068052A JP2019068052A JP2018154711A JP2018154711A JP2019068052A JP 2019068052 A JP2019068052 A JP 2019068052A JP 2018154711 A JP2018154711 A JP 2018154711A JP 2018154711 A JP2018154711 A JP 2018154711A JP 2019068052 A JP2019068052 A JP 2019068052A
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
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Abstract
Description
Claims (23)
- ダイ側及びランド側を含むパッケージ基板と;
内側リング・スティフナ及び該内側リング・スティフナに隣接して配置される後続リング・スティフナであって、各リング・スティフナが、導電性接着剤を用いて前記ダイ側に載置され、少なくとも1つの導電性接着剤が前記パッケージ基板内のトレースに結合される、前記内側リング・スティフナ及び前記後続リング・スティフナと;
前記内側リング・スティフナ及び前記後続リング・スティフナに電気的に接触する受動デバイスであって、前記後続リング・スティフナが接地に結合され、前記内側リング・スティフナが電力接続に結合される、前記受動デバイスと;
を備える、半導体パッケージ。 - 前記受動デバイスは第1受動デバイスであり、
前記内側リング・スティフナ及び前記後続リング・スティフナと電気的に接触する少なくとも1つの更なる受動デバイスを更に含む、
請求項1に記載の半導体パッケージ。 - 前記ダイ側に配置される第1ダイを更に含み、該第1ダイは、前記トレースを通して前記後続リング・スティフナに結合される、
請求項1に記載の半導体パッケージ。 - 前記トレースは第1トレースであり、
前記ダイ側に配置される第1ダイであって、前記第1トレースを通して前記後続リング・スティフナに結合される前記第1ダイと;
前記ダイ側に配置される補助ダイであって、補助トレースを通して前記後続リング・スティフナに結合される前記補助ダイと;
を更に含む、請求項1に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング構造であり、前記内側リング・スティフナは、集合的にリング・スティフナの輪郭を描く2つのリングセグメント・スティフナを含む、
請求項1に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング・スティフナであり、
集合的にリング・スティフナの輪郭を描く少なくとも2つの外側リングセグメント・スティフナを備える、外側リングセグメント・スティフナを更に含む、
請求項1に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング構造であり、
前記内側リング・スティフナは、集合的にリング・スティフナの輪郭を描く2つのリングセグメント・スティフナを備え、
前記後続リング・スティフナを囲むリング・スティフナの輪郭を集合的に描く少なくとも2つの外側リングセグメント・スティフナを備える、外側リングセグメント・スティフナを更に含む、
請求項1に記載の半導体パッケージ。 - 前記受動デバイスは内側受動デバイスであり、
外側リング・スティフナであって、前記後続リング・スティフナが前記内側リング・スティフナと当該外側リング・スティフナとの間のダイ側に配置される、前記外側リング・スティフナと;
前記外側リング・スティフナ及び前記後続リング・スティフナに電気的に接触する少なくとも1つの外側受動デバイスであって、前記外側リング・スティフナが電力接続に結合される、前記少なくとも1つの外側受動デバイスと;
を更に含む、請求項1に記載の半導体パッケージ。 - 前記内側受動デバイスは第1内側受動デバイスであり、
前記内側リング・スティフナ及び前記後続リング・スティフナに電気的に接触する少なくとも1つの更なる内側受動デバイスを更に含み、
前記外側受動デバイスは、第1外側受動デバイスであり、
前記後続リング・スティフナ及び前記外側リング・スティフナに接触する少なくとも1つの更なる外側受動デバイスを更に含む、
請求項8に記載の半導体パッケージ。 - 前記ダイ側に配置される第1ダイを更に含み、前記第1ダイは、前記トレースを通して前記後続リング・スティフナに結合される、
請求項8に記載の半導体パッケージ。 - 前記トレースは第1トレースであり、
前記ダイ側に配置される第1ダイであって、前記第1トレースを通して前記後続リング・スティフナに結合される前記第1ダイと;
前記ダイ側に配置される補助ダイであって、補助トレースを通して前記後続リング・スティフナに結合される前記補助ダイと;
を更に含む、請求項8に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング構造であり、前記内側リング・スティフナは、集合的にリング・スティフナの輪郭を描く2つのリングセグメント・スティフナを備える、
請求項8に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング・スティフナであり、
集合的にリング・スティフナの輪郭を描く少なくとも2つの外側リングセグメント・スティフナを備える、外側リングセグメント・スティフナを更に含む、
請求項8に記載の半導体パッケージ。 - 前記後続リング・スティフナは一体型リング構造であり、
前記内側リング・スティフナは、集合的にリング・スティフナの輪郭を描く2つのリングセグメント・スティフナを備え、
前記後続リング・スティフナを囲むリング・スティフナの輪郭を集合的に描く少なくとも2つの外側リングセグメント・スティフナを備える、外側リングセグメント・スティフナを更に含む、
請求項8に記載の半導体パッケージ。 - 前記ランド側に配置されるボールグリッドアレイと;
前記ボールグリッドアレイが接触するボードであって、プリント配線基板である前記ボードと;
を更に含む、請求項1に記載の半導体パッケージ。 - 前記受動デバイスは、200μm〜500μmの範囲の長さ、400μm〜1,000μmの範囲の幅及び150μm〜250μmの範囲の高さのキャパシタである、
請求項1に記載の半導体パッケージ。 - スティフナを半導体パッケージ基板に組み立てる方法であって:
半導体パッケージ基板のダイ側に内側リング・スティフナ及び後続リング・スティフナを載置することであって、前記半導体パッケージ基板はランド側も含むことと;
受動デバイスの載置を達成するために前記内側リング・スティフナ及び前記後続リング・スティフナの各々にトレンチを形成することと;
前記内側リング・スティフナと前記後続リング・スティフナとの間の前記受動デバイスの載置において電気的接続を形成することと;
前記のリング・スティフナの間の電気的接続に対して受動デバイスを組み立てることと;
を備える、方法。 - 前記内側リング・スティフナは、2つ以上の内側リングセグメント・スティフナから組み立てられ、前記受動デバイスは第1内側受動デバイスであり、
前記後続リング・スティフナ及び異なる内側リングセグメント・スティフナに対して後続の内側受動デバイスを組み立てることを更に含む、
請求項17に記載の方法。 - 前記受動デバイスは、内側受動デバイスであり、
外側リング・スティフナを前記ダイ側に前記後続リング・スティフナに隣接して載置することと;
受動デバイスの載置を達成するために、前記後続リング・スティフナ及び前記外側リング・スティフナの各々にトレンチを形成することと;
前記後続リング・スティフナと前記外側リング・スティフナとの間の前記受動デバイスの載置において電気的接続を形成することと;
前記後続リング・スティフナと前記外側リング・スティフナとの間の前記電気的接続に対して外側受動デバイスを組み立てることと;
を更に含む、請求項17に記載の方法。 - 外側リング・スティフナは、2つ以上の外側リングセグメント・スティフナから組み立てられ、外側受動デバイスは、第1外側受動デバイスであり、
前記後続リング・スティフナ及び異なる外側リングセグメント・スティフナに対して後続の外側受動デバイスを組み立てることを更に含む、
を更に含む、請求項17に記載の方法。 - コンピューティングシステムであって:
半導体パッケージ基板のダイ側に載置される第1ダイ及び補助ダイであって、前記半導体パッケージ基板がランド側も含む、前記第1ダイ及び前記補助ダイと;
内側リング・スティフナ及び該内側リング・スティフナに隣接して配置される後続リング・スティフナであって、各リング・スティフナが、導電性接着剤を用いて前記ダイ側に載置され、少なくとも1つの導電性接着剤が前記のパッケージ基板内のトレースに結合される、前記内側リング・スティフナ及び前記後続リング・スティフナと;
前記内側リング・スティフナ及び前記後続リング・スティフナに電気的に接触する受動デバイスであって、前記後続リング・スティフナが接地に結合され、前記内側リング・スティフナが電力接続に結合される、前記受動デバイスと;
前記ランド側に配置されるボールグリッドアレイと;
前記ボールグリッドアレイに電気的に接触するボードであって、前記第1ダイ及び前記補助ダイのために電気的及び物理的に絶縁性の外側のシェルを含む前記ボードと;
を備える、コンピューティングシステム。 - 前記補助ダイは、少なくとも1つの貫通シリコンビアによって前記補助ダイに各々結合される第1積層化補助ダイと後続積層化補助ダイを支持し、前記第1ダイ及び前記補助ダイの各々は、ボールアレイを通して前記半導体パッケージ基板と通信する、
請求項21に記載のコンピューティングシステム。 - 前記ダイ側に配置されるメモリダイ積層を更に含み、該メモリダイ積層は、少なくとも1つのTSVを通して前記半導体パッケージ基板と通信する少なくとも2つのメモリダイを有するチップセットを含む、
請求項22に記載のコンピューティングシステム。
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