JP2018530176A - Spadアレイ構造及び動作方法 - Google Patents
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Abstract
Description
本出願は、その内容がその全体で参照により本明細書に組み込まれる、2015年7月8日に出願され、“SPAD ARRAY STRUCTURES AND METHODS OF OPERATION”(SPADアレイ構造及び動作方法)という題名の、オーストラリア仮特許出願第2015902699号の優先権を主張する。
複数(n個)のSPAD構造と、
各消滅回路がSPAD構造のうちの1つに接続される、複数(n個)の消滅回路と、
SPAD構造の各々に接続された共通トリガ回路であって、
カウンタ、
メモリ、
各々がSPAD構造に接続される複数(n個)のラッチ、及び複数のラッチに接続されて、ラッチの全てがトリガされる場合にカウンタを停止するように構成される論理回路、
複数(n個)の入力を有するパルスラッチ及び書込み回路であって、各入力が、SPAD構造に接続され、SPAD構造からの出力パルスを検出するように構成され、出力パルスが検出される度に、出力パルスが検出されたSPAD構造のSPAD IDがメモリに提供され、カウンタの値が読み出されて、SPAD IDと一緒にメモリに記憶される、パルスラッチ及び書込み回路
をさらに備える共通トリガ回路と
を備える。
セル中のカウンタを開始するステップと、
セル中の複数のSPAD構造のうちの1つからの各出力パルスを検出するステップと、
最初のn−1個の検出された出力パルスについて、カウンタの値を取り込み、出力パルスが検出されたSPAD構造のSPAD IDと一緒にメモリにカウンタ値を記憶するステップと、
n番目に検出された出力パルスについて、カウンタを停止する、又はカウンタの値を取り込み、出力パルスが検出されたSPAD構造のSPAD IDと一緒にメモリにカウンタ値を記憶するステップと、
各記憶されたカウンタ値及び関連するSPAD IDをメモリから読み出し、n番目に検出された出力パルスによりカウンタが停止された場合に現在のカウンタ値を読み出すステップと
を含む。
Claims (21)
- 複数の単一光子アバランシェダイオード(SPAD)セルを備えるSPADアレイであって、各SPADセルが、
複数(n個)のSPAD構造と、
各消滅回路が前記SPAD構造のうちの1つに接続される、複数(n個)の消滅回路と、
前記SPAD構造の各々に接続された共通トリガ回路であって、
カウンタ、
メモリ、
各々が前記SPAD構造に接続される複数(n個)のラッチ、及び前記複数のラッチに接続されて、前記ラッチの全てがトリガされる場合に前記カウンタを停止するように構成される論理回路、
複数(n個)の入力を有するパルスラッチ及び書込み回路であって、各入力が、前記SPAD構造に接続され、前記SPAD構造からの出力パルスを検出するように構成され、前記出力パルスが検出される度に、前記出力パルスが検出された前記SPAD構造のSPAD IDが前記メモリに提供され、前記カウンタの値が読み出されて、前記SPAD IDと一緒に前記メモリに記憶される、前記パルスラッチ及び書込み回路
をさらに備える前記共通トリガ回路と
を備える、前記SPADアレイ。 - カウンタが、少なくとも16ビットカウンタである、請求項1に記載のSPADアレイ。
- メモリがn−1個の値を記憶するように構成され、各値が、少なくとも、カウンタのビットサイズに、n−1を表すのに必要なビットの数を加えたビットサイズを有する、請求項1又は2に記載のSPADアレイ。
- n=2である、請求項1〜3のいずれかに記載のSPADアレイ。
- アレイが、少なくとも128×128のセルアレイである、請求項1〜4のいずれかに記載のSPADアレイ。
- 各SPAD構造が、少なくとも1つのアノード及び活性領域を備えるPウェル領域と、Pドリフト領域と、少なくとも1つのカソードを備えるNウェル領域とを備え、前記Pドリフト領域が前記Pウェル領域とオーバーラップする、請求項1〜5のいずれかに記載のSPADアレイ。
- 各SPAD構造において、Pウェル領域がSPADの上面からNウェル領域へと延在する円形ディスク領域であり、Pドリフト領域が、前記Pウェル領域の厚みよりも厚い厚みを有し、前記Pウェル領域から径方向に延在し、前記Pウェル領域の下で前記Nウェル領域の中へと延在してオーバーラップ領域を画定する環状領域である、請求項6に記載のSPADアレイ。
- 各SPAD構造において、オーバーラップ領域の幅と活性領域の直径の比が、0.05〜0.25の範囲にある、請求項6に記載のSPADアレイ。
- 各SPAD構造が、少なくとも1つのアノードを備えるPウェル領域と、活性領域と、打ち込み領域中のPドリフト領域と、少なくとも1つのカソードを備えるNウェル領域とを備え、前記SPADの前記活性領域の上面が露出し、前記Nウェル領域の上面が1又は2以上のシャロートレンチアイソレーション(STI)領域で覆われ、ポリシリコンゲート(ポリ)領域が、前記露出した活性領域から離れた前記打ち込み領域の上面を覆って配置され、1又は2以上のSTI領域を前記打ち込み領域から分離するために前記Nウェル領域の前記上面の部分を覆って延在する、請求項1〜8のいずれかに記載のSPADアレイ。
- 各SPAD構造において、ポリシリコンゲートが、Pウェル領域と同じ電位に保持される、請求項9に記載のSPADアレイ。
- 単一光子アバランシェダイオード(SPAD)アレイのセル中の、複数(n個)のSPAD構造の1又は2以上のトリガ時間を記録するための方法であって、
セル中のカウンタを開始するステップと、
前記セル中の前記複数のSPAD構造のうちの1つからの各出力パルスを検出するステップと、
最初のn−1個の検出された出力パルスについて、前記カウンタの値を取り込み、前記出力パルスが検出された前記SPAD構造のSPAD IDと一緒にメモリに前記カウンタ値を記憶するステップと、
n番目に検出された出力パルスについて、前記カウンタを停止する、又は前記カウンタの値を取り込み、前記出力パルスが検出された前記SPAD構造のSPAD IDと一緒に前記メモリに前記カウンタ値を記憶するステップと、
各記憶されたカウンタ値及び関連するSPAD IDを前記メモリから読み出し、前記n番目に検出された前記出力パルスにより前記カウンタが停止された場合に現在のカウンタ値を読み出すステップと
を含む、前記方法。 - n番目に検出された出力パルスについて、カウンタが停止される、請求項11に記載の方法。
- 複数のSPAD構造のうちの1つからの各々の検出される出力パルスの後に、前記出力パルスを生成したSPADが再度バイアスをかけられ、n番目及びそれ以降の各々の検出される出力パルスについて、カウンタの値が取り込まれて、前記カウンタ値が、前記出力パルスが検出された前記SPAD構造のSPAD IDと一緒にメモリに記憶される、請求項11に記載の方法。
- カウンタがまだ停止されていない場合に、読み出すステップの前又は前記読み出すステップと同時に前記カウンタを停止し、前記読み出すステップ後に前記カウンタ及びメモリをリセットするステップをさらに含む、請求項11〜13のいずれかに記載の方法。
- カウンタが、少なくとも16ビットカウンタである、請求項11〜14のいずれかに記載の方法。
- セル中のSPAD構造の数が2である、請求項11〜15のいずれかに記載の方法。
- 少なくとも1つのアノード及び活性領域を備えるPウェル領域と、Pドリフト領域と、少なくとも1つのカソードを備えるNウェル領域とを備え、前記Pドリフト領域が前記Pウェル領域とオーバーラップする、SPAD構造。
- Pウェル領域が、SPADの上面からNウェル領域へと延在する円形ディスク領域であり、Pドリフト領域が、前記Pウェル領域の厚みよりも厚い厚みを有し、前記Pウェル領域から径方向に延在し、前記Pウェル領域の下で前記Nウェル領域の中へと延在してオーバーラップ領域を画定する環状領域である、請求項17に記載のSPAD構造。
- オーバーラップ領域の幅と活性領域の直径の比が、0.05〜0.25の範囲にある、請求項17又は18に記載のSPAD構造。
- 少なくとも1つのアノードを備えるPウェル領域と、活性領域と、打ち込み領域中のPドリフト領域と、少なくとも1つのカソードを備えるNウェル領域とを備えるSPAD構造であって、前記SPADの前記活性領域の上面が露出し、前記Nウェル領域の上面が1又は2以上のシャロートレンチアイソレーション(STI)領域で覆われ、ポリシリコンゲート(ポリ)領域が、前記露出した活性領域から離れた前記打ち込み領域の上面を覆って配置され、1又は2以上のSTI領域を前記打ち込み領域から分離するために前記Nウェル領域の前記上面の部分を覆って延在する、前記SPAD構造。
- ポリシリコンゲートが、Pウェル領域と同じ電位に保持される、請求項20に記載のSPAD構造。
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PCT/AU2016/000247 WO2017004663A1 (en) | 2015-07-08 | 2016-07-08 | Spad array structures and methods of operation |
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JP2020141012A (ja) * | 2019-02-27 | 2020-09-03 | キヤノン株式会社 | 光電変換装置、光電変換システム、及び移動体 |
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KR20180027527A (ko) | 2018-03-14 |
US20180195900A1 (en) | 2018-07-12 |
JP6789251B2 (ja) | 2020-11-25 |
NZ738738A (en) | 2021-08-27 |
KR102039963B1 (ko) | 2019-11-04 |
AU2016290889A1 (en) | 2018-01-25 |
CA2990466A1 (en) | 2017-01-12 |
EP3320559A1 (en) | 2018-05-16 |
US10697829B2 (en) | 2020-06-30 |
EP3320559A4 (en) | 2019-01-30 |
EP3320559B1 (en) | 2021-03-03 |
MY193971A (en) | 2022-11-04 |
CA2990466C (en) | 2023-07-11 |
AU2016290889B2 (en) | 2021-03-04 |
WO2017004663A1 (en) | 2017-01-12 |
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