JP2018200987A - Semiconductor device housing package and semiconductor device - Google Patents

Semiconductor device housing package and semiconductor device Download PDF

Info

Publication number
JP2018200987A
JP2018200987A JP2017105813A JP2017105813A JP2018200987A JP 2018200987 A JP2018200987 A JP 2018200987A JP 2017105813 A JP2017105813 A JP 2017105813A JP 2017105813 A JP2017105813 A JP 2017105813A JP 2018200987 A JP2018200987 A JP 2018200987A
Authority
JP
Japan
Prior art keywords
wiring conductor
wiring
semiconductor element
package
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017105813A
Other languages
Japanese (ja)
Other versions
JP7038492B2 (en
Inventor
泰人 木村
Yasuto Kimura
泰人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2017105813A priority Critical patent/JP7038492B2/en
Publication of JP2018200987A publication Critical patent/JP2018200987A/en
Application granted granted Critical
Publication of JP7038492B2 publication Critical patent/JP7038492B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

To provide a semiconductor device housing package or the like effective for improving transmission characteristics.SOLUTION: A semiconductor device housing package includes an insulating substrate including a plurality of insulating layers laminated to each other and a wiring conductor positioned between the insulating layers and having an input portion at a part in the longitudinal direction and an output portion at a position distant from the input portion, and the wiring conductor has a non-formed portion along the length direction at a center portion in a width direction orthogonal to the length direction between the input portion and the output portion.SELECTED DRAWING: Figure 2

Description

本発明は、配線導体を有する半導体素子収納用パッケージおよび半導体装置に関する。   The present invention relates to a package for housing a semiconductor element having a wiring conductor and a semiconductor device.

半導体集積回路素子等の半導体素子を含む半導体装置を構成する部品として、半導体素子と電気的に接続される配線導体を含む半導体素子収納用パッケージが用いられている。半導体素子収納用パッケージは、複数の絶縁層が積層されてなる絶縁体と、絶縁体の内部等に配置された上記配線導体等の導体とを含んでいる（例えば、特許文献１〜３を参照）。   As a component constituting a semiconductor device including a semiconductor element such as a semiconductor integrated circuit element, a package for housing a semiconductor element including a wiring conductor electrically connected to the semiconductor element is used. The package for housing a semiconductor element includes an insulator in which a plurality of insulating layers are stacked, and a conductor such as the wiring conductor disposed inside the insulator (see, for example, Patent Documents 1 to 3). ).

特開平９−237854号公報Japanese Patent Laid-Open No. 9-237854 特開2002−324867号公報JP 2002-324867 A 特開2002−324868号公報JP 2002-324868

近年、高速化および低消費電力化等のために、線路導体等の導体における導通抵抗の低減が求められている。これに対して、導体を流れる電流の流れ方向において、導体の厚みを大きくすること、または導体の平面視における面積（線幅）を大きくすることが考えられる。   In recent years, reduction of conduction resistance in conductors such as line conductors has been demanded in order to increase speed and reduce power consumption. On the other hand, it is conceivable to increase the thickness of the conductor or increase the area (line width) in plan view of the conductor in the direction of current flow through the conductor.

しかしながら、導体の厚みまたは平面視における面積を大きくすると、導体と絶縁体との熱膨張率（線膨張係数等）の差に起因した熱応力による、導体または導体と絶縁体との界面部分における機械的な破壊の可能性が大きくなる。   However, when the thickness of the conductor or the area in plan view is increased, the machine at the interface portion between the conductor or the conductor and the insulator due to the thermal stress caused by the difference in the coefficient of thermal expansion (such as the linear expansion coefficient) between the conductor and the insulator. The possibility of destructive increases.

本発明の実施形態の半導体素子収納用パッケージは、互いに積層された複数の絶縁層を含む絶縁基板と、前記絶縁層の層間に位置しており、長さ方向の一部に入力部を有するとともに該入力部から離れた位置に出力部を有する配線導体とを備えており、該配線導体が、前記入力部と前記出力部との間において、前記長さ方向に直交する幅方向の中央部分に、前記長さ方向に沿った非形成部を有している。   A package for housing a semiconductor device according to an embodiment of the present invention is located between an insulating substrate including a plurality of insulating layers stacked on each other and the insulating layer, and has an input portion in a part in the length direction. A wiring conductor having an output part at a position away from the input part, and the wiring conductor is provided between the input part and the output part at a central part in the width direction orthogonal to the length direction. And a non-forming portion along the length direction.

本発明の実施形態の半導体装置は、上記構成の半導体素子収納用パッケージと、前記搭載部に搭載され、前記配線導体と電気的に接続された半導体素子とを有している。   A semiconductor device according to an embodiment of the present invention includes a semiconductor element housing package having the above-described configuration and a semiconductor element mounted on the mounting portion and electrically connected to the wiring conductor.

本発明の１つの態様の半導体素子収納用パッケージによれば、上記構成であることから、絶縁層の層間において配線導体の非形成部では熱応力が効果的に低減される。すなわち、配線導体と絶縁基板との間に生じる熱応力は、非形成部によって分散される。したがって、例えば配線導体の厚みを従来よりも大きくすること等による導通抵抗の低減と、熱応力による配線導体等の機械的な破壊の可能性の低減とが可能な、半導体素子収納用パッケージを提供することができる。   According to the package for housing a semiconductor element of one aspect of the present invention, because of the above configuration, thermal stress is effectively reduced in the portion where the wiring conductor is not formed between the insulating layers. That is, the thermal stress generated between the wiring conductor and the insulating substrate is dispersed by the non-forming portion. Therefore, for example, a package for housing a semiconductor element is provided that can reduce conduction resistance by increasing the thickness of the wiring conductor, for example, and reducing the possibility of mechanical destruction of the wiring conductor due to thermal stress. can do.

また、本発明の１つの態様の半導体装置によれば、上記構成の半導体素子収納用パッケージを含んでいることから、配線導体等の機械的な破壊の可能性が低減された、長期信頼
性の向上に有効な半導体装置を提供することができる。 In addition, according to the semiconductor device of one aspect of the present invention, since the semiconductor element housing package having the above-described configuration is included, the possibility of mechanical destruction of the wiring conductor or the like is reduced, and long-term reliability is achieved. A semiconductor device effective for improvement can be provided.

本発明の実施形態の半導体素子収納用パッケージおよび半導体装置を示す斜視図である。1 is a perspective view showing a semiconductor element storage package and a semiconductor device according to an embodiment of the present invention. 本発明の実施形態の半導体素子収納用パッケージを分解して示す分解斜視図である。It is a disassembled perspective view which decomposes | disassembles and shows the package for semiconductor element accommodation of embodiment of this invention. 本発明の実施形態の半導体素子収納用パッケージにおける配線導体の一例を示す斜視図である。It is a perspective view which shows an example of the wiring conductor in the package for semiconductor element accommodation of embodiment of this invention. 本発明の実施形態の半導体素子収納用パッケージにおける入力部および出力部を示す斜視図である。It is a perspective view which shows the input part and output part in the package for semiconductor element accommodation of embodiment of this invention. （ａ）および（ｂ）は、それぞれ、本発明の他の実施形態の半導体素子収納用パッケージにおける配線導体の一例を示す平面図である。(A) And (b) is a top view which shows an example of the wiring conductor in the package for semiconductor element accommodation of other embodiment of this invention, respectively. （ａ）は、本発明の他の実施形態の半導体素子収納用パッケージにおける配線導体の一例を示す平面図であり、（ｂ）は（ａ）の一部を拡大して示す平面図である。(A) is a top view which shows an example of the wiring conductor in the package for semiconductor element accommodation of other embodiment of this invention, (b) is a top view which expands and shows a part of (a).

本発明の半導体素子収納用パッケージおよび半導体装置について、添付の図面を参照して説明する。図１は、本発明の実施形態の半導体素子収納用パッケージを示す斜視図である。図２は、本発明の実施形態の半導体素子収納用パッケージを分解して示す分解斜視図である。図３は、本発明の実施形態の半導体素子収納用パッケージにおける配線導体の一例を示す斜視図である。図４は、本発明の実施形態の半導体素子収納用パッケージにおける入力部および出力部を示す斜視図である。   A semiconductor element housing package and a semiconductor device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a perspective view showing a package for housing semiconductor elements according to an embodiment of the present invention. FIG. 2 is an exploded perspective view showing the package for housing semiconductor elements according to the embodiment of the present invention in an exploded manner. FIG. 3 is a perspective view showing an example of a wiring conductor in the package for housing a semiconductor element according to the embodiment of the present invention. FIG. 4 is a perspective view showing an input part and an output part in the package for housing a semiconductor element according to the embodiment of the present invention.

例えば図１および図２に示すように、複数の絶縁層１が積層されて絶縁基板２が形成されている。また、絶縁層１の同士の層間に配線導体３が配置されている。実施形態の例では、配線導体３の一つの端に入力部４が設けられ、他の端に出力部５が設けられている。すなわち、配線導体３は、長さ方向の一部に入力部４を有するとともに、入力部４から離された位置に出力部５を有している。配線導体３は、その長さ方向の一部に、長さ方向に沿って伸びる非形成部６を有している。非形成部６は、配線導体３を、長さ方向に直交する幅方向に複数に分けるスリットとみなすことができる。これらの絶縁基板２および配線導体３等によって、実施形態の半導体素子収納用パッケージ10が基本的に構成されている。   For example, as shown in FIGS. 1 and 2, a plurality of insulating layers 1 are laminated to form an insulating substrate 2. Further, the wiring conductor 3 is disposed between the insulating layers 1. In the example of the embodiment, the input unit 4 is provided at one end of the wiring conductor 3 and the output unit 5 is provided at the other end. That is, the wiring conductor 3 has the input unit 4 in a part in the length direction and the output unit 5 at a position separated from the input unit 4. The wiring conductor 3 has a non-forming portion 6 extending along the length direction in a part of the length direction. The non-forming part 6 can be regarded as a slit that divides the wiring conductor 3 into a plurality of parts in the width direction orthogonal to the length direction. The insulating substrate 2, the wiring conductor 3, and the like basically constitute the semiconductor element storage package 10 of the embodiment.

なお、以下の説明における配線導体３の長さ方向とは、配線導体３において入力部３から出力部４に向かう電気信号（つまり電流）の流れ方向である。仮にスリットがないとしたときの配線導体の形状が正方形に近いような四角形状であったとしても、この長さ方向についての定義は同様に適用される。   In the following description, the length direction of the wiring conductor 3 is the flow direction of an electric signal (that is, current) from the input unit 3 to the output unit 4 in the wiring conductor 3. Even if the shape of the wiring conductor when there is no slit is a quadrangular shape that is close to a square, the definition of the length direction is similarly applied.

絶縁基板２は、平面視において長方形状であり、その短辺側の１辺が非形成である。すなわち、絶縁基板２およびこれを形成している複数の絶縁層１のそれぞれは、平面視において、１辺が欠けた長方形状であり、また、「コ」字状または「Ｕ」字状である。絶縁基板２は、上記欠けた１辺において開口部（符号なし）を有するものとみなすことができる。   The insulating substrate 2 has a rectangular shape in plan view, and one side on the short side is not formed. That is, each of the insulating substrate 2 and the plurality of insulating layers 1 forming the insulating substrate 2 has a rectangular shape with one side missing in a plan view, and has a “U” shape or a “U” shape. . The insulating substrate 2 can be regarded as having an opening (no symbol) on the one side that is missing.

本実施形態の半導体素子収納用パッケージ（以下、単にパッケージともいう）10において、絶縁基板２に金属製の封止体９が接合されて、半導体素子21を収容して気密封止する容器としての基体２Ａが形成されている。この実施形態における封止体９は、絶縁基板２の下面に接合された底板部９ａと、絶縁基板２の上面に接合された枠部９ｂと、底板部９ａと枠部９ｂとに接合されて絶縁基板２の開口部を覆う端部９ｃとを有している。端部９
ｃには、端部９ｃを厚み方向に貫通している貫通部９ｄが設けられている。 In a semiconductor element storage package (hereinafter also simply referred to as a package) 10 according to the present embodiment, a metal sealing body 9 is bonded to an insulating substrate 2 to accommodate a semiconductor element 21 and hermetically seal it. A base 2A is formed. The sealing body 9 in this embodiment is bonded to the bottom plate portion 9a bonded to the lower surface of the insulating substrate 2, the frame portion 9b bonded to the upper surface of the insulating substrate 2, and the bottom plate portion 9a and the frame portion 9b. And an end portion 9c that covers the opening of the insulating substrate 2. Edge 9
In c, a through portion 9d penetrating the end portion 9c in the thickness direction is provided.

封止体９の底部９ａ、枠部９ｂおよび端部９ｃと絶縁基板２とで囲まれる容器内に、光半導体素子または半導体集積回路素子等の半導体素子21が実装される。実装される半導体素子21は、絶縁基板２に設けられた配線導体３と電気的に接続される。配線導体３と電気的に接続された半導体素子21は、入力部４および出力部５を介して外部電気回路と電気的に接続させることができる。配線導体３等の導体の部分の詳細については後述する。   A semiconductor element 21 such as an optical semiconductor element or a semiconductor integrated circuit element is mounted in a container surrounded by the bottom portion 9a, the frame portion 9b and the end portion 9c of the sealing body 9, and the insulating substrate 2. The semiconductor element 21 to be mounted is electrically connected to the wiring conductor 3 provided on the insulating substrate 2. The semiconductor element 21 electrically connected to the wiring conductor 3 can be electrically connected to an external electric circuit via the input unit 4 and the output unit 5. Details of the conductor portion such as the wiring conductor 3 will be described later.

なお、実施形態のパッケージ10は、上記のような貫通部を有する端部９ｃを含むことから、貫通部９ｄを介して外部との光信号等の送受が容易になっている。すなわち、貫通部９ｄを通して容器内外を接続する光導波路等の光伝送材（図示せず）を配置すれば、光導波路等を通って光信号が容器内外に伝送され得る。   In addition, since the package 10 of the embodiment includes the end portion 9c having the through portion as described above, it is easy to send and receive optical signals and the like to the outside through the through portion 9d. That is, if an optical transmission material (not shown) such as an optical waveguide that connects the inside and outside of the container through the penetrating portion 9d is disposed, an optical signal can be transmitted into and out of the container through the optical waveguide or the like.

配線導体３は、絶縁層１の層間および絶縁基板２の露出表面（上面の一部）に位置している。また、上記のように、絶縁層１の層間に位置する配線導体３は、その長さ方向の一部に入力部４および出力部５を有している。配線導体３は、半導体素子21と電気的に接続されて、半導体素子21を外部電気回路に電気的に接続する導電路の一部を構成している。配線導体３と外部電気回路との電気的な接続は、上記のように入力部４および出力部５において行なわれる。実施形態の半導体素子収納用パッケージ10では、入力部４および出力部５のそれぞれが、絶縁層１の層間に配置された他の配線導体３Ａおよび絶縁層１を厚み方向に貫通する貫通導体（いわゆるビア導体）11を介して絶縁基板２の露出表面（上面の一部）に位置する入力端子４Ａまたは出力端子５Ａと電気的に接続されている。配線導体３と半導体素子21との電気的な接続は、この入力端子４Ａおよび出力端子５Ａを介して行なわせることができる。   The wiring conductor 3 is located between the insulating layer 1 and the exposed surface (a part of the upper surface) of the insulating substrate 2. In addition, as described above, the wiring conductor 3 positioned between the insulating layers 1 has the input unit 4 and the output unit 5 in a part in the length direction. The wiring conductor 3 is electrically connected to the semiconductor element 21 and constitutes a part of a conductive path that electrically connects the semiconductor element 21 to an external electric circuit. Electrical connection between the wiring conductor 3 and the external electric circuit is performed in the input unit 4 and the output unit 5 as described above. In the semiconductor element housing package 10 of the embodiment, each of the input unit 4 and the output unit 5 has a through conductor (so-called so-called through the other wiring conductor 3A and the insulating layer 1 disposed between the insulating layers 1 in the thickness direction). It is electrically connected to the input terminal 4A or the output terminal 5A located on the exposed surface (a part of the upper surface) of the insulating substrate 2 through the via conductors 11. The electrical connection between the wiring conductor 3 and the semiconductor element 21 can be made through the input terminal 4A and the output terminal 5A.

また、絶縁基板２を形成している複数の絶縁層１は、平面視における寸法が互いに異なるものを含んでいる。この寸法差に応じて、絶縁基板２表面（図１の例では上面）に段状の部分（段部）が設けられている。段部において露出する下層の絶縁層の上面に、配線導体３とビア導体等を介して電気的に接続された接続用の配線導体３Ｂが位置している。基体２Ａにおける容器内に位置する接続用の配線導体３Ｂは、例えばボンディングワイヤ等の導電性接続（図示せず）を介して半導体素子21と電気的に接続される。   Further, the plurality of insulating layers 1 forming the insulating substrate 2 include those having different dimensions in plan view. In accordance with this dimensional difference, a stepped portion (step portion) is provided on the surface of the insulating substrate 2 (upper surface in the example of FIG. 1). A wiring conductor 3B for connection electrically connected to the wiring conductor 3 via a via conductor or the like is located on the upper surface of the lower insulating layer exposed at the stepped portion. The connection wiring conductor 3B located in the container of the base 2A is electrically connected to the semiconductor element 21 through a conductive connection (not shown) such as a bonding wire.

このような配線導体３等の導体が設けられた絶縁基板２は、半導体素子収納用パッケージ10において、基体２Ａにおける容器内外の電気的な接続を行なう入出力部としての機能を有する部材とみなすこともできる。例えば、上記のように容器内に伝送された光信号が光半導体素子で電気信号に変換され、上記入出力部を介して外部電気回路に電気信号が伝送される。   The insulating substrate 2 provided with such a conductor such as the wiring conductor 3 is regarded as a member having a function as an input / output unit for electrically connecting the inside and outside of the container in the base 2A in the package 10 for housing a semiconductor element. You can also. For example, the optical signal transmitted into the container as described above is converted into an electrical signal by the optical semiconductor element, and the electrical signal is transmitted to the external electrical circuit via the input / output unit.

絶縁基板２およびこれを構成する絶縁層１は、例えば、酸化アルミニウム質焼結体、ムライト質焼結体、ガラスセラミック焼結体、窒化アルミニウム質焼結体または窒化ケイ素質焼結体等のセラミック材料によって形成されている。例えば絶縁基板２が、酸化アルミニウム質焼結体からなる複数の絶縁層１が積層されてなるものである場合には、次のようにして絶縁基板２を製作することができる。   The insulating substrate 2 and the insulating layer 1 constituting the insulating substrate 2 are made of, for example, a ceramic such as an aluminum oxide sintered body, a mullite sintered body, a glass ceramic sintered body, an aluminum nitride sintered body, or a silicon nitride sintered body. It is made of material. For example, when the insulating substrate 2 is formed by laminating a plurality of insulating layers 1 made of an aluminum oxide sintered body, the insulating substrate 2 can be manufactured as follows.

すなわち、まず、酸化アルミニウ、酸化ケイ素、酸化カルシウムおよび酸化マグネシウム等の原料粉末を、適当な有機溶剤およびバインダとともに混練してスラリーを作製する。次に、このスラリーをドクターブレード法またはリップコータ法等の成形法でシート状（帯状）に成形してセラミックグリーンシートを作製する。その後、セラミックグリーンシートを所定の形状および寸法に切断して複数のグリーンシートを作製し、これらのグリーンシートを上下に積層して約1300〜1600℃で焼成する。以上の工程によって、複数の絶縁層１が互いに上下に積層されてなる絶縁基板２を製作することができる。   That is, first, raw material powders such as aluminum oxide, silicon oxide, calcium oxide and magnesium oxide are kneaded together with an appropriate organic solvent and a binder to prepare a slurry. Next, this slurry is formed into a sheet shape (band shape) by a forming method such as a doctor blade method or a lip coater method to produce a ceramic green sheet. Thereafter, the ceramic green sheet is cut into a predetermined shape and size to produce a plurality of green sheets, and these green sheets are stacked one above the other and fired at about 1300-1600 ° C. Through the above steps, an insulating substrate 2 in which a plurality of insulating layers 1 are stacked one above the other can be manufactured.

配線導体３、他の配線導体３Ａ、接続用の配線導体３Ｂ、入力端子４Ａおよび出力端子５Ａならびに貫通導体11といった導体の部分（以下、配線導体３等という）は、例えば、タングステン、モリブデン、マンガン、銅、銀、パラジウム、金、白金、ニッケルまたはコバルト等の金属材料によって形成されている。配線導体３等は、このような金属材料の合金材料からなるものでもよく、複数の金属層が互いに積層等の手段で組み合わされたものでもよい。複数の金属層等は、互いに異なる種類の金属材料からなるものでもよく、互いに異なる厚みまたは直径を有するものでもよい。   The conductor portions (hereinafter referred to as the wiring conductor 3 etc.) such as the wiring conductor 3, the other wiring conductor 3A, the connecting wiring conductor 3B, the input terminal 4A and the output terminal 5A, and the through conductor 11 are, for example, tungsten, molybdenum, manganese , Copper, silver, palladium, gold, platinum, nickel or cobalt. The wiring conductor 3 or the like may be made of an alloy material of such a metal material, or may be a combination of a plurality of metal layers by means of lamination or the like. The plurality of metal layers and the like may be made of different types of metal materials, and may have different thicknesses or diameters.

配線導体３等は、例えば、タングステンからなる場合であれば、次のようにして形成することができる。まず、タングステン等の金属材料の粉末を有効溶剤およびバインダ等とともに混練して金属ペーストを作製する。次に、この金属ペーストを絶縁基板２の絶縁層１となるグリーンシートの表面にスクリーン印刷法等の方法で所定パターンに印刷する。貫通導体11となる金属ペーストについては、あらかじめグリーンシートに設けておいた貫通孔内に真空吸引を併用したスクリーン印刷等の方法で充填する。その後、この金属ペーストをグリーンシートと同時焼成する。以上の工程によって、配線導体３等が設けられた絶縁基板２を製作することができる。   For example, if the wiring conductor 3 is made of tungsten, it can be formed as follows. First, a powder of a metal material such as tungsten is kneaded together with an effective solvent and a binder to produce a metal paste. Next, this metal paste is printed in a predetermined pattern on the surface of the green sheet to be the insulating layer 1 of the insulating substrate 2 by a method such as screen printing. About the metal paste used as the penetration conductor 11, it fills by the method of screen printing etc. which used vacuum suction together in the through-hole previously provided in the green sheet. Thereafter, the metal paste is fired simultaneously with the green sheet. Through the above steps, the insulating substrate 2 provided with the wiring conductor 3 and the like can be manufactured.

配線導体３等は、上記のメタライズ層の露出表面にニッケルおよび金等のめっき層がさらに設けられたものでもよい。めっき層によって、配線導体３等の酸化が抑制され、信頼性が向上する。また、後述するボンディングワイヤ等の接続性（ボンディング性等）の特性が向上する。   The wiring conductor 3 or the like may be one in which a plating layer such as nickel and gold is further provided on the exposed surface of the metallized layer. Oxidation of the wiring conductor 3 etc. is suppressed by the plating layer, and reliability is improved. In addition, the characteristics of connectivity (bonding properties, etc.) of bonding wires and the like which will be described later are improved.

前述したように、実施形態の半導体素子収納用パッケージ10において、配線導体３が、入力部４と出力部５との間において、長さ方向に直交する幅方向の中央部分に、長さ方向に沿った非形成部６を有している。このような非形成部６が含まれていることから、配線導体３の電気抵抗の低減に有効であるとともに、長期信頼性の向上にも有効な半導体素子収納用パッケージ10を提供することができる。   As described above, in the semiconductor element housing package 10 according to the embodiment, the wiring conductor 3 is provided between the input unit 4 and the output unit 5 in the longitudinal direction at the central portion in the width direction orthogonal to the longitudinal direction. It has a non-formed part 6 along. Since such a non-formed portion 6 is included, it is possible to provide the semiconductor element housing package 10 that is effective in reducing the electrical resistance of the wiring conductor 3 and also effective in improving long-term reliability. .

すなわち、配線導体３が非形成部６を有するため、絶縁層１の層間において配線導体３に生じる熱応力を効果的に低減することができる。すなわち、配線導体３と絶縁基板２との間に生じる熱応力は、非形成部６によって分散される。したがって、例えば配線導体３の厚みを従来よりも大きくすること等による導通抵抗の低減と、熱応力による配線導体３等の機械的な破壊の可能性の低減とが容易になる。   That is, since the wiring conductor 3 has the non-formation part 6, the thermal stress generated in the wiring conductor 3 between the insulating layers 1 can be effectively reduced. That is, the thermal stress generated between the wiring conductor 3 and the insulating substrate 2 is dispersed by the non-forming portion 6. Therefore, for example, it is easy to reduce conduction resistance by increasing the thickness of the wiring conductor 3 than before, and to reduce the possibility of mechanical destruction of the wiring conductor 3 and the like due to thermal stress.

また、実施形態の半導体素子収納用パッケージ10では、配線導体３がその長さ方向に沿った非形成部６を有し、幅方向に複数に分割されていることから、１つ１つの分割された配線導体３の線幅は、仮に非形成部６がないとしたときに比べて小さい。そのため、例えば後述するように金属ペーストをスクリーン印刷等の印刷法で塗布して焼成する方法で配線導体３を形成するときに、配線導体３の線幅および厚みのばらつきの低減に対して有効である。この厚みばらつきの低減により、例えば配線導体３における電気信号の伝送特性をシミュレーションによって精度よく解析、予測し、設計することができる。そのため、伝送特性の向上が容易な配線基板10とすることもできる。   Further, in the semiconductor element housing package 10 of the embodiment, since the wiring conductor 3 has the non-formed portion 6 along the length direction and is divided into a plurality of parts in the width direction, the wiring conductors 3 are divided one by one. The line width of the wiring conductor 3 is smaller than when the non-formed part 6 is not provided. Therefore, for example, when forming the wiring conductor 3 by a method of applying and baking a metal paste by a printing method such as screen printing as will be described later, it is effective for reducing variations in the line width and thickness of the wiring conductor 3. is there. By reducing the thickness variation, for example, the transmission characteristic of the electric signal in the wiring conductor 3 can be accurately analyzed, predicted, and designed by simulation. Therefore, the wiring board 10 can be easily improved in transmission characteristics.

ここで、仮に、非形成部６を除いた部分における配線導体３の合計の幅と同じ幅であって非形成部を有していない配線導体を形成しようとすると、金属ペーストの印刷幅が比較的大きくなる。そのため、金属ペーストの表面張力およぶ重力による金属ペーストの湾曲または金属ペーストの粘度や前述のグリーンシートの表面粗さに起因した金属ペーストの広がり等に起因した金属ペーストの厚みばらつきが配線導体３の箇所によって比較的大き
くなる。これにより、配線導体３の幅方向等における厚みばらつきが比較的大きくなる可能性がある。これに対して、実施形態の配線基板３では、分割された配線導体３の厚みや広がりの制御が容易であり、配線導体３の幅方向における厚みや線幅のばらつきを小さくできる可能性がある。そのため、配線導体３の伝送特性の予測等が容易であり、かつ所望の厚さと線幅を有する配線導体３を作製することができ、伝送特性の向上に有利な半導体素子収納用パッケージ10とすることができる。 Here, if an attempt is made to form a wiring conductor that has the same width as the total width of the wiring conductor 3 in the portion excluding the non-formed portion 6 and has no non-formed portion, the printed width of the metal paste is compared. Become bigger. Therefore, the thickness of the metal paste due to the surface tension of the metal paste and the curvature of the metal paste due to gravity or the viscosity of the metal paste, the spread of the metal paste due to the surface roughness of the green sheet, etc. Is relatively large. Thereby, the thickness variation in the width direction or the like of the wiring conductor 3 may be relatively large. On the other hand, in the wiring board 3 of the embodiment, it is easy to control the thickness and spread of the divided wiring conductor 3, and there is a possibility that variations in thickness and line width in the width direction of the wiring conductor 3 can be reduced. . Therefore, it is easy to predict the transmission characteristics of the wiring conductor 3, and the wiring conductor 3 having a desired thickness and line width can be manufactured, and the semiconductor element housing package 10 is advantageous for improving the transmission characteristics. be able to.

非形成部６を有する配線導体３は、例えば、配線導体３となる金属ペーストを印刷するスクリーン印刷用の版面に、非形成部６に対応した非印刷部を設けておけばよい。すなわち、非形成部６と同様のパターンでメッシュが塞がれた版面を用いて、金属ペーストをグリーンシートの表面に印刷すればよい。   For example, the wiring conductor 3 having the non-formed portion 6 may be provided with a non-printing portion corresponding to the non-forming portion 6 on a screen printing plate on which a metal paste to be the wiring conductor 3 is printed. That is, the metal paste may be printed on the surface of the green sheet using a printing plate in which the mesh is closed with the same pattern as that of the non-formation part 6.

上記のように、実施形態の半導体素子収納用パッケージ10と、この半導体素子収納用パッケージ10に機械的に接続されているとともに、配線導体３と電気的に接続された半導体素子21とによって、本発明の実施形態の半導体装置20が構成される。半導体素子21の半導体素子収納用パッケージ10に対する機械的な接続、すなわち固定は、例えば、基体２Ａの封止体９に含まれる底部９ｂの上面に半導体素子21を接合したり、底部９ｂの上面に設置されるペルチェ素子（図示せず）に配置された配線基板（図示せず）に半導体素子21を接合したりすることで行なわれる。底部９ｂまたは前述の配線基板に対する半導体素子21の接合は、例えば、スズ−銀はんだまたは金−スズろう材等の低融点ろう材を介した接合によって行なうことができる。また、半導体素子21は、樹脂を含む接着剤またはフィラー含有ガラス等の接合材を介して底部９ｂまたは前述の配線基板に接合されてもよい。   As described above, the semiconductor element storage package 10 according to the embodiment and the semiconductor element 21 mechanically connected to the semiconductor element storage package 10 and electrically connected to the wiring conductor 3, A semiconductor device 20 according to an embodiment of the invention is configured. The mechanical connection of the semiconductor element 21 to the semiconductor element storage package 10, that is, fixing, is performed by, for example, joining the semiconductor element 21 to the upper surface of the bottom portion 9 b included in the sealing body 9 of the base 2 A or attaching the semiconductor element 21 to the upper surface of the bottom portion 9 b. This is performed by bonding the semiconductor element 21 to a wiring board (not shown) disposed on the installed Peltier element (not shown). The joining of the semiconductor element 21 to the bottom portion 9b or the above-described wiring board can be performed by joining via a low melting point brazing material such as tin-silver solder or gold-tin brazing material. The semiconductor element 21 may be bonded to the bottom portion 9b or the above-described wiring board via a bonding material such as an adhesive containing resin or filler-containing glass.

半導体素子21または半導体素子21と電気的に接続される前述の配線基板と配線導体３との電気的な接続は、例えば上記のようにボンディングワイヤを介して行なうことができる。また、半導体素子21と配線導体３との電気的な接続は、樹脂製シートに導体が設けられてなるフレキシブル基板または異方導電性接着剤等の他の導電性接続材を介して行なわれてもよい。   The electrical connection between the semiconductor element 21 or the above-described wiring board electrically connected to the semiconductor element 21 and the wiring conductor 3 can be performed, for example, via bonding wires as described above. In addition, the electrical connection between the semiconductor element 21 and the wiring conductor 3 is performed through a flexible substrate in which a conductor is provided on a resin sheet or another conductive connecting material such as an anisotropic conductive adhesive. Also good.

例えば図３に示す例のように、実施形態の半導体素子収納用パッケージ10および半導体装置20において、１つの配線導体３に複数の非形成部６が、配線導体３の幅方向に並んで配置されている。また、複数の非形成部６は、配線導体３の幅方向に平行に並んで配置される。このような場合には、分割された個々の配線導体３の幅を効果的に小さく抑えることができる。したがって、絶縁層１と配線導体３との熱膨張係数差に起因して生じる、配線導体３における応力の集中を効果的に緩和し、信頼性の向上に有利な半導体素子収納用パッケージ10および半導体装置20とすることができる。   For example, as in the example shown in FIG. 3, in the semiconductor element housing package 10 and the semiconductor device 20 of the embodiment, a plurality of non-formed portions 6 are arranged side by side in the width direction of the wiring conductor 3 in one wiring conductor 3. ing. The plurality of non-formed portions 6 are arranged in parallel with the width direction of the wiring conductor 3. In such a case, the width of each divided wiring conductor 3 can be effectively reduced. Therefore, the concentration of stress in the wiring conductor 3 caused by the difference in thermal expansion coefficient between the insulating layer 1 and the wiring conductor 3 can be effectively alleviated, and the semiconductor element housing package 10 and the semiconductor which are advantageous for improving the reliability. Device 20 may be used.

また、この場合には、分割された個々の配線導体３の厚みの精度を効果的に高めることができ、配線導体３の厚みまたは線幅のばらつきを低減することができる。したがって、配線導体３の伝送特性をさらに向上させる上で有利な半導体素子収納用パッケージ10とすることができる。   In this case, the accuracy of the thickness of each divided wiring conductor 3 can be effectively increased, and variations in the thickness or line width of the wiring conductor 3 can be reduced. Therefore, it is possible to obtain a semiconductor element housing package 10 that is advantageous in further improving the transmission characteristics of the wiring conductor 3.

なお、分割された個々の配線導体３の幅が小さくなり過ぎると、例えばスクリーン印刷時のメッシュの影響が大きくなって、配線導体３の線幅がばらつく可能性が高くなる。したがって、配線導体３に複数の非形成部６を設ける場合には、非形成部を挟んで分割された個々の配線導体３の線幅が、例えば約30〜50μｍまたはそれ以上になるように調整すればよい。   If the width of each divided wiring conductor 3 becomes too small, for example, the influence of the mesh at the time of screen printing increases, and the possibility that the line width of the wiring conductor 3 varies will increase. Accordingly, when a plurality of non-formed portions 6 are provided in the wiring conductor 3, the line width of each wiring conductor 3 divided across the non-formed portions is adjusted to be, for example, about 30 to 50 μm or more. do it.

図５（ａ）および（ｂ）は、それぞれ本発明の他の実施形態の半導体素子収納用パッケージにおける配線導体の一例を示す平面図である。図６（ａ）は、本発明の他の実施形態の半導体素子収納用パッケージ10および半導体装置20における配線導体３の一例を示す平面図であり、図６（ｂ）は図６（ａ）の一部を拡大して示す平面図である。図５および図６において図１〜図４と同様の部位には同様の符号を付している。   FIGS. 5A and 5B are plan views showing examples of wiring conductors in a package for housing a semiconductor element according to another embodiment of the present invention. FIG. 6A is a plan view showing an example of the wiring conductor 3 in the semiconductor element housing package 10 and the semiconductor device 20 according to another embodiment of the present invention, and FIG. 6B is a plan view of FIG. It is a top view which expands and shows a part. In FIGS. 5 and 6, the same parts as those in FIGS.

図５（ａ）に示す例では、配線導体３の長さ方向に直交する方向の非形成部６の幅が比較的大きく、図５（ｂ）に示す例では、配線導体３の長さ方向に直交する方向の非形成部６の幅が比較的小さい。また、図５（ａ）および（ｂ）のいずれにおいても、分割された個々の配線導体３の長さ方向に直交する方向の線幅は、互いに同じ程度に揃えられているとともに、非形成部６の幅より大きい（広い）。これにより、配線導体３は、電気抵抗が小さくなり、電気的な伝送特性をさらに向上させる上で有利な半導体素子収納用パッケージ10とすることができる。さらに、配線導体３は、入力部４と出力部５に接続される、配線導体３の長さ方向に直交する方向に設けられる配線導体３の線幅が、分割された個々の配線導体３の長さ方向に直交する方向の線幅と同じ程度に揃えられている。また、個々の非形成部６の幅も、互いに同じ程度に揃えられている。この場合には、分割された個々の配線導体３の線幅および非形成部６の幅が一定であるため、個々の配線導体の一部に電流が集中するような可能性が低減される。そのため、電気的な特性の向上に有利である。さらに、個々の配線導体３の一部に、パッケージ10または半導体装置20の製造工程において生じる応力が集中するような可能性が低減される。そのため、半導体素子収納用パッケージ10および半導体装置20の長期信頼性の向上に有利である。また、設計が容易であり、生産性の向上についても有利な半導体素子収納用パッケージ10および半導体装置20とすることができる。   In the example shown in FIG. 5A, the width of the non-forming portion 6 in the direction orthogonal to the length direction of the wiring conductor 3 is relatively large. In the example shown in FIG. The width of the non-forming portion 6 in the direction orthogonal to the width is relatively small. 5A and 5B, the line widths of the divided individual wiring conductors 3 in the direction orthogonal to the length direction are aligned to the same extent, and the non-formed part. Greater than 6 width (wide). As a result, the wiring conductor 3 has a reduced electrical resistance and can be made into a semiconductor element housing package 10 that is advantageous in further improving the electrical transmission characteristics. Furthermore, the wiring conductor 3 is connected to the input unit 4 and the output unit 5, and the line width of the wiring conductor 3 provided in the direction orthogonal to the length direction of the wiring conductor 3 is the same as that of each divided wiring conductor 3. It is aligned to the same extent as the line width in the direction orthogonal to the length direction. Further, the widths of the individual non-formed portions 6 are also aligned to the same extent. In this case, since the line width of the divided individual wiring conductors 3 and the width of the non-forming portion 6 are constant, the possibility that current is concentrated on a part of the individual wiring conductors is reduced. Therefore, it is advantageous for improvement of electrical characteristics. Furthermore, the possibility that stress generated in the manufacturing process of the package 10 or the semiconductor device 20 is concentrated on a part of each wiring conductor 3 is reduced. Therefore, it is advantageous for improving the long-term reliability of the semiconductor element storage package 10 and the semiconductor device 20. In addition, the semiconductor element storage package 10 and the semiconductor device 20 that are easy to design and advantageous in improving productivity can be obtained.

図５（ａ）に示す例のように非形成部６の幅が比較的大きい場合には、非形成部となる非印刷部分を設けながら、配線導体３となる金属ペーストを印刷することが容易である。また、図５（ｂ）に示す例のように非形成部６の幅が比較的小さい場合には、配線導体３の電気抵抗の低減に有利である。したがって、伝送特性の向上に有利な半導体素子収納用パッケージ10および半導体装置20とすることができる。   When the width of the non-formed part 6 is relatively large as in the example shown in FIG. 5A, it is easy to print the metal paste that becomes the wiring conductor 3 while providing the non-printed part that becomes the non-formed part. It is. Further, when the width of the non-forming portion 6 is relatively small as in the example shown in FIG. 5B, it is advantageous for reducing the electric resistance of the wiring conductor 3. Therefore, the semiconductor element housing package 10 and the semiconductor device 20 that are advantageous in improving transmission characteristics can be obtained.

図６に示す例は、図５に示した図１の変形例とは異なる他の変形例とみなすこともできる。図６に示す例では、非形成部３を挟んで隣り合う配線導体３（非形成部によって分割されたもの）同士を接続する補助配線８が設けられている。図６（ａ）では、補助配線8
が設けられている領域を仮想線８Ａで示している。 The example shown in FIG. 6 can be regarded as another modified example different from the modified example of FIG. 1 shown in FIG. In the example shown in FIG. 6, the auxiliary wiring 8 that connects the adjacent wiring conductors 3 (divided by the non-forming part) across the non-forming part 3 is provided. In FIG. 6A, auxiliary wiring 8
A region where the symbol is provided is indicated by a virtual line 8A.

図６に示す例において、接続部Ｓにおける配線導体３の厚みが他の部分と異なっている。図６（ｂ）において、配線導体３のうち、他の部分よりも厚みが大きい接続部Ｓ（Ｓ１）と、他の部分よりも厚みが小さい接続部Ｓ（Ｓ２）とを示している。   In the example shown in FIG. 6, the thickness of the wiring conductor 3 in the connection portion S is different from the other portions. In FIG.6 (b), the connection part S (S1) with a thickness larger than another part among the wiring conductors 3 and the connection part S (S2) with a thickness smaller than another part are shown.

すなわち、実施形態の半導体素子収納用パッケージ10において、非形成部６の一部に、上記の幅方向に伸びるとともに配線導体３と接続している補助配線８が位置していてもよい。この場合には、補助配線８によって、非形成部６が長さ方向において複数に分割されたものとみなすこともできる。すなわち、個々の非形成部６の長さが比較的小さく（短く）なっている。このような場合には、補助配線８を介して、互いに隣り合う配線導体３間でも電流が流れ得る。これによって、配線導体３の見かけの線幅を大きくして、電気抵抗を効果的に低減することもできる。   That is, in the semiconductor element housing package 10 of the embodiment, the auxiliary wiring 8 that extends in the width direction and is connected to the wiring conductor 3 may be located in a part of the non-forming portion 6. In this case, it can be considered that the non-forming portion 6 is divided into a plurality of parts in the length direction by the auxiliary wiring 8. That is, the length of each non-formation part 6 is comparatively small (short). In such a case, a current can flow between the wiring conductors 3 adjacent to each other via the auxiliary wiring 8. As a result, the apparent line width of the wiring conductor 3 can be increased and the electrical resistance can be effectively reduced.

また、非形成部６による応力の分散の効果を得ながら、補助配線８を含めた配線導体３等の導体の絶縁基板２に対する接合面積をより大きくすることもできる。また、個々の、非形成部６に沿った配線導体３の長さ方向の寸法（すなわち長さ）を小さく抑えることもできるため、配線導体３となる金属ペーストのばらつきも効果的に低減することができる。したがって、信頼性の向上、導通抵抗の低減および伝送特性の向上に有利な半導体素子収納用パッケージ10および半導体装置20とすることができる。   Further, it is possible to increase the bonding area of the conductor such as the wiring conductor 3 including the auxiliary wiring 8 with respect to the insulating substrate 2 while obtaining the effect of stress distribution by the non-forming portion 6. Moreover, since the dimension (namely, length) of the wiring conductor 3 along the non-formation part 6 in the length direction can be suppressed to be small, the dispersion of the metal paste used as the wiring conductor 3 can be effectively reduced. Can do. Therefore, it is possible to obtain the semiconductor element housing package 10 and the semiconductor device 20 that are advantageous in improving reliability, reducing conduction resistance, and improving transmission characteristics.

なお、図６に示す例は、正方形状の分散型の非形成部６が、配線導体３に縦横の並びに設けられた例とみなすこともできる。この例に示すように、非形成部６は、必ずしも、配線導体３の長さ方向における寸法が、それと直交する方向における寸法よりも大きいものである必要はない。つまり、非形成部６は、配線導体３の長さ方向に沿った細長いものである必要はない。例えば正方形状の分散型の非形成部６が縦横の並びに設けられた例では、補助配線８による、配線導体３の電気抵抗の低減の効果を高めることができる。   The example shown in FIG. 6 can also be regarded as an example in which square-shaped distributed non-forming portions 6 are provided in the wiring conductor 3 vertically and horizontally. As shown in this example, the non-formation part 6 does not necessarily need to have a dimension in the length direction of the wiring conductor 3 larger than a dimension in a direction orthogonal to the dimension. That is, the non-formation part 6 does not need to be elongate along the length direction of the wiring conductor 3. For example, in an example in which square-shaped distributed non-forming portions 6 are provided vertically and horizontally, the effect of reducing the electrical resistance of the wiring conductor 3 by the auxiliary wiring 8 can be enhanced.

さらに、正方形状の分散型の非形成部６は、平面視において、配線導体３の長さ方向に対して傾く方向で等間隔に配置される。また、正方形状の分散型の非形成部６は、配線導体３の電気抵抗を低減しつつ、パッケージ10または半導体装置20の製造工程において生じる応力が配線導体３の一部に集中することを低減するために、平面視において、配線導体３の長さ方向に対して45°の傾きで等間隔に配置される。   Furthermore, the square distributed non-forming portions 6 are arranged at equal intervals in a direction inclined with respect to the length direction of the wiring conductor 3 in plan view. Further, the square distributed non-forming portion 6 reduces the electrical resistance of the wiring conductor 3 and reduces the concentration of stress generated in the manufacturing process of the package 10 or the semiconductor device 20 on a part of the wiring conductor 3. For this purpose, they are arranged at equal intervals with an inclination of 45 ° with respect to the length direction of the wiring conductor 3 in plan view.

また、上記の実施形態の半導体素子収納用パッケージ10および半導体装置20において、配線導体３の厚さが、補助配線８が接続されている接続部Ｓにおいて他の部分と異なるものであってもよい。   Further, in the semiconductor element housing package 10 and the semiconductor device 20 of the above embodiment, the thickness of the wiring conductor 3 may be different from other portions in the connection portion S to which the auxiliary wiring 8 is connected. .

接続部Ｓにおける配線導体３の厚みが、他の部分における配線導体３の厚みと異なる場合には、接続部Ｓにおける応力を配線導体３の厚み方向に分散させて、配線導体３と絶縁基板２との接合の信頼性を向上させることができたり、接続部Ｓの機械的な強度を向上させたりすることができる。すなわち、配線導体３と補助配線８との接続し合う部分では、配線としての伸びる方向、または縮む方向が互いに異なる配線導体３と補助配線８との間で応力が集中しやすい。また、絶縁層１と配線導体３および補助配線８との熱膨張係数差に起因して生じる応力が接続部Ｓとなる補助配線８に集中しやすい。これに対して、他の部分と厚みが異なる接続部Ｓの場合には、厚み方向（上下方向）において応力が集中しやすい部分を他の部分と異ならせることができたり、接続部Ｓの機械的な強度を向上させたりすることができる。そのため、配線導体３の一部に応力が集中する可能性が効果的に低減されたり、補助配線８にクラックや割れが生じる可能性が低減されたりし、補助配線８の電気的な接続不良が生じる可能性を低減することができる。したがって、配線導体３と絶縁基板２との接合の信頼性が向上した半導体素子収納用パッケージ10および半導体装置20とすることもできる。   When the thickness of the wiring conductor 3 in the connection portion S is different from the thickness of the wiring conductor 3 in other portions, the stress in the connection portion S is dispersed in the thickness direction of the wiring conductor 3, so that the wiring conductor 3 and the insulating substrate 2. It is possible to improve the reliability of bonding with the contact portion S, and to improve the mechanical strength of the connection portion S. That is, in a portion where the wiring conductor 3 and the auxiliary wiring 8 are connected to each other, stress is likely to concentrate between the wiring conductor 3 and the auxiliary wiring 8 that are different from each other in the extending direction or contracting direction as the wiring. Further, the stress generated due to the difference in thermal expansion coefficient between the insulating layer 1 and the wiring conductor 3 and the auxiliary wiring 8 tends to concentrate on the auxiliary wiring 8 serving as the connection portion S. On the other hand, in the case of the connection portion S having a thickness different from that of the other portion, the portion where stress is likely to concentrate in the thickness direction (vertical direction) can be made different from the other portion. Strength can be improved. Therefore, the possibility that stress is concentrated on a part of the wiring conductor 3 is effectively reduced, and the possibility that cracks and cracks are generated in the auxiliary wiring 8 is reduced. The possibility of occurring can be reduced. Therefore, the semiconductor element housing package 10 and the semiconductor device 20 with improved reliability of bonding between the wiring conductor 3 and the insulating substrate 2 can be obtained.

また、配線導体３の厚さが、補助配線８が接続されている接続部Ｓにおいて他の部分よりも大きい場合には、比較的電流が集中しやすい接続部において配線導体３の電気抵抗が他の部分よりも低減される。そのため、接続部Ｓにおいても電流（つまり電気信号）が効率よく伝送される。これによって、半導体素子収納用パッケージ10および半導体装置20における電気特性を向上させることもできる。さらに、配線導体３は、接続部Ｓの厚さを他の部分よりも大きくすることにより、接続部Ｓの機械的な強度を向上させることができる。これにより、絶縁層１と配線導体３との熱膨張係数差に起因して生じる応力が接続部Ｓとなる補助配線８に集中することにより、補助配線８にクラックや割れが生じる可能性を低減できる。よって、配線導体３は、電気的な接続不良が補助配線８に生じる可能性を低減できる。   In addition, when the thickness of the wiring conductor 3 is larger than the other portions in the connection portion S to which the auxiliary wiring 8 is connected, the electrical resistance of the wiring conductor 3 is different in the connection portion where current tends to concentrate relatively. It is reduced more than the part. Therefore, the current (that is, the electric signal) is also efficiently transmitted in the connection portion S. As a result, the electrical characteristics of the semiconductor element storage package 10 and the semiconductor device 20 can be improved. Furthermore, the wiring conductor 3 can improve the mechanical strength of the connection part S by making the thickness of the connection part S larger than the other part. As a result, the stress caused by the difference in thermal expansion coefficient between the insulating layer 1 and the wiring conductor 3 is concentrated on the auxiliary wiring 8 serving as the connection portion S, thereby reducing the possibility of the auxiliary wiring 8 being cracked or cracked. it can. Therefore, the wiring conductor 3 can reduce the possibility that an electrical connection failure occurs in the auxiliary wiring 8.

また、配線導体３の厚さが、補助配線８が接続されている接続部Ｓにおいて他の部分よりも小さい場合には、接続部において配線導体３または補助配線８となる金属ペーストの印刷時のにじみ、広がり等の可能性が低減される。そのため、配線導体３および補助配線８の線幅を所定の数値に制御することが容易であるとともに、絶縁層１と配線導体３および補助配線８との熱膨張係数差に起因して生じる応力が接続部Ｓとなる補助配線８に集中
する可能性を低減することができる。つまり、電気抵抗の低減を重視するときには、前述のように接続部Ｓにおける配線導体３の厚さが比較的大きい方がよく、配線導体３の線幅の精度、制御を重視するときには、接続部Ｓにおける配線導体３の厚さが比較的小さい方がよい。 In addition, when the thickness of the wiring conductor 3 is smaller than the other portions in the connection portion S to which the auxiliary wiring 8 is connected, the metal paste that becomes the wiring conductor 3 or the auxiliary wiring 8 in the connection portion is printed. The possibility of bleeding, spreading, etc. is reduced. Therefore, it is easy to control the line widths of the wiring conductor 3 and the auxiliary wiring 8 to predetermined values, and stress generated due to the difference in thermal expansion coefficient between the insulating layer 1 and the wiring conductor 3 and auxiliary wiring 8 is generated. The possibility of concentrating on the auxiliary wiring 8 serving as the connection portion S can be reduced. That is, when importance is placed on the reduction of electrical resistance, the thickness of the wiring conductor 3 in the connection portion S should be relatively large as described above, and when importance is placed on the accuracy and control of the line width of the wiring conductor 3, the connection portion The thickness of the wiring conductor 3 in S should be relatively small.

また、接続部Ｓは、入力部４と出力部５との間における、絶縁層１の各辺に沿った配線導体３の外周部分に位置する、補助配線８との接続部分を含み、この接続部Ｓにおける配線導体３の厚さが他の部分と異なることにより、配線導体３は、前述と同様の作用効果を得ることができる。   In addition, the connection portion S includes a connection portion with the auxiliary wiring 8 located at the outer peripheral portion of the wiring conductor 3 along each side of the insulating layer 1 between the input portion 4 and the output portion 5. Since the thickness of the wiring conductor 3 in the portion S is different from that of the other portions, the wiring conductor 3 can obtain the same effects as described above.

なお、接続部Ｓにおいて配線導体３の厚さが他の部分と異なったとしても、配線導体３の全長に比べれば短い区間であるため、配線導体３全体の電気抵抗に対する影響は小さい。そのため、この構成おいても、配線導体３の伝送特性の向上が容易な半導体素子収納用パッケージ10および半導体装置20とすることができる。   Even if the thickness of the wiring conductor 3 in the connection portion S is different from that of the other portions, the influence on the electrical resistance of the entire wiring conductor 3 is small because it is a section shorter than the entire length of the wiring conductor 3. Therefore, even in this configuration, it is possible to provide the semiconductor element housing package 10 and the semiconductor device 20 in which the transmission characteristics of the wiring conductor 3 can be easily improved.

接続部Ｓにおける配線導体３の厚みを他の部分と異ならせるには、例えば、配線導体３となる金属ペーストおよび補助配線８となる金属ペーストの少なくとも一方について、その粘度、印刷厚み、版面とグリーンシートとの間の距離、グリーンシートの表面粗さおよび印刷速度（スキージの移動速度）等の条件を適宜調整すればよい。この調整によって、接続部Ｓに金属ペーストが集中しやくなるか、または逃げやすくなり、接続部Ｓにおける金属ペーストの印刷厚みを他の部分と異ならせることができる。   In order to make the thickness of the wiring conductor 3 in the connection portion S different from other portions, for example, at least one of the metal paste that becomes the wiring conductor 3 and the metal paste that becomes the auxiliary wiring 8, its viscosity, printing thickness, plate surface and green Conditions such as the distance to the sheet, the surface roughness of the green sheet, and the printing speed (squeegee moving speed) may be appropriately adjusted. This adjustment makes it easier for the metal paste to concentrate on the connection portion S or makes it easier to escape, so that the printed thickness of the metal paste at the connection portion S can be different from other portions.

１・・絶縁層
２・・絶縁基板
２Ａ・・基体
３・・配線導体
３Ａ・・他の配線導体
３Ｂ・・接続用の配線導体
４・・入力部
４Ａ・・入力端子
５・・出力部
５Ａ・・出力端子
６・・非形成部
８・・補助配線
Ｓ・・接続部
９・・封止体
９ａ・・底部
９ｂ・・枠部
９ｃ・・端部
10・・半導体素子収納用パッケージ
11・・貫通導体
20・・電子装置 1 .. Insulating layer 2.. Insulating substrate 2 A.. Substrate 3. Wiring conductor 3 A.. Other wiring conductor 3 B... Wiring conductor 4 for connection 4 Input section 4 A Input terminal 5 Output section 5 A · · Output terminal 6 · · Non-formed portion 8 · · Auxiliary wiring S · · Connection portion 9 · · Sealing body 9a · · Bottom portion 9b · · Frame portion 9c · · End
10. ・ Semiconductor element storage package
11. ・ Penetration conductor
20 ・ ・ Electronic equipment

Claims (5)

互いに積層された複数の絶縁層を含む絶縁基板と、
前記絶縁層の層間に位置しており、長さ方向の一部に入力部を有するとともに該入力部から離れた位置に出力部を有する配線導体とを備えており、
該配線導体が、前記入力部と前記出力部との間において、前記長さ方向に直交する幅方向の中央部分に、前記長さ方向に沿った非形成部を有している半導体素子収納用パッケージ。 An insulating substrate including a plurality of insulating layers stacked on each other;
It is located between the insulating layers, and has a wiring conductor having an input part at a part in the length direction and an output part at a position away from the input part,
For wiring of a semiconductor element, the wiring conductor has a non-formed portion along the length direction at a central portion in the width direction orthogonal to the length direction between the input portion and the output portion. package. 複数の前記非形成部が、前記配線導体の前記幅方向に並んで配置されている請求項１記載の半導体素子収納用パッケージ。   The package for housing semiconductor elements according to claim 1, wherein the plurality of non-formed portions are arranged side by side in the width direction of the wiring conductor. 前記非形成部の一部に前記幅方向に伸びるとともに前記配線導体と接続している補助配線が位置しており、該補助配線によって、前記非形成部が、前記長さ方向において複数に分割されている請求項１または請求項２記載の半導体素子収納用パッケージ。   An auxiliary wiring extending in the width direction and connected to the wiring conductor is located in a part of the non-formed portion, and the non-formed portion is divided into a plurality of portions in the length direction by the auxiliary wiring. The package for housing a semiconductor device according to claim 1 or 2. 前記配線導体の厚さが、前記補助配線が接続されている接続部において他の部分と異なる請求項１〜請求項３のいずれか１項記載の半導体素子収納用パッケージ。   4. The package for housing a semiconductor element according to claim 1, wherein a thickness of the wiring conductor is different from other portions in a connection portion to which the auxiliary wiring is connected. 5. 請求項１〜請求項４のいずれか１項記載の半導体素子収納用パッケージと、
前記搭載部に搭載され、前記配線導体と電気的に接続された半導体素子とを備える半導体装置。 A package for housing a semiconductor element according to any one of claims 1 to 4,
A semiconductor device comprising: a semiconductor element mounted on the mounting portion and electrically connected to the wiring conductor.
JP2017105813A 2017-05-29 2017-05-29 Semiconductor element storage package and semiconductor device Active JP7038492B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017105813A JP7038492B2 (en) 2017-05-29 2017-05-29 Semiconductor element storage package and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017105813A JP7038492B2 (en) 2017-05-29 2017-05-29 Semiconductor element storage package and semiconductor device

Publications (2)

Publication Number Publication Date
JP2018200987A true JP2018200987A (en) 2018-12-20
JP7038492B2 JP7038492B2 (en) 2022-03-18

Family

ID=64667344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017105813A Active JP7038492B2 (en) 2017-05-29 2017-05-29 Semiconductor element storage package and semiconductor device

Country Status (1)

Country Link
JP (1) JP7038492B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923045A (en) * 1995-07-05 1997-01-21 Kyocera Corp Wiring board
JP2002324867A (en) * 2001-04-24 2002-11-08 Kyocera Corp Ceramic terminal and package for storing semiconductor element
JP2002324868A (en) * 2001-04-24 2002-11-08 Kyocera Corp Ceramic terminal and package for storing semiconductor element
WO2015076121A1 (en) * 2013-11-20 2015-05-28 株式会社村田製作所 Multilayer wiring substrate and probe card provided therewith

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923045A (en) * 1995-07-05 1997-01-21 Kyocera Corp Wiring board
JP2002324867A (en) * 2001-04-24 2002-11-08 Kyocera Corp Ceramic terminal and package for storing semiconductor element
JP2002324868A (en) * 2001-04-24 2002-11-08 Kyocera Corp Ceramic terminal and package for storing semiconductor element
WO2015076121A1 (en) * 2013-11-20 2015-05-28 株式会社村田製作所 Multilayer wiring substrate and probe card provided therewith

Also Published As

Publication number Publication date
JP7038492B2 (en) 2022-03-18

Similar Documents

Publication Publication Date Title
WO2016017574A1 (en) Package for housing electronic components and electronic device comprising same
JP6140834B2 (en) Wiring board and electronic device
US10334740B2 (en) Electronic-component mount substrate, electronic device, and electronic module
US9848491B2 (en) Wiring board, electronic device, and electronic module
CN110622300A (en) Electronic component mounting substrate, electronic device, and electronic module
JP6825986B2 (en) Wiring boards, electronic component storage packages and electronic devices
JP2016115736A (en) Semiconductor element package and semiconductor device
JP2014049482A (en) Wiring board, electronic device, and electronic module
JP6224322B2 (en) Electronic component storage package and electronic device using the same
JP2012156428A (en) Package for housing electronic component, and electronic device having the same
JP2016006846A (en) Wiring board and electronic apparatus
JP6680521B2 (en) Electronic equipment
JP2018200987A (en) Semiconductor device housing package and semiconductor device
JP6224473B2 (en) Wiring board, electronic device and electronic module
JP2014049590A (en) Wiring board and electronic device
JP5721359B2 (en) Semiconductor device substrate and semiconductor device including the same
US10388628B2 (en) Electronic component package
JP6166094B2 (en) Wiring board and electronic device
JP2018198249A (en) Wiring board
JP6885706B2 (en) Substrate for mounting semiconductor elements and semiconductor devices
JP7433766B2 (en) Circuit boards, electronic components and electronic modules
JP6680634B2 (en) Substrate for mounting semiconductor element and semiconductor device
JP2010056506A (en) Mounting structure of electronic apparatus
WO2020004459A1 (en) Electronic element mounting substrate, electronic device, and electronic module
JP2017079258A (en) Electronic part-mounting board and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200110

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20201112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20201124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210706

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20210827

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20210827

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210901

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220215

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220308

R150 Certificate of patent or registration of utility model

Ref document number: 7038492

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150