JP2018093114A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2018093114A
JP2018093114A JP2016236918A JP2016236918A JP2018093114A JP 2018093114 A JP2018093114 A JP 2018093114A JP 2016236918 A JP2016236918 A JP 2016236918A JP 2016236918 A JP2016236918 A JP 2016236918A JP 2018093114 A JP2018093114 A JP 2018093114A
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Japan
Prior art keywords
semiconductor device
layer
semiconductor chip
metal layer
electrode
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JP2016236918A
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English (en)
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JP6860334B2 (ja
JP2018093114A5 (ja
Inventor
達郎 刀禰館
Tatsuro Tonedachi
達郎 刀禰館
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Priority to JP2016236918A priority Critical patent/JP6860334B2/ja
Priority to US15/688,572 priority patent/US20180158762A1/en
Publication of JP2018093114A publication Critical patent/JP2018093114A/ja
Publication of JP2018093114A5 publication Critical patent/JP2018093114A5/ja
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Publication of JP6860334B2 publication Critical patent/JP6860334B2/ja
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Abstract

【課題】信頼性を保ちつつ、放熱効率を向上させることができる半導体装置を提供する。
【解決手段】本実施形態による半導体装置は、第１の電極と、第２の電極と、を第１の面に有する半導体チップと、前記第１の電極に接続された第１の配線と、前記第２の電極に直接接続され、前記半導体チップの前記第１の面から前記第１の配線の頂部までの長さより大きい厚みを有し、銅を主材料とする第１の層と、前記第１の層上に設けられた第２の配線と、前記半導体チップ、前記第１の配線、前記第１の層、前記第２の配線の一部を封止するとともに、前記第２の配線の他の一部を露出するよう設けられた半導体パッケージと、を備える。
【選択図】図２

Description

本発明による実施形態は、半導体装置に関する。
半導体パワーパッケージ等の半導体装置は、パッケージの上下両面に露出した接続導体を有する表面放熱型がある。リードフレーム等の接続導体は、半田を介して半導体チップに接続されている。また、接続導体と半導体チップとの間に、効率よく放熱するための金属スペーサが設けられている場合がある。金属スペーサは、熱伝導率の低い半田を介して半導体チップに接続されている。そのため、半導体チップから発生する熱は効率よく金属スペーサに伝熱しにくく、場合によっては高い熱抵抗のために短時間で破壊に至る場合がある。また、例えばＩＧＢＴを有する半導体チップにおいて、金属スペーサは、半導体チップ上面のエミッタ電極に電気的に接続している。半導体チップ上面には、エミッタ電極の他にワイヤに接続されたゲート電極や、エミッタ電極に対し電位の異なる部分が設けられている。従って、金属スペーサやリードフレームの実装時に半田がはみ出すことによって、エミッタ電極がエミッタ電極に対し電位の異なる部分やゲート電極とショートしないようにする必要がある。このため、金属スペーサのサイズはエミッタ電極上面の面積より小さくなるよう制限される。あるいは、エミッタ電極とゲート電極間の距離を十分に設ける必要があるため、チップ面積が増大してしまう。以上により、電極間でショートしないよう信頼性を保ちつつ、放熱効率を向上させるには問題があった。
特開２００２−１１０９８１号公報 特開２０１５−５０３４７号公報
信頼性を保ちつつ、放熱効率を向上させることができる半導体装置を提供する。
本実施形態による半導体装置は、第１の電極と、第２の電極と、を第１の面に有する半導体チップと、前記第１の電極に接続された第１の配線と、前記第２の電極に直接接続され、前記半導体チップの前記第１の面から前記第１の配線の頂部までの長さより大きい厚みを有し、銅を主材料とする第１の層と、前記第１の層上に設けられた第２の配線と、前記半導体チップ、前記第１の配線の少なくとも一部、前記第２の配線の一部、前記第１の層、を封止するとともに、前記第２の配線の他の一部を露出するよう設けられた半導体パッケージと、を備える。
第１実施形態に係る半導体装置を模式的に示す斜視図。 図１に示す半導体装置の切断線ＩＩ−ＩＩに沿った断面図。 第１実施形態に係る半導体装置の内部を説明するための図であり、半導体チップに金属層を設けた構造の斜視図。 図３に示す半導体装置の内部構造を示す平面図。 図２に示す半導体装置の一部を拡大した断面図。 第１実施形態に係る熱抵抗のシミュレーション結果。 第１実施形態に係る半導体装置の変形例を示す断面図。 第２実施形態に係る半導体装置の製造方法を説明する図。
以下、図面を参照して本発明に係る実施形態を説明する。本実施形態は、本発明を限定するものではない。
（第１実施形態）
図１は、第１実施形態に係る半導体装置を模式的に示す斜視図である。半導体装置１は半導体パワーパッケージに適用することができる。半導体装置１は、パッケージ１０と、リードフレーム２０、３０と、を備える。リードフレーム２０は、パッケージ１０の側面から引き出されている。リードフレーム３０の一部は、パッケージ１０によって封止されており、また、他の一部、すなわち表面の少なくとも一部は、パッケージ１０の上面から露出してその上面の一部を構成している。パッケージ１０の下面には、後に説明される他のリードフレームが設けられている。パッケージ１０は樹脂からなり、リードフレーム２０の一部、３０の一部と、後に説明される半導体チップ等をトランスファモールド法により封止している。以上のように半導体装置１は、両面放熱タイプの半導体パッケージを構成している。
図２は、図１に示す半導体装置１の切断線ＩＩ−ＩＩに沿った断面図である。半導体装置１は、パッケージ１０と、リードフレーム２０、３０、４０と、半導体チップ５０と、第１の層である金属層６０と、金属層７０と、半田８０と、ワイヤ９０を備える。リードフレーム２０、３０、４０は、銅を主材料として形成されている。なおアルミニウム等の金属材料を用いてもよいが、半田接続可能なように、アルミニウム表面にニッケルおよび金をめっきしておく必要がある。リードフレーム４０の一部は、リードフレーム３０と同様にパッケージ１０によって封止されており、また、他の一部、すなわち表面の少なくとも一部は、パッケージ１０の下面から露出してその下面の一部を構成している。半導体チップ５０は例えばＩＧＢＴである。半導体チップ５０の第１面である上面５０１には、金属層６０の下面が直接接して、すなわち物理的に接続して設けられている。また、金属層６０の上面は半田８０を介してリードフレーム３０に接続されている。半導体チップ５０の第２面である下面５０２には、金属層７０の上面が直接接して設けられている。また、金属層７０の下面は半田８０を介してリードフレーム４０に接続されている。すなわち、リードフレーム３０、４０は金属層６０、７０で挟まれた半導体チップ５０を半田８０を介して挟むように設けられている。ワイヤ９０は、半導体チップ５０の上面５０１の一部とリードフレーム２０とを接続するように設けられている。
図３は第１実施形態に係る半導体装置１の内部を説明するための図であり、半導体チップ５０に金属層６０、７０を設けた構造の斜視図である。図４は、図３に示す半導体装置１の内部構造を示す平面図である。図３、図４に示すように、半導体チップ５０の上面５０１には、第１電極であるゲート電極５０３と、第２電極であるエミッタ電極５０４と、が設けられている。ゲート電極５０３とエミッタ電極５０４はアルミニウムで形成されてもよい。ゲート電極５０３は上面５０１の中央端部に設けられている。エミッタ電極５０４はゲート電極５０３から間隔を空けて、かつゲート電極５０３の３方向を囲うように設けられている。なお、図３、図４においてエミッタ電極５０４は、金属層６０の直下に設けられている。エミッタ電極５０４は４つに分離されて設けられており、エミッタ電極５０４間には、図示しないゲート配線が設けられている。また、半導体チップ５０の周縁部には、図示しないガードリングが設けられている。なお、エミッタ電極５０４は５つ以上、あるいは３つ以下に分離されていてもよい。エミッタ電極５０４上に設けられた金属層６０は銅を主材料として、電界めっきあるいは無電界めっきにより形成されている。金属層６０は、エミッタ電極５０４に直接接し、すなわち物理的に接続し、かつエミッタ電極５０４の上面全体を覆うように設けられている。半導体チップ５０の下面５０２の全面には、コレクタ電極５０５が設けられている。コレクタ電極５０５はアルミニウムで形成されてもよい。コレクタ電極５０５上に設けられた金属層７０は、金属層６０と同様に銅を主材料として、電界めっきあるいは無電界めっきにより形成されている。金属層７０は、コレクタ電極５０５上面に直接接し、すなわち物理的に接続し、かつ上面全体を覆うように設けられている。
ワイヤ９０の頂部９０１よりリードフレーム３０側に位置する。更には、金属層６０の厚みは、半導体チップ５０の上面５０１、すなわち、エミッタ電極５０４の上面からワイヤ９０の頂部までの長さよりも大きい。金属層６０の厚みは５０μｍ以上であり、より好ましくは１００μｍ以上である。これにより、ワイヤ９０の頂部９０１がリードフレーム３０に接触したり、あるいは、金属層６０とリードフレーム３０との間からはみ出した半田８０にワイヤ９０が接触することがなく、ショートを防止することができる。また、金属層６０は、エミッタ電極５０４に直接接し、すなわち物理的に接続し、かつエミッタ電極５０４の上面全体を覆うように設けられている。すなわち、金属層６０の周縁部は、エミッタ電極の周縁部と一致するよう設けることができる。これにより、エミッタ電極５０４の上面全体から金属層６０へ効率よく伝熱を行うことができ、半導体チップ５０から効率よく放熱することができる。金属層６０とエミッタ電極５０４との間には従来のような半田が存在しない。従って銅より熱伝導率の低い半田が熱伝導を律速することがなく、また、半田とゲート電極５０３、あるいは半田とエミッタ電極５０４に対し電位の異なる部分とによるショートの問題は生じない。金属層６０の主材料である銅は電界めっきあるいは無電界めっきにより形成されるため、上記のように、５０μｍ以上の厚膜に形成可能であり、かつ半田を用いることなく直接エミッタ上に形成され得る。一方、例えばアルミニウムは、銅より低い熱伝導率を有している。また、スパッタによるアルミニウムの成膜工程において、厚膜レジストの形成及び除去が困難であるため、５０μｍ以上の厚膜のアルミニウムを金属層として形成することは困難である。以上の構造により、ショートを防止して信頼性を保ちつつ、放熱効率を向上させることができる。半導体チップ５０の下面５０２には、金属層６０と同じ材料で、かつ略同じ厚みを有する金属層７０が設けられている。これにより、半導体チップ５０の半導体基板（例えばＳｉ、ＳｉＣなど）と金属層６０との線膨張係数の差により生じる応力を、半導体基板５０と金属層７０との間で生じる応力で相殺することによって、半導体チップ５０の反りを緩和することができる。また、金属層７０は、半導体チップ５０の下面５０２に設けられたコレクタ電極５０５に直接接して、すなわち物理的に接続して、コレクタ電極５０５の上面全体を覆うように設けることができる。すなわち、金属層７０の周縁部は、コレクタ電極５０５の周縁部と面一になるよう設けることができる。これにより、コレクタ電極５０５の上面全体から金属層７０へ効率よく放熱を行うことができる。金属層６０、７０は、半導体チップの上下面５０１、５０２にそれぞれ直接接して設けられており、半田を介していない。一方、従来構造の場合、半導体チップと金属層との間、金属層とリードフレームとの間の接続に半田が用いられるため、リフロー時における半導体チップや金属層の姿勢制御が困難になる。第１実施形態の半導体装置１では、半導体チップ５０に直接金属層６０が設けられるため、半導体チップに対する金属層の姿勢制御を考慮する必要がなく、よって信頼性の高い半導体装置を得ることができる。
図６は、第１実施形態に係る熱抵抗のシミュレーション結果である。このシミュレーションにおいては、アルミニウムを主材料とするエミッタ電極上に金属層を設けていない従来構造が基準構造として用いられる。また、エミッタ電極上に銅を主材料とする金属層を設けた構造が検討構造として用いられる。横軸を時間（ｓｅｃ）、縦軸を基準構造の表面温度に対する検討構造の表面温度比をΔＴｊ比とし、検討構造の時間経過に伴う表面温度変化率、すなわち熱抵抗の変化率を示している。なお、検討構造の金属層の厚みは１０μｍ、２０μｍ、５０μｍであり、エミッタ電極と接する面に対し反対側の面は断熱しており、放熱はないものとする。グラフから分かるように、金属層の厚みが５０μｍの場合にΔＴｊ比は最小値をとり、約６２％である。半導体チップから発生する熱を短時間で効率よく金属層に吸収していることがわかる。基準構造の場合、高い熱抵抗のために、０．０１ミリ秒オーダーで半導体チップが短絡して破壊に至る可能性がある。半導体装置には加熱防止保護回路を備えている場合があるが、その作動より前に半導体チップの破壊が生じてしまう。しかしながら、金属層の厚みが５０μｍの場合、０．０１ミリ秒時のΔＴｊ比は５０％を超えている。従って、基準構造に比べ半導体チップからの熱が短時間で効率よく金属層に吸収され、加熱防止保護回路の作動前の半導体チップの破壊を防止できる。なお、０．０１ミリ秒経過以降は、加熱防止保護回路が作動することによって過剰な加熱を防止することができる。以上から本実施形態に係る半導体装置１において、金属層の厚みを５０μｍ以上とすることが好ましい。また、ワイヤの頂部にリードフレームが接しないよう十分な間隔を設けるためにも、厚みが１００μｍ以上であるとより好ましい。これにより、ショートを防止して信頼性を向上させることができるとともに、短時間での放熱性をより向上させることができる。
以上述べたように、本実施形態に係る半導体装置１は、銅を主材料とする金属層６０、７０を半導体チップの上下の電極に直接接し、すなわち物理的に接続するように設け、かつ電極上面全体に設けることで、効率よく放熱を行うことができる。また、金属層が上述した厚みを有することで、ワイヤ９０へのリードフレーム３０や半田８０の接触を防止することができ、信頼性の高い半導体装置を提供することができる。また同時に、加熱防止保護回路の作動より前の、短時間での放熱性を向上させることができる。本実施形態に係る半導体装置１において、リードフレーム３０、４０と金属層６０、７０との接続に半田８０を用いたが、ＡｇナノペーストやＣｕＳｎのような合金を用いた金属拡散接続でも構わない。また半導体チップ５０の材料はシリコンを用いたが、ＧａＮあるいはＳｉＣ等でもよい。またチップはＩＧＢＴを用いたが、ＭＯＳＦＥＴ、ＨＥＭＴ、ダイオードその他であってもかまわない。半導体装置１は１チップを封止したモジュールについて説明したが、２個以上を封止したモジュールであってもかまわない。また、ＩＧＢＴとＦＲＤのように、種類の異なるチップを複数封止してもかまわない。半導体チップを複数封止したモジュールの場合、複数の半導体チップの上面の電位が同じであれば、モジュールの表面に露出したリードフレームと、リードフレームに半田を介して接続された金属層とを複数のチップで共有することができる。つまり、図２に示す半導体装置と同様な外観であって、内部に複数のチップを有するモジュールを提供することができる。このモジュールでは、上面に許容される範囲の最大寸法のリードフレームを搭載することができる。また、例えば、結晶欠陥の多いＳｉＣ基板を用いて形成される半導体チップは、サイズの上限を制限されるが、本実施形態のモジュールを用いることによって、上面に許容される範囲の最大寸法のリードフレームを複数のＳｉＣからなる半導体チップで共用することができる。
（第１実施形態の変形例）
第１実施形態に係る半導体装置１において、半導体チップ５０のゲート電極５０３は、ワイヤ９０によりリードフレーム２０に接続されていた。本変形例では、図７に示すように、リードフレーム１１０を半田（図示せず）を介してリフローによって半導体チップ５０のゲート電極５０３に接続している。この場合において、金属層６０の上面６０１の位置は、パッケージ１０内部におけるリードフレーム１１０の上面１１１の位置より高い。すなわち、金属層６０の上面６０１はリードフレーム１１０の上面１１１に対してリードフレーム３０側に位置する。更には、金属層６０の厚みは、半導体チップ５０の上面５０１からリードフレーム１１０の上面１１１、すなわち、パッケージ１０の内部におけるリードフレーム１１０の頂部１１１、までの距離よりも大きい。金属層６０の厚みは５０μｍ以上であり、より好ましくは１００μｍ以上である。これにより第１実施形態と同様に、リードフレーム１１１はリードフレーム３０や半田８０に接することなく、よってショートを避けることができる。その他、第１実施形態と同様の効果を有する。
（第２実施形態）
第１実施形態では、金属層６０、７０は、半導体チップ５０を電界めっき、あるいは無電界めっきすることにより形成された。第２実施形態では、ウエハを半導体チップに分割する前に、銅板状の金属層がウエハに高温圧着される。図８は第２実施形態に係る半導体装置を形成する工程を示す。ウエハ１２０にＩＧＢＴが形成された後、ウエハ１２０の上面に金属層６０２が形成される。金属層６０２は銅を主材料とし、予めＩＧＢＴのエミッタ電極上面の形状と同じ形状になるよう、また、５０μｍ以上、好ましくは１００μｍ以上の厚みを有するようパターニングされている。ウエハ１２０の下面全体には、ウエハ１２０と同じ平面形状の銅板状の金属層７０２が設けられる。金属層７０２の厚みは、金属層６０２の厚みと略同じである。金属層６０２、７０２はＡｕＳｎ合金を介してウエハ１２０に高温圧着される。この後、ダイシングによって金属層６０２、７０２に挟まれた半導体チップ５０が得られる。なお、ダイシングラインに対応する金属層７０２の一部をエッチングで除去することによって、ウエハ１２０は容易にダイシング可能である。第２実施形態のその後の工程は、第１実施形態の対応する工程と同様でよい。以上の製造工程により形成された第２実施形態に係る半導体装置は、第１実施形態に係る半導体装置と同様の効果を有する。
（第２実施形態の変形例）
第２実施形態では、ウエハ１２０の上面に形成される金属層６０２は予めパターニングされていた。第２実施形態の変形例では、予めパターニングされていない板状の銅板をＡｕＳｎ合金を介してウエハ１２０に高温圧着する。その後、ウエハ１２０の上面のゲート電極部分、チップ周辺部分、ダイシングライン部分に対応する銅板の一部をエッチングによって除去し、所望の形状の金属層を得る。ダイシングライン部分に沿ってダイシングすることにより、半導体チップが形成される。なお、ダイシングラインに対応するウエハ１２０下面の金属層７０２の一部を、予めエッチングによって除去しておくと、ウエハ１２０はより容易にダイシングされる。第２実施形態の変形例のその後の工程は、第１実施形態の対応する工程と同様でよい。以上の製造工程により形成された第２実施形態の変形例に係る半導体装置は、第１実施形態に係る半導体装置と同様の効果を有する。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。
１０ パッケージ
２０、３０、４０、１１０ リードフレーム
５０ 半導体チップ
５０１、６０１ 上面
５０２ 下面
５０３ ゲート電極
５０４ エミッタ電極
５０５ コレクタ電極
６０、７０、６０２、７０２ 金属層
８０ はんだ
９０ ワイヤ
９０１、１１１ 頂部
１２０ ウエハ

Claims (8)

  1. 第１の電極と、第２の電極と、を第１の面に有する半導体チップと、
    前記第１の電極に電気的に接続された第１の配線と、
    前記第２の電極に直接接続されるとともに、前記半導体チップの前記第１の面から前記第１の配線の頂部までの長さより大きい厚みを有し、銅を主材料とする第１の層と、
    前記第１の層上に設けられた第２の配線と、
    前記半導体チップ、前記第１の配線の少なくとも一部、前記第２の配線の一部、前記第１の層、を封止するとともに、前記第２の配線の他の一部を露出するよう設けられた半導体パッケージと、
    を備える半導体装置。
  2. 前記半導体装置は、
    前記半導体チップの前記第１の面に対し反対側の第２の面に直接接続して設けられ、前記第１の層と略同じ厚みを有し、銅を主材料とする第２の層と、
    前記２の層に電気的に接続し、前記半導体パッケージから露出した部分を有する第３の配線と、
    を更に備える請求項１に記載の半導体装置。
  3. 前記半導体パッケージは表面実装型である請求項１に記載の半導体装置。
  4. 前記第１の層は５０μｍ以上の厚みを有する、請求項１に記載の半導体装置。
  5. 前記第１の層は１００μｍ以上の厚みを有する、請求項１に記載の半導体装置。
  6. 前記第１の層は電界めっき、あるいは無電界めっきにより形成されている、請求項１に記載の半導体装置。
  7. 前記第１の層は銀ナノペーストを介して前記第１の配線に接続されている、請求項１に記載の半導体装置。
  8. 前記第１の層はＡｕＳｎ合金層を介して前記第１の電極に接続されている、請求項１に記載の半導体装置。
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