JP2018093114A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2018093114A JP2018093114A JP2016236918A JP2016236918A JP2018093114A JP 2018093114 A JP2018093114 A JP 2018093114A JP 2016236918 A JP2016236918 A JP 2016236918A JP 2016236918 A JP2016236918 A JP 2016236918A JP 2018093114 A JP2018093114 A JP 2018093114A
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- Prior art keywords
- semiconductor device
- layer
- semiconductor chip
- metal layer
- electrode
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 8
- 238000007772 electroless plating Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 description 74
- 239000002184 metal Substances 0.000 description 74
- 229910000679 solder Inorganic materials 0.000 description 22
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910016347 CuSn Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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Abstract
【解決手段】本実施形態による半導体装置は、第1の電極と、第2の電極と、を第1の面に有する半導体チップと、前記第1の電極に接続された第1の配線と、前記第2の電極に直接接続され、前記半導体チップの前記第1の面から前記第1の配線の頂部までの長さより大きい厚みを有し、銅を主材料とする第1の層と、前記第1の層上に設けられた第2の配線と、前記半導体チップ、前記第1の配線、前記第1の層、前記第2の配線の一部を封止するとともに、前記第2の配線の他の一部を露出するよう設けられた半導体パッケージと、を備える。
【選択図】図2
Description
図1は、第1実施形態に係る半導体装置を模式的に示す斜視図である。半導体装置1は半導体パワーパッケージに適用することができる。半導体装置1は、パッケージ10と、リードフレーム20、30と、を備える。リードフレーム20は、パッケージ10の側面から引き出されている。リードフレーム30の一部は、パッケージ10によって封止されており、また、他の一部、すなわち表面の少なくとも一部は、パッケージ10の上面から露出してその上面の一部を構成している。パッケージ10の下面には、後に説明される他のリードフレームが設けられている。パッケージ10は樹脂からなり、リードフレーム20の一部、30の一部と、後に説明される半導体チップ等をトランスファモールド法により封止している。以上のように半導体装置1は、両面放熱タイプの半導体パッケージを構成している。
第1実施形態に係る半導体装置1において、半導体チップ50のゲート電極503は、ワイヤ90によりリードフレーム20に接続されていた。本変形例では、図7に示すように、リードフレーム110を半田(図示せず)を介してリフローによって半導体チップ50のゲート電極503に接続している。この場合において、金属層60の上面601の位置は、パッケージ10内部におけるリードフレーム110の上面111の位置より高い。すなわち、金属層60の上面601はリードフレーム110の上面111に対してリードフレーム30側に位置する。更には、金属層60の厚みは、半導体チップ50の上面501からリードフレーム110の上面111、すなわち、パッケージ10の内部におけるリードフレーム110の頂部111、までの距離よりも大きい。金属層60の厚みは50μm以上であり、より好ましくは100μm以上である。これにより第1実施形態と同様に、リードフレーム111はリードフレーム30や半田80に接することなく、よってショートを避けることができる。その他、第1実施形態と同様の効果を有する。
第1実施形態では、金属層60、70は、半導体チップ50を電界めっき、あるいは無電界めっきすることにより形成された。第2実施形態では、ウエハを半導体チップに分割する前に、銅板状の金属層がウエハに高温圧着される。図8は第2実施形態に係る半導体装置を形成する工程を示す。ウエハ120にIGBTが形成された後、ウエハ120の上面に金属層602が形成される。金属層602は銅を主材料とし、予めIGBTのエミッタ電極上面の形状と同じ形状になるよう、また、50μm以上、好ましくは100μm以上の厚みを有するようパターニングされている。ウエハ120の下面全体には、ウエハ120と同じ平面形状の銅板状の金属層702が設けられる。金属層702の厚みは、金属層602の厚みと略同じである。金属層602、702はAuSn合金を介してウエハ120に高温圧着される。この後、ダイシングによって金属層602、702に挟まれた半導体チップ50が得られる。なお、ダイシングラインに対応する金属層702の一部をエッチングで除去することによって、ウエハ120は容易にダイシング可能である。第2実施形態のその後の工程は、第1実施形態の対応する工程と同様でよい。以上の製造工程により形成された第2実施形態に係る半導体装置は、第1実施形態に係る半導体装置と同様の効果を有する。
第2実施形態では、ウエハ120の上面に形成される金属層602は予めパターニングされていた。第2実施形態の変形例では、予めパターニングされていない板状の銅板をAuSn合金を介してウエハ120に高温圧着する。その後、ウエハ120の上面のゲート電極部分、チップ周辺部分、ダイシングライン部分に対応する銅板の一部をエッチングによって除去し、所望の形状の金属層を得る。ダイシングライン部分に沿ってダイシングすることにより、半導体チップが形成される。なお、ダイシングラインに対応するウエハ120下面の金属層702の一部を、予めエッチングによって除去しておくと、ウエハ120はより容易にダイシングされる。第2実施形態の変形例のその後の工程は、第1実施形態の対応する工程と同様でよい。以上の製造工程により形成された第2実施形態の変形例に係る半導体装置は、第1実施形態に係る半導体装置と同様の効果を有する。
20、30、40、110 リードフレーム
50 半導体チップ
501、601 上面
502 下面
503 ゲート電極
504 エミッタ電極
505 コレクタ電極
60、70、602、702 金属層
80 はんだ
90 ワイヤ
901、111 頂部
120 ウエハ
Claims (8)
- 第1の電極と、第2の電極と、を第1の面に有する半導体チップと、
前記第1の電極に電気的に接続された第1の配線と、
前記第2の電極に直接接続されるとともに、前記半導体チップの前記第1の面から前記第1の配線の頂部までの長さより大きい厚みを有し、銅を主材料とする第1の層と、
前記第1の層上に設けられた第2の配線と、
前記半導体チップ、前記第1の配線の少なくとも一部、前記第2の配線の一部、前記第1の層、を封止するとともに、前記第2の配線の他の一部を露出するよう設けられた半導体パッケージと、
を備える半導体装置。 - 前記半導体装置は、
前記半導体チップの前記第1の面に対し反対側の第2の面に直接接続して設けられ、前記第1の層と略同じ厚みを有し、銅を主材料とする第2の層と、
前記2の層に電気的に接続し、前記半導体パッケージから露出した部分を有する第3の配線と、
を更に備える請求項1に記載の半導体装置。 - 前記半導体パッケージは表面実装型である請求項1に記載の半導体装置。
- 前記第1の層は50μm以上の厚みを有する、請求項1に記載の半導体装置。
- 前記第1の層は100μm以上の厚みを有する、請求項1に記載の半導体装置。
- 前記第1の層は電界めっき、あるいは無電界めっきにより形成されている、請求項1に記載の半導体装置。
- 前記第1の層は銀ナノペーストを介して前記第1の配線に接続されている、請求項1に記載の半導体装置。
- 前記第1の層はAuSn合金層を介して前記第1の電極に接続されている、請求項1に記載の半導体装置。
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WO2020166251A1 (ja) * | 2019-02-13 | 2020-08-20 | 株式会社デンソー | 半導体装置 |
WO2022160245A1 (zh) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | 集成电路封装件及其制备方法和终端 |
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