JP2018014395A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
<半導体装置の構造>
以下に、図1および図2を用いて、本実施の形態1の半導体装置の構造について説明する。図1は、本実施の形態の半導体装置を示す平面図である。図2は、本実施の形態の半導体装置を示す断面図であり、図1のA−A線における断面図である。本実施の形態の半導体装置は、pチャネル型のLDMOSトランジスタを有する半導体装置である。なお、LDMOSトランジスタ(電界効果トランジスタ)は、横型パワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)と呼ばれることもある。当該LDMOSは、例えば15〜800Vで駆動する高耐圧MOSFETである。
以下に、図18および図19に示す比較例の半導体装置を参照して、本実施の形態の半導体装置の構造の効果について説明する。図18および図19は、比較例である半導体装置を示す断面図である。なお、図18および図19に示すLDMOSの構造は、ゲート電極の構造を除き、本実施の形態の半導体装置と同様の構造を有している。
以下に、図3〜図9を用いて、本実施の形態の半導体装置の製造方法について説明する。図3〜図9は、本実施の形態の半導体装置の製造工程中における断面図である。
本実施の形態の半導体装置の製造方法では、図1、図2を用いて上述した半導体装置と同様の効果を得ることができる。すなわち、絶縁膜破壊の直接的な原因となる高エネルギーの正孔をゲート電極GE内で発生させないようにするため、素子分離領域EIと隣接する半導体基板SBの主面の直上のシリコン膜SGを除去し、代わりに金属膜MGを形成している。これにより、高エネルギーの電子がゲート電極GE内に注入された際に、高エネルギーの正孔が発生することのないLDMOSを実現することができる。よって、AHR機構またはAHI機構による絶縁破壊を抑制することができる。
以下に、図10を用いて、本実施の形態1の変形例1である半導体装置の構造について説明する。図10は、本実施の形態1の変形例1である半導体装置を示す平面図である。
本実施の形態1の半導体装置の変形例2を示す断面図である図11に示すように、ソース領域SR側のシリコン膜SGを残して、ドレイン領域DR側のゲート電極GEを全て金属膜MGにより構成してもよい。
本実施の形態1の半導体装置の変形例3を示す断面図である図12に示すように、溝D1内に埋め込まれる金属膜MGは、溝D1内を完全に埋め込んでいなくてもよい。つまり、金属膜MGの膜厚は、シリコン膜SGより小さく、かつ、溝D1の幅の1/2より小さくてもよい。
以下に、図13〜図15を用いて、本実施の形態2の半導体装置の製造方法および半導体装置の構造について説明する。図13〜図15は、本実施の形態2の半導体装置の製造方法を説明する断面図である。
以下に、図16および図17を用いて、本実施の形態3の半導体装置の製造方法および半導体装置の構造について説明する。図16および図17は、本実施の形態3の半導体装置の製造方法を説明する断面図である。
BX 埋込み酸化膜
D1、DT 溝
DR ドレイン領域
EI 素子分離領域
GE ゲート電極
GF ゲート絶縁膜
IF1、IF2 絶縁膜
MG 金属膜
POF オフセット領域
SB 半導体基板
SG シリコン膜
SL 半導体層
SR ソース領域
SSB 支持基板
Claims (15)
- 半導体基板と、
前記半導体基板の上面に形成され、それぞれp型の導電型を有するソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極のゲート長方向において、前記ゲート絶縁膜と前記ドレイン領域との間の前記半導体基板の前記上面に形成された第1溝内に埋め込まれた第1絶縁膜と、
を有し、
前記ゲート電極の一部は、前記第1絶縁膜の直上に形成されており、
前記ゲート電極は、
半導体膜と、
前記第1絶縁膜と前記ソース領域との間の前記半導体基板の前記上面の直上において前記半導体膜を貫通する第2溝内に埋め込まれ、前記半導体膜に電気的に接続された金属膜と、
を備えている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2溝内の前記金属膜の一部は、前記第1絶縁膜の直上に位置する、半導体装置。 - 請求項1記載の半導体装置において、
前記第2溝の側壁を覆う第2絶縁膜からなるサイドウォールが形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2溝内において、前記金属膜と前記ゲート絶縁膜との間には、第3絶縁膜が介在している、半導体装置。 - 請求項4記載の半導体装置において、
前記第3絶縁膜は、前記第2溝の底面および側壁を覆っており、前記ゲート絶縁膜よりも膜厚が小さい、半導体装置。 - 請求項1記載の半導体装置において、
前記ドレイン領域に電気的に接続され、前記第1溝の底面から、前記第1溝よりも前記ソース領域側の前記半導体基板の前記上面に亘って形成された第1p型半導体領域をさらに有し、
前記第1p型半導体領域のp型不純物濃度は、前記ドレイン領域のp型不純物濃度よりも低く、
前記第2溝は、前記第1絶縁膜に隣接する前記第1p型半導体領域の上面の直上に形成されている、半導体装置。 - 請求項6記載の半導体装置において、
前記ドレイン領域および前記第1p型半導体領域は、前記半導体基板内に形成された第2p型半導体領域を介して電気的に接続されており、
前記第2p型半導体領域のp型不純物濃度は、前記ドレイン領域のp型不純物濃度よりも低く、前記第1p型半導体領域のp型不純物濃度より高い、半導体装置。 - 請求項3記載の半導体装置において、
前記ドレイン領域に電気的に接続され、前記第1溝の底面から、前記第1溝よりも前記ソース領域側の前記半導体基板の前記上面に亘って形成された第1p型半導体領域をさらに有し、
前記第1p型半導体領域のp型不純物濃度は、前記ドレイン領域のp型不純物濃度よりも低く、
前記金属膜よりも前記ソース領域側に位置する前記半導体膜の一部は、前記第1p型半導体領域の直上に位置する、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜は、STI構造を有する、半導体装置。 - 半導体基板と、
前記半導体基板の上面に形成され、それぞれp型の導電型を有するソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極のゲート長方向において、前記ゲート絶縁膜と前記ドレイン領域との間の前記半導体基板の前記上面に形成された溝内に埋め込まれた第1絶縁膜と、
を有し、
前記ゲート電極の一部は、前記第1絶縁膜の直上に形成されており、
前記ゲート電極は、
前記第1絶縁膜と前記ソース領域との間の前記半導体基板の前記上面の直上に位置する金属膜と、
前記金属膜と電気的に接続され、前記ゲート長方向において前記金属膜と前記ソース領域との間に位置する半導体膜と、
を備えている、半導体装置。 - (a)半導体基板を用意する工程、
(b)前記半導体基板の上面に、p型の導電型を有するソース領域と、p型の導電型を有するドレイン領域とを形成する工程、
(c)前記半導体基板の前記上面に第1溝を形成し、前記第1溝内に埋め込まれた第1絶縁膜を形成する工程、
(d)前記第1絶縁膜と前記ソース領域との間の前記半導体基板の前記上面を覆うゲート絶縁膜を形成する工程、
(e)前記(d)工程の後、前記ソース領域および前記ドレイン領域の相互間の前記第1絶縁膜の直上と、前記第1絶縁膜および前記ソース領域の相互間の前記半導体基板の前記上面の直上とに亘って、半導体膜を形成する工程、
(f)前記半導体膜を貫通する第2溝を形成することで、前記第1絶縁膜と前記ソース領域との間の前記半導体基板の前記上面を、前記半導体膜から露出させる工程、
(g)前記第2溝内を埋め込む金属膜を形成することで、前記金属膜および前記半導体膜からなるゲート電極を形成する工程、
を有し、
前記ゲート電極、前記ソース領域およびドレイン領域は、電界効果トランジスタを構成する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
(f1)前記(f)工程の後、前記(g)工程の前に、前記第2溝の側壁を覆う第2絶縁膜からなるサイドウォールを形成する工程をさらに有する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
(f2)前記(f)工程の後、前記(g)工程の前に、前記第2溝の底面を覆う第3絶縁膜を形成する工程をさらに有する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第3絶縁膜は、前記第2溝の底面および側壁を覆っており、前記ゲート絶縁膜よりも膜厚が小さい、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
(a1)前記(a)工程の後、前記(d)工程の前に、前記半導体基板の前記上面にp型半導体領域を形成する工程をさらに有し、
前記(f)工程の後において、前記p型半導体領域は、前記第1溝の底面から、前記第1溝よりも前記ソース領域側の前記半導体基板の前記上面に亘って形成されており、
前記p型半導体領域のp型不純物濃度は、前記ドレイン領域のp型不純物濃度よりも低く、
前記第2溝は、前記第1絶縁膜に隣接する前記p型半導体領域の上面の直上に形成されている、半導体装置の製造方法。
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