JP2017507484A - 静電チャックおよびその作製方法 - Google Patents
静電チャックおよびその作製方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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Abstract
Description
本願は、2014年2月7日付で出願された米国仮特許出願第61/937,135号明細書の利益を主張するものであり、この仮特許出願の全教示は、参照によって本願に組み込まれる。
Claims (68)
- セラミックの構造要素と、
前記セラミックの構造要素の上に配置される少なくとも1つの電極と、
前記少なくとも1つの電極の上部に配置される表面誘電体層であって、基板を静電チャックに静電的にクランプするための電荷を形成するように前記電極における電圧によって活性化される表面層と、
を含む静電チャックであって、前記表面誘電体層は、
(i)前記少なくとも1つの電極の上部に配置される、約5μm未満の厚さのアモルファスアルミナの絶縁体層と、
(ii)前記絶縁体層の上部に配置される誘電体層の積層体と、
を含み、前記誘電体層の積層体は、
(a)酸窒化アルミニウムを含む少なくとも1つの誘電体層と、
(b)酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む少なくとも1つの誘電体層と、
を含む、静電チャック。 - 前記表面誘電体層が約1μm〜約250μmの範囲の厚さを有する、請求項1に記載の静電チャック。
- 前記表面誘電体層が窒化ケイ素の層を含む、請求項1または2に記載の静電チャック。
- 前記表面誘電体層が酸窒化ケイ素の層を含む、請求項1または2に記載の静電チャック。
- 前記表面誘電体層が1つ以上の電気絶縁層から構成される、請求項1〜4のいずれか一項に記載の静電チャック。
- 少なくとも1つの電気絶縁層が、原子層堆積法の薄膜堆積技法によって堆積される、請求項5に記載の静電チャック。
- 少なくとも1つの電気絶縁層が、化学蒸着法、プラズマ強化化学蒸着法、物理蒸着法、電子ビーム堆積法、スプレー被膜法、大気圧プラズマ堆積法、高圧プラズマ堆積法、電気化学堆積法およびスパッタ堆積法からなる群から選択される薄膜堆積技法によって堆積される、請求項5に記載の静電チャック。
- 前記表面誘電体層が、アルミナ、酸窒化アルミニウム、窒化アルミニウム、酸化ケイ素、酸窒化ケイ素、窒化ケイ素、遷移金属酸化物、遷移金属酸窒化物、レアアース酸化物およびレアアース酸窒化物からなる群から選択される材料から構成される、請求項5に記載の静電チャック。
- 前記表面誘電体層が、多結晶薄膜、アモルファス薄膜および準結晶薄膜からなる群から選択される材料の1つ以上の種類から構成される、請求項5に記載の静電チャック。
- 前記表面誘電体層がコンフォーマルである、請求項5に記載の静電チャック。
- 前記表面誘電体層が1μm〜250μmの間の厚さを有する、請求項5に記載の静電チャック。
- 前記表面誘電体層が10μm〜70μmの間の厚さを有する、請求項11に記載の静電チャック。
- 前記表面誘電体層が25μm〜50μmの間の厚さを有する、請求項12に記載の静電チャック。
- 前記表面誘電体層が、前記表面誘電体層の頂面および底面の間に印加される500Vを超えるピーク電圧を保持する能力を有する、請求項1〜13のいずれか一項に記載の静電チャック。
- 前記表面誘電体層が、前記表面誘電体層の頂面および底面の間に印加される1000Vを超えるピーク電圧を保持する能力を有する、請求項14に記載の静電チャック。
- 前記表面誘電体層が−150℃〜+750℃の温度において安定である、請求項1〜15のいずれか一項に記載の静電チャック。
- 前記表面誘電体層が、次の機能、すなわち、(1)高力誘電体バリア、(2)本質的に金属汚染が低くかつ低粒子源の誘電体層、(3)プラズマエッチングの抵抗表面、および(4)摩耗抵抗表面の少なくともいずれか1つを遂行する、請求項1〜16のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が、原子層堆積法によって前記少なくとも1つの電極の上部に堆積される、請求項1〜17のいずれか一項に記載の静電チャック。
- 前記絶縁体層が、約0.5μm〜約2μmの範囲の厚さを有する、請求項18に記載の静電チャック。
- 前記絶縁体層の厚さが約1μmである、請求項19に記載の静電チャック。
- 前記誘電体層の積層体が、
i)前記絶縁体層の上部に堆積される第1誘電体層であって、酸化ケイ素を含む第1誘電体層と、
ii)前記第1誘電体層の上部に第2誘電体層として堆積される少なくとも1つの誘電体層であって、酸窒化アルミニウムを含む少なくとも1つの誘電体層と、
iii)前記第2誘電体層の上部に第3誘電体層として堆積される少なくとも1つの誘電体層であり、酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む少なくとも1つの誘電体層であって、酸化ケイ素を含む第3誘電体層と、
を含む、請求項1〜20のいずれか一項に記載の静電チャック。 - 前記第1誘電体層が約10μm〜約50μmの範囲の厚さを有する、請求項21に記載の静電チャック。
- 前記第1誘電体層の厚さが約20μmである、請求項22に記載の静電チャック。
- 前記第2誘電体層が約1μm〜約20μmの範囲の厚さを有する、請求項21に記載の静電チャック。
- 前記第2誘電体層の厚さが約10μmである、請求項24に記載の静電チャック。
- 前記第3誘電体層が約10μm〜約50μmの範囲の厚さを有する、請求項21に記載の静電チャック。
- 前記第3誘電体層の厚さが約20μmである、請求項26に記載の静電チャック。
- 前記セラミックの構造要素がアルミナを含む、請求項1〜27のいずれか一項に記載の静電チャック。
- 前記セラミックの構造要素が窒化アルミニウムを含む、請求項1〜27のいずれか一項に記載の静電チャック。
- 前記セラミックの構造要素が窒化ケイ素を含む、請求項1〜27のいずれか一項に記載の静電チャック。
- 前記少なくとも1つの電極が、アルミニウム、チタン、モリブデン、銀、白金、金、ニッケル、タングステン、クロム、バナジウム、ルテニウム、鉄、パラジウム、ニッケル−コバルト−鉄合金、マンガンおよび窒化物の少なくともいずれか1つを含む、請求項1〜30のいずれか一項に記載の静電チャック。
- 前記少なくとも1つの電極が窒化チタンを含む、請求項31に記載の静電チャック。
- 前記少なくとも1つの電極が約0.5μm未満の厚さを含む、請求項1〜32のいずれか一項に記載の静電チャック。
- 前記少なくとも1つの電極が約0.25μm未満の厚さを含む、請求項1〜33のいずれか一項に記載の静電チャック。
- 前記表面誘電体層がイットリアおよびジルコニアの少なくともいずれかを含む、請求項1〜34のいずれか一項に記載の静電チャック。
- 前記表面誘電体層が窒化ケイ素を含む、請求項1〜35のいずれか一項に記載の静電チャック。
- 前記誘電体層の積層体が、
i)酸窒化アルミニウムを含む少なくとも1つの誘電体層であって、前記絶縁体層の上部に配置される第1誘電体層である少なくとも1つの誘電体層と、
ii)酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む少なくとも1つの誘電体層であって、前記第1誘電体層の上部に配置される第2誘電体層である少なくとも1つの誘電体層と、
を含む、請求項1〜36のいずれか一項に記載の静電チャック。 - 前記第1誘電体層の厚さが約10μmである、請求項37に記載の静電チャック。
- 前記第2誘電体層が約40μm〜約50μmの範囲の厚さを有する、請求項37または38に記載の静電チャック。
- 前記静電チャックの基板接触表面が複数の突出部を含み、前記突出部は、前記複数の突出部を取り囲む前記静電チャックの基板接触表面の部分を超える高さに延びている、請求項1〜39のいずれか一項に記載の静電チャック。
- 前記複数の突出部が約3μm〜約15μmの間の高さを含む、請求項40に記載の静電チャック。
- 前記複数の突出部が約6μm〜約8μmの間の高さを含む、請求項41に記載の静電チャック。
- 前記複数の突出部が、エッチング加工された突出部または堆積された突出部の少なくともいずれかを含む、請求項40に記載の静電チャック。
- 前記複数の突出部の少なくとも1つの突出部が、下部に位置する突出部の上部の基板接触表面被膜を含む、請求項40に記載の静電チャック。
- 前記基板接触表面被膜が、原子層堆積法によって堆積されるアルミナを含む、請求項44に記載の静電チャック。
- 原子層堆積法によって堆積されたアモルファスアルミナの拡散バリア層であって、前記誘電体層の積層体の上部に配置される拡散バリア層をさらに含む、請求項1〜45のいずれか一項に記載の静電チャック。
- 前記拡散バリア層が約0.2μm〜約1μmの範囲の厚さを有する、請求項46に記載の静電チャック。
- 前記拡散バリア層の上部に堆積された複数の突出部をさらに含む、請求項46に記載の静電チャック。
- 前記拡散バリア層の上部に堆積された複数の突出部が酸化ケイ素を含む、請求項48に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が少なくとも約200V/μmの最小絶縁耐力を有する、請求項1〜49のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が約200V/μm〜約400V/μmの間の最小絶縁耐力を有する、請求項50に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が少なくとも約500V/μmの最小絶縁耐力を有する、請求項50に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が少なくとも約800V/μmの最小絶縁耐力を有する、請求項50に記載の静電チャック。
- 酸窒化アルミニウムを含む前記少なくとも1つの誘電体層が少なくとも約50V/μmの最小絶縁耐力を含む、請求項1〜53のいずれか一項に記載の静電チャック。
- 酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む前記少なくとも1つの誘電体層が、少なくとも約70V/μmの最小絶縁耐力を含む酸化ケイ素を含む、請求項1〜54のいずれか一項に記載の静電チャック。
- 酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む前記少なくとも1つの誘電体層が、少なくとも約70V/μmの最小絶縁耐力を含む酸窒化ケイ素を含む、請求項1〜55のいずれか一項に記載の静電チャック。
- ヒータをさらに含む、請求項1〜56のいずれか一項に記載の静電チャック。
- 前記ヒータが、前記セラミックの構造要素の背面側に堆積されかつ封入される抵抗発熱体を含む、請求項57に記載の静電チャック。
- 少なくとも1つの埋め込み型温度センサをさらに含む、請求項57または58に記載の静電チャック。
- ガス孔、ガス流路、リフトピン孔および接地ピン孔の少なくともいずれか1つに丸められた端部を含む、請求項1〜59のいずれか一項に記載の静電チャック。
- 前記静電チャックの基板接触表面が、原子層堆積法による堆積アルミナ、酸化ケイ素、窒化ケイ素、酸窒化ケイ素およびケイ素富化酸化物の少なくともいずれか1つを含む、請求項1〜60のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が約2容積%未満の気孔率を含む、請求項1〜61のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が約1容積%未満の気孔率を含む、請求項1〜62のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が約0.5容積%未満の気孔率を含む、請求項1〜63のいずれか一項に記載の静電チャック。
- 前記アモルファスアルミナの絶縁体層が、式AlxOyのアルミナを含み、この場合、xは1.8〜2.2の範囲内、yは2.6〜3.4の範囲内である、請求項1〜64のいずれか一項に記載の静電チャック。
- 酸窒化アルミニウムを含む前記少なくとも1つの誘電体層が、式AlOxNyの酸窒化アルミニウムを含み、この場合、xは1.4〜1.8の範囲内、yは0.2〜0.5の範囲内である、請求項1〜65のいずれか一項に記載の静電チャック。
- 酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む前記少なくとも1つの誘電体層が、式SiOxの酸化ケイ素を含み、この場合、xは1.8〜2.4の範囲内である、請求項1〜66のいずれか一項に記載の静電チャック。
- 酸化ケイ素および酸窒化ケイ素の少なくともいずれかを含む前記少なくとも1つの誘電体層が、式SiOxNyの酸窒化ケイ素を含み、この場合、xは1.6〜2.0の範囲内、yは0.1〜0.5の範囲内である、請求項1〜67のいずれか一項に記載の静電チャック。
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JP2001525617A (ja) * | 1997-12-02 | 2001-12-11 | アプライド マテリアルズ インコーポレイテッド | セラミック静電チャック及びその製造方法。 |
JP2006517740A (ja) * | 2003-01-17 | 2006-07-27 | ゼネラル・エレクトリック・カンパニイ | ウェーハ加工装置及びその製造方法 |
WO2007043519A1 (ja) * | 2005-10-12 | 2007-04-19 | Shin-Etsu Chemical Co., Ltd. | 静電吸着機能を有するウエハ加熱装置 |
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KR102369706B1 (ko) | 2022-03-04 |
KR20160118259A (ko) | 2016-10-11 |
CN107078086A (zh) | 2017-08-18 |
TW201545268A (zh) | 2015-12-01 |
EP3103136B1 (en) | 2021-06-23 |
EP3103136A1 (en) | 2016-12-14 |
TWI663681B (zh) | 2019-06-21 |
CN107078086B (zh) | 2021-01-26 |
JP6527524B2 (ja) | 2019-06-05 |
SG10201806706VA (en) | 2018-09-27 |
US10497598B2 (en) | 2019-12-03 |
WO2015120265A1 (en) | 2015-08-13 |
US20160336210A1 (en) | 2016-11-17 |
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