JP2017225235A

JP2017225235A - Single-phase inverter device

Info

Publication number: JP2017225235A
Application number: JP2016118429A
Authority: JP
Inventors: 英伸楠本; Hidenobu Kusumoto
Original assignee: Meidensha Corp; Meidensha Electric Manufacturing Co Ltd
Current assignee: Meidensha Corp; Meidensha Electric Manufacturing Co Ltd
Priority date: 2016-06-15
Filing date: 2016-06-15
Publication date: 2017-12-21

Abstract

PROBLEM TO BE SOLVED: To provide a single-phase inverter device in which the occurrence of a surge voltage on a DC side is suppressed.SOLUTION: A single-phase inverter comprises: DC capacitors C1 to C4 connected in parallel: and semiconductor devices TRU, TRY, TRV, and TRX bridge-connected. In the single-phase inverter, the semiconductor devices TRU and TRY are closely provided, the TRV and the TRX are alternately closely provided so as to be separated from the TRU and the TRY. When turning on the semiconductor devices the TRU and the TRY or the TRV and the TRX, a P conductor 101 and an N conductor 102 are oppositely arranged, and an U conductor 103 and a V conductor 104 are oppositely arranged so that a magnetic flux caused by a current flowing from positive potential poles Pto Pof the DC capacitors C1 to C4 to the semiconductor device TRU or TRV and the magnetic flux caused by the current inflowing to negative potential poles Nto Nfrom the semiconductor device TRY or TRX are cancelled. Thus, a surge voltage on the DC side generated at a turn off of the semiconductor device is suppressed, and each semiconductor device is prevented from damage.SELECTED DRAWING: Figure 2

Description

本発明は、自己消弧型半導体素子を用いた電圧型インバータにおいて、素子が電流を遮断するときのサージ電圧を抑制する技術に関する。 The present invention relates to a technology for suppressing a surge voltage when an element cuts off a current in a voltage-type inverter using a self-extinguishing semiconductor element.

自己消弧型半導体素子、例えばＩＧＢＴを用いた単相インバータの構成例を図６、図７に示す。単相インバータの電気的接続を示す図６において、直流コンデンサＣの正電位極Ｐ，負電位極Ｎは、図示省略の直流電源の正極、負極に各々接続されている。 6 and 7 show a configuration example of a single-phase inverter using a self-extinguishing semiconductor element, for example, an IGBT. In FIG. 6 showing the electrical connection of the single-phase inverter, the positive potential pole P and the negative potential pole N of the DC capacitor C are respectively connected to the positive electrode and the negative electrode of a DC power supply (not shown).

直流コンデンサＣの正、負電位極Ｐ，Ｎ間には、半導体素子ＴＲＵ（第１の半導体素子）およびＴＲＸ（第２の半導体素子）が直列に接続されるとともに、半導体素子ＴＲＶ（第３の半導体素子）およびＴＲＹ（第４の半導体素子）が直列に接続されている。 Between the positive and negative potential poles P and N of the DC capacitor C, a semiconductor element TRU (first semiconductor element) and TRX (second semiconductor element) are connected in series, and a semiconductor element TRV (third semiconductor element) is connected. A semiconductor element) and TRY (fourth semiconductor element) are connected in series.

半導体素子ＴＲＵ，ＴＲＶ，ＴＲＸ，ＴＲＹは自己消弧型の半導体素子、例えばＩＧＢＴで構成されている。尚、直流コンデンサＣは、例えば図７に示すように、分割した４つの直流コンデンサＣ１〜Ｃ４を並列接続して構成されている。 The semiconductor elements TRU, TRV, TRX, TRY are constituted by self-extinguishing type semiconductor elements, for example, IGBTs. For example, as shown in FIG. 7, the DC capacitor C is configured by connecting four divided DC capacitors C1 to C4 in parallel.

半導体素子ＴＲＵおよびＴＲＹと、半導体素子ＴＲＶおよびＴＲＸを交互にオン、オフ制御することにより、半導体素子ＴＲＵおよびＴＲＸの共通接続点と、半導体素子ＴＲＶおよびＴＲＹの共通接続点との間に接続された負荷（図示省略）に交流電力が供給される。 By alternately turning on and off the semiconductor elements TRU and TRY and the semiconductor elements TRV and TRX, they are connected between the common connection point of the semiconductor elements TRU and TRX and the common connection point of the semiconductor elements TRV and TRY. AC power is supplied to a load (not shown).

図６の単相インバータの物理的接続を示す図７において、１は、平板状の平面導体からなるＰ導体であり、平板の長手方向一端側に、平板の長辺から直交する方向に突出して正極端子Ｐ１が設けられ、平板の長手方向他端側に、平板の長辺から直交する方向に突出して正極端子Ｐ２が設けられている。このＰ導体１は図示省略の直流電源の正極に接続されている。 In FIG. 7 showing the physical connection of the single-phase inverter of FIG. 6, reference numeral 1 denotes a P conductor made of a flat plate-like conductor, and protrudes in the direction perpendicular to the long side of the flat plate at one end side in the longitudinal direction of the flat plate. A positive electrode terminal P1 is provided, and a positive electrode terminal P2 is provided on the other end in the longitudinal direction of the flat plate so as to protrude in a direction orthogonal to the long side of the flat plate. The P conductor 1 is connected to the positive electrode of a DC power supply (not shown).

２は、平板状の平面導体からなるＮ導体であり、平板の長手方向一端側に、平板の長辺から直交する方向に突出して負極端子Ｎ１が設けられ、平板の長手方向他端側に、平板の長辺から直交する方向に突出して負極端子Ｎ２が設けられている。このＮ導体２は図示省略の直流電源の負極に接続されている。 2 is an N conductor made of a flat planar conductor, and is provided with a negative electrode terminal N1 projecting in a direction orthogonal to the long side of the flat plate on one end side in the longitudinal direction of the flat plate, and on the other longitudinal end side of the flat plate, A negative electrode terminal N2 is provided so as to protrude in a direction perpendicular to the long side of the flat plate. The N conductor 2 is connected to the negative electrode of a DC power supply (not shown).

Ｎ導体２はＰ導体１に対して、所定厚みを有した絶縁物５を介して対向配設されており、図７では、Ｐ導体１が奥側に配置され、Ｎ導体２が手前側に配置され、Ｐ導体１とＮ導体２の間に絶縁物５が介在する配置関係となっている。 The N conductor 2 is disposed opposite to the P conductor 1 via an insulator 5 having a predetermined thickness. In FIG. 7, the P conductor 1 is disposed on the back side, and the N conductor 2 is on the near side. The arrangement relationship is such that the insulator 5 is interposed between the P conductor 1 and the N conductor 2.

また正極端子Ｐ１，Ｐ２と負極端子Ｎ１，Ｎ２は各々対向しない位置に配設されており、負極端子Ｎ１，Ｎ２は、正極端子Ｐ１，Ｐ２の配設位置に対してＰ導体１の長手方向一端から他端へ向かう方向に所定距離ずれた位置に各々配設されている。 Further, the positive terminals P1, P2 and the negative terminals N1, N2 are arranged at positions not facing each other, and the negative terminals N1, N2 are one end in the longitudinal direction of the P conductor 1 with respect to the arrangement positions of the positive terminals P1, P2. Are respectively disposed at positions shifted by a predetermined distance in the direction from one end to the other end.

また、図７における、前記Ｐ導体１のさらに奥側の部位（Ｐ導体１の、絶縁物５と反対側に対向する部位）には、Ｐ導体１の長辺に沿って直流コンデンサＣ１〜Ｃ４が順次配設されている。 Further, in FIG. 7, DC capacitors C <b> 1 to C <b> 4 are disposed along the long side of the P conductor 1 at a portion on the further back side of the P conductor 1 (a portion facing the opposite side of the insulator 5 of the P conductor 1). Are sequentially arranged.

直流コンデンサＣ１〜Ｃ４の各正電位極Ｐ_C1〜Ｐ_C4は、該コンデンサに対向するＰ導体１に直接、接続固定されている。直流コンデンサＣ１〜Ｃ４の各負電位極Ｎ_C1〜Ｎ_C4は、当該負電位極の大きさよりやや大きい範囲で対向するＰ導体１および絶縁物５の部位を切り欠くか又は貫通させて、Ｎ導体２に接続固定されている。 The positive potential electrodes P _{C1 to} P _C4 of the DC capacitors C1 to _C4 are directly connected and fixed to the P conductor 1 facing the capacitors. The negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to _C4 are formed by cutting out or penetrating the portions of the P conductor 1 and the insulator 5 facing each other in a range slightly larger than the size of the negative potential electrode. 2 is connected and fixed.

尚、図７ではＮ導体２および絶縁物５にはハッチングを付与していない。また、Ｐ導体１とＮ導体２が絶縁物５を介して重なっている部位のＰ導体１にはハッチングを付与せず、重なっていない部位のＰ導体１にのみハッチングを付与している。 In FIG. 7, the N conductor 2 and the insulator 5 are not hatched. Further, the P conductor 1 in the portion where the P conductor 1 and the N conductor 2 overlap with each other through the insulator 5 is not given hatching, and the hatching is given only to the P conductor 1 in the portion not overlapping.

前記正極端子Ｐ１の配設位置に相当し、且つＰ導体１の長辺に直交する部位には半導体素子ＴＲＵが配設され、半導体素子ＴＲＵのコレクタは正極端子Ｐ１に接続されている。 A semiconductor element TRU is disposed at a position corresponding to the position where the positive electrode terminal P1 is disposed and orthogonal to the long side of the P conductor 1, and the collector of the semiconductor element TRU is connected to the positive electrode terminal P1.

前記負極端子Ｎ１の配設位置に相当し、且つＮ導体２の長辺に直交する部位には半導体素子ＴＲＸが配設され、半導体素子ＴＲＸのエミッタは負極端子Ｎ１に接続されている。 A semiconductor element TRX is disposed in a portion corresponding to the position where the negative electrode terminal N1 is disposed and orthogonal to the long side of the N conductor 2, and the emitter of the semiconductor element TRX is connected to the negative electrode terminal N1.

前記正極端子Ｐ２の配設位置に相当し、且つＰ導体１の長辺に直交する部位には半導体素子ＴＲＶが配設され、半導体素子ＴＲＶのコレクタは正極端子Ｐ２に接続されている。 A semiconductor element TRV is disposed at a position corresponding to the position where the positive terminal P2 is disposed and orthogonal to the long side of the P conductor 1, and the collector of the semiconductor element TRV is connected to the positive terminal P2.

前記負極端子Ｎ２の配設位置に相当し、且つＮ導体２の長辺に直交する部位には半導体素子ＴＲＹが配設され、半導体素子ＴＲＹのエミッタは負極端子Ｎ２に接続されている。 A semiconductor element TRY is disposed at a portion corresponding to the position where the negative electrode terminal N2 is disposed and orthogonal to the long side of the N conductor 2, and the emitter of the semiconductor element TRY is connected to the negative electrode terminal N2.

１１は、導電性の部材からなり、隣接配置された半導体素子ＴＲＵ，ＴＲＸに跨って配設されたＵ導体であり、半導体素子ＴＲＵのエミッタ、半導体素子ＴＲＸのコレクタおよび図示省略の負荷の一端が各々接続されている。 Reference numeral 11 denotes a U conductor made of a conductive member and disposed across adjacent semiconductor elements TRU and TRX. The emitter of the semiconductor element TRU, the collector of the semiconductor element TRX, and one end of a load (not shown) Each is connected.

１２は、導電性の部材からなり、隣接配置された半導体素子ＴＲＶ，ＴＲＹに跨って配設されたＶ導体であり、半導体素子ＴＲＶのエミッタ、半導体素子ＴＲＹのコレクタおよび図示省略の負荷の他端が各々接続されている。 Reference numeral 12 denotes a V conductor made of a conductive member and disposed across the adjacently arranged semiconductor elements TRV and TRY. The emitter of the semiconductor element TRV, the collector of the semiconductor element TRY, and the other end of the load (not shown) Are connected to each other.

上記のように、物理的に半導体素子ＴＲＵとＴＲＸ、半導体素子ＴＲＶとＴＲＹをペアで構成することで、Ｐ導体１、Ｎ導体２、Ｕ導体１１、Ｖ導体１２および絶縁物５の構成を容易なものとしている。 As described above, by physically configuring the semiconductor elements TRU and TRX and the semiconductor elements TRV and TRY as a pair, the configuration of the P conductor 1, the N conductor 2, the U conductor 11, the V conductor 12, and the insulator 5 is easy. It is supposed to be.

上記構成において、例えば半導体素子ＴＲＵおよびＴＲＹがオンされた場合、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１→正極端子Ｐ１→半導体素子ＴＲＵのコレクタ、エミッタ→Ｕ導体１１→負荷→Ｖ導体１２→半導体素子ＴＲＹのコレクタ、エミッタ→負極端子Ｎ２→Ｎ導体２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 In the above configuration, for example, when the semiconductor elements TRU and TRY are turned on, the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 → P conductor 1 → positive terminal P1 → collector and emitter of the semiconductor element TRU → U conductor 11 → Load → V conductor 12 → Collector and emitter of semiconductor element TRY → Negative electrode N2 → N conductor 2 → Current flows through the path of the negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to _C4 .

また、半導体素子ＴＲＶおよびＴＲＸがオンされた場合、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１→正極端子Ｐ２→半導体素子ＴＲＶのコレクタ、エミッタ→Ｖ導体１２→負荷→Ｕ導体１１→半導体素子ＴＲＸのコレクタ、エミッタ→負極端子Ｎ１→Ｎ導体２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 Further, when the semiconductor elements TRV and TRX are turned on, the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 → P conductor 1 → positive electrode terminal P2 → collector and emitter of the semiconductor element TRV → V conductor 12 → load → U conductor 11 → collector and emitter of semiconductor element TRX → negative electrode terminal N1 → N conductor 2 → current flows through the path of negative potential electrodes N _{C1 to} N _C4 of DC capacitors C1 to _C4 .

尚、電力変換器の主回路配線におけるインダクタンスの低減を図る技術は、例えば特許文献１に記載されている。 A technique for reducing inductance in the main circuit wiring of the power converter is described in Patent Document 1, for example.

特開２００６−２８０１９１号公報JP 2006-280191 A

図６、図７のように構成された単相インバータにおいて、サージ電圧を発生させるインダクタンスは、例えば半導体素子ＴＲＵおよびＴＲＸの直列回路側では、各直流コンデンサＣ１〜Ｃ４内部のインダクタンス、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4と半導体素子ＴＲＵのコレクタ間のＰ導体１のインダクタンス、半導体素子の内部のインダクタンス、半導体素子ＴＲＵのエミッタと半導体素子ＴＲＸのコレクタ間のＵ導体１１のインダクタンス、半導体素子ＴＲＸのエミッタと各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4間のＮ導体２のインダクタンスである。 In the single-phase inverter configured as shown in FIGS. 6 and 7, the inductance that generates the surge voltage is, for example, the inductance inside each DC capacitor C1 to C4 and each DC capacitor C1 on the series circuit side of the semiconductor elements TRU and TRX. The inductance of the P conductor 1 between the positive potential electrodes P _{C1 to} P _C4 of .about.C4 and the collector of the semiconductor element TRU, the inductance inside the semiconductor element, and the inductance of the U conductor 11 between the emitter of the semiconductor element TRU and the collector of the semiconductor element TRX. , The inductance of the N conductor 2 between the emitter of the semiconductor element TRX and the negative potential electrodes N _{C1 to} N _{C4 of the} DC capacitors C1 to _C4 .

前記Ｕ導体１１は、隣接配置された半導体素子ＴＲＵ，ＴＲＸに跨る比較的小さい面積で構成されるため、該Ｕ導体１１を通る電流によるインダクタンスは大きい。これはＶ導体１２においても同様である。 Since the U conductor 11 is configured with a relatively small area straddling adjacent semiconductor elements TRU and TRX, the inductance due to the current passing through the U conductor 11 is large. The same applies to the V conductor 12.

このように直流側の電流ループのインダクタンスが大きいため、半導体素子ＴＲＵ，ＴＲＹのターンオフ時、半導体素子ＴＲＶ，ＴＲＸのターンオフ時に発生するサージ電圧が大きくなり、各半導体素子が破損しやすくなる。 Thus, since the inductance of the current loop on the DC side is large, the surge voltage generated when the semiconductor elements TRU and TRY are turned off and when the semiconductor elements TRV and TRX are turned off becomes large, and each semiconductor element is easily damaged.

本発明は上記課題を解決するものであり、その目的は、直流側でのサージ電圧の発生を抑制した単相インバータ装置を提供することにある。 The present invention solves the above-described problems, and an object of the present invention is to provide a single-phase inverter device that suppresses generation of a surge voltage on the DC side.

上記課題を解決するための請求項１に記載の単相インバータ装置は、直流電源の正、負極端間に並列に接続した複数の直流コンデンサと、前記直流電源の正、負極端間に第１および第２の半導体素子を順次直列に接続した第１の直列回路と、前記直流電源の正、負極端間に第３および第４の半導体素子を順次直列に接続した第２の直列回路と、を備え、
前記第１の直列回路の第１および第２の半導体素子の共通接続点と、前記第２の直列回路の第３および第４の半導体素子の共通接続点との間に交流出力を得る単相インバータにおいて、
第１の半導体素子および第４の半導体素子を互いに近設し、第３の半導体素子および第２の半導体素子を前記第１および第４の半導体素子から離間して互いに近設し、
前記直流電源の正極および前記各直流コンデンサの正電位極が接続される平面導体であって、該平面導体の一端側に設けられ、前記第１の半導体素子のコレクタが接続された第１の正極端子と、該平面導体の他端側に設けられ、前記第３の半導体素子のコレクタが接続された第２の正極端子とを有した第１の導体と、
前記第１の導体に対して所定距離隔てて対向配設され、前記直流電源の負極および前記各直流コンデンサの負電位極が接続される平面導体であって、該平面導体の一端側で且つ前記第１の正極端子の近傍に設けられ、前記第４の半導体素子のエミッタが接続された第１の負極端子と、該平面導体の他端側で且つ前記第２の正極端子の近傍に設けられ、前記第２の半導体素子のエミッタが接続された第２の負極端子と、を有した第２の導体と、
を備えたことを特徴している。 The single-phase inverter device according to claim 1 for solving the above-described problem is a plurality of DC capacitors connected in parallel between the positive and negative ends of a DC power supply, and a first between the positive and negative ends of the DC power supply. And a first series circuit in which the second semiconductor elements are sequentially connected in series, and a second series circuit in which the third and fourth semiconductor elements are sequentially connected in series between the positive and negative ends of the DC power supply, With
A single phase that obtains an AC output between a common connection point of the first and second semiconductor elements of the first series circuit and a common connection point of the third and fourth semiconductor elements of the second series circuit In the inverter,
A first semiconductor element and a fourth semiconductor element are placed close to each other; a third semiconductor element and a second semiconductor element are spaced apart from the first and fourth semiconductor elements;
A planar conductor to which a positive electrode of the DC power source and a positive potential electrode of each DC capacitor are connected, the first positive electrode being provided on one end side of the planar conductor and connected to the collector of the first semiconductor element A first conductor having a terminal and a second positive electrode terminal provided on the other end side of the planar conductor and connected to a collector of the third semiconductor element;
A planar conductor disposed opposite to the first conductor at a predetermined distance to which a negative electrode of the DC power source and a negative potential electrode of each DC capacitor are connected, on one end side of the planar conductor and A first negative electrode terminal provided near the first positive electrode terminal, to which the emitter of the fourth semiconductor element is connected, and provided at the other end of the planar conductor and in the vicinity of the second positive electrode terminal. A second conductor having a second negative electrode terminal to which an emitter of the second semiconductor element is connected;
It is characterized by having.

上記構成において、前記第１および第２の半導体素子の共通接続点と、第３および第４の半導体素子の共通接続点との間に接続される、例えば負荷に交流電力を供給するために、第１および第４の半導体素子と、第３および第２の半導体素子は交互にオン制御される。 In the above configuration, for example, to supply alternating current power to a load connected between the common connection point of the first and second semiconductor elements and the common connection point of the third and fourth semiconductor elements, The first and fourth semiconductor elements and the third and second semiconductor elements are on-controlled alternately.

例えば第１および第４の半導体素子がオンされた場合、各直流コンデンサの正電位極→第１の導体→第１の正極端子→第１の半導体素子のコレクタ、エミッタ→第１および第２の半導体素子の共通接続点→負荷→第３および第４の半導体素子の共通接続点→第４の半導体素子のコレクタ、エミッタ→第１の負極端子→第２の導体→各直流コンデンサの負電位極の経路で電流が流れる。 For example, when the first and fourth semiconductor elements are turned on, the positive potential electrode of each DC capacitor → the first conductor → the first positive terminal → the collector and emitter of the first semiconductor element → the first and second elements Common connection point of semiconductor element → load → common connection point of third and fourth semiconductor elements → collector and emitter of fourth semiconductor element → first negative electrode terminal → second conductor → negative potential electrode of each DC capacitor Current flows through the path.

この際、各直流コンデンサの正電位極から第１の導体（正極側の導体）を通して、第１の半導体素子のコレクタが接続されている第１の正極端子に流出する電流と、第４の半導体素子のエミッタが接続されている第１の負極端子から第２の導体（負極側の導体）を通して各直流コンデンサの負電位極に流入する電流は、互いに逆方向であることと、第１の半導体素子と第４の半導体素子が互いに近設され、且つ第１の導体と第２の導体が対向配設されていることとから、前記各直流コンデンサの正電位極から第１の導体を通して流出する電流と、第２の導体を通して負電位極へ流入する電流とが生成する磁束は打ち消される。 At this time, the current flowing out from the positive potential electrode of each DC capacitor to the first positive electrode terminal to which the collector of the first semiconductor element is connected through the first conductor (conductor on the positive electrode side), and the fourth semiconductor The currents flowing from the first negative terminal to which the emitter of the element is connected to the negative potential electrode of each DC capacitor through the second conductor (negative-side conductor) are in opposite directions, and the first semiconductor Since the element and the fourth semiconductor element are disposed close to each other, and the first conductor and the second conductor are disposed opposite to each other, the first conductor flows out from the positive potential electrode of each DC capacitor. The magnetic flux generated by the current and the current flowing into the negative potential electrode through the second conductor is canceled out.

このため、第１の半導体素子および第４の半導体素子のターンオフ時に直流側でのサージ電圧の発生は抑制される。 For this reason, the generation of a surge voltage on the DC side is suppressed when the first semiconductor element and the fourth semiconductor element are turned off.

また、第３および第２の半導体素子がオンされた場合、各直流コンデンサの正電位極→第１の導体→第２の正極端子→第３の半導体素子のコレクタ、エミッタ→第３および第４の半導体素子の共通接続点→負荷→第１および第２の半導体素子の共通接続点→第２の半導体素子のコレクタ、エミッタ→第２の負極端子→第２の導体→各直流コンデンサの負電位極の経路で電流が流れる。 Further, when the third and second semiconductor elements are turned on, the positive potential electrode of each DC capacitor → the first conductor → the second positive terminal → the collector and emitter of the third semiconductor element → the third and fourth Common connection point of the semiconductor element → Load → Common connection point of the first and second semiconductor elements → Collector and emitter of the second semiconductor element → Second negative terminal → Second conductor → Negative potential of each DC capacitor Current flows through the pole path.

この際、各直流コンデンサの正電位極から第１の導体（正極側の導体）を通して、第３の半導体素子のコレクタが接続されている第２の正極端子に流出する電流と、第２の半導体素子のエミッタが接続されている第２の負極端子から第２の導体（負極側の導体）を通して各直流コンデンサの負電位極に流入する電流は、互いに逆方向であることと、第３の半導体素子と第２の半導体素子が互いに近設され、且つ第１の導体と第２の導体が対向配設されていることとから、前記各直流コンデンサの正電位極から第１の導体を通して流出する電流と、第２の導体を通して負電位極へ流入する電流とが生成する磁束は打ち消される。 At this time, the current flowing out from the positive potential electrode of each DC capacitor through the first conductor (positive conductor) to the second positive terminal to which the collector of the third semiconductor element is connected, and the second semiconductor The current flowing from the second negative terminal to which the emitter of the element is connected to the negative potential electrode of each DC capacitor through the second conductor (negative-side conductor) is opposite to each other, and the third semiconductor Since the element and the second semiconductor element are disposed close to each other and the first conductor and the second conductor are disposed to face each other, the positive potential electrode of each DC capacitor flows out through the first conductor. The magnetic flux generated by the current and the current flowing into the negative potential electrode through the second conductor is canceled out.

このため、第３の半導体素子および第２の半導体素子のターンオフ時に直流側でのサージ電圧の発生は抑制される。 For this reason, the generation of a surge voltage on the DC side is suppressed when the third semiconductor element and the second semiconductor element are turned off.

また、請求項２に記載の単相インバータ装置は、請求項１において、一端が前記第１の半導体素子のエミッタに接続され、他端が前記第２の半導体素子のコレクタに接続され、前記一端と他端の間の中間点を第１交流出力端子とした第３の導体と、
前記第３の導体に対して所定距離隔てて対向配設され、一端が前記第４の半導体素子のコレクタに接続され、他端が前記第３の半導体素子のエミッタに接続され、前記一端と他端の間の中間点を第２交流出力端子とした第４の導体と、
を備えたこと特徴としている。 The single-phase inverter device according to claim 2 is the single-phase inverter device according to claim 1, wherein one end is connected to an emitter of the first semiconductor element, and the other end is connected to a collector of the second semiconductor element. A third conductor having a middle point between the first and second ends as a first AC output terminal;
It is disposed opposite to the third conductor at a predetermined distance, one end is connected to the collector of the fourth semiconductor element, the other end is connected to the emitter of the third semiconductor element, and the other end is connected to the other end. A fourth conductor having a middle point between the ends as a second AC output terminal;
It is characterized by having.

上記構成において、前記第１および第２の半導体素子の共通接続点である第１交流出力端子と、第３および第４の半導体素子の共通接続点である第２交流出力端子との間に接続される、例えば負荷に交流電力を供給するために、第１および第４の半導体素子と、第３および第２の半導体素子は交互にオン制御される。 In the above configuration, a connection is made between a first AC output terminal that is a common connection point of the first and second semiconductor elements and a second AC output terminal that is a common connection point of the third and fourth semiconductor elements. For example, in order to supply AC power to a load, the first and fourth semiconductor elements and the third and second semiconductor elements are alternately turned on.

例えば第１および第４の半導体素子がオンされた場合、各直流コンデンサの正電位極→第１の導体→第１の正極端子→第１の半導体素子のコレクタ、エミッタ→第３の導体の一端→第３の導体の中間点の第１の交流出力端子→負荷→第４の導体の中間点の第２の交流出力端子→第４の導体の一端→第４の半導体素子のコレクタ、エミッタ→第１の負極端子→第２の導体→各直流コンデンサの負電位極の経路で電流が流れる。 For example, when the first and fourth semiconductor elements are turned on, the positive potential electrode of each DC capacitor → the first conductor → the first positive terminal → the collector and emitter of the first semiconductor element → one end of the third conductor → first AC output terminal at the midpoint of the third conductor → load → second AC output terminal at the midpoint of the fourth conductor → one end of the fourth conductor → collector and emitter of the fourth semiconductor element → A current flows through a path of the first negative electrode terminal → the second conductor → the negative potential electrode of each DC capacitor.

また、第１の半導体素子のエミッタから第３の導体を通して、第１交流出力端子へ流れる電流と、第２交流出力端子から第４の導体を通して第４の半導体素子のコレクタへ流れる電流は互いに逆方向であることと、第１の半導体素子と第４の半導体素子が互いに近設され、且つ第３の導体と第４の導体が対向配設されていることとから、前記第３の導体を通して流れる電流と、第４の導体を通して流れる電流とが生成する磁束は打ち消される。 Also, the current flowing from the emitter of the first semiconductor element through the third conductor to the first AC output terminal and the current flowing from the second AC output terminal through the fourth conductor to the collector of the fourth semiconductor element are opposite to each other. The first conductor element and the fourth semiconductor element are arranged close to each other, and the third conductor and the fourth conductor are disposed opposite to each other, so that the third conductor is passed through the third conductor. The magnetic flux generated by the flowing current and the current flowing through the fourth conductor is canceled out.

このため、第１の半導体素子および第４の半導体素子のターンオフ時にサージ電圧の発生は抑制される。 For this reason, generation | occurrence | production of a surge voltage is suppressed at the time of turn-off of a 1st semiconductor element and a 4th semiconductor element.

さらに、第１の半導体素子および第４の半導体素子と、第３の半導体素子および第２の半導体素子とは離間して配設しているため、その分の距離だけ第３、第４の導体の各々の両端間距離は長い。このため、第３の導体、第４の導体を通して流れる前記電流経路における表面積が広いので、高周波であるサージ電圧は表皮効果も含めたインダクタンス低減によって抑制される。 Further, since the first semiconductor element and the fourth semiconductor element and the third semiconductor element and the second semiconductor element are spaced apart from each other, the third and fourth conductors are provided by that distance. The distance between both ends of each is long. For this reason, since the surface area in the said current path which flows through the 3rd conductor and the 4th conductor is large, the surge voltage which is a high frequency is suppressed by inductance reduction including a skin effect.

また、第３および第２の半導体素子がオンされた場合、各直流コンデンサの正電位極→第１の導体→第２の正極端子→第３の半導体素子のコレクタ、エミッタ→第４の導体の他端→第４の導体の中間点の第２の交流出力端子→負荷→第３の導体の中間点の第１の交流出力端子→第３の導体の他端→第２の半導体素子のコレクタ、エミッタ→第２の負極端子→第２の導体→各直流コンデンサの負電位極の経路で電流が流れる。 Further, when the third and second semiconductor elements are turned on, the positive potential electrode of each DC capacitor → the first conductor → the second positive terminal → the collector and emitter of the third semiconductor element → the fourth conductor The other end → the second AC output terminal at the middle point of the fourth conductor → the load → the first AC output terminal at the middle point of the third conductor → the other end of the third conductor → the collector of the second semiconductor element The current flows through the path of the emitter → the second negative terminal → the second conductor → the negative potential electrode of each DC capacitor.

また、第３の半導体素子のエミッタから第４の導体を通して、第２交流出力端子へ流れる電流と、第１交流出力端子から第３の導体を通して第２の半導体素子のコレクタへ流れる電流は互いに逆方向であることと、第３の半導体素子と第２の半導体素子が互いに近設され、且つ第３の導体と第４の導体が対向配設されていることとから、前記第３の導体を通して流れる電流と、第４の導体を通して流れる電流とが生成する磁束は打ち消される。 Also, the current flowing from the emitter of the third semiconductor element through the fourth conductor to the second AC output terminal and the current flowing from the first AC output terminal through the third conductor to the collector of the second semiconductor element are opposite to each other. And the third semiconductor element and the second semiconductor element are disposed close to each other, and the third conductor and the fourth conductor are disposed to face each other, so that the third conductor is passed through the third conductor. The magnetic flux generated by the flowing current and the current flowing through the fourth conductor is canceled out.

このため、第３の半導体素子および第２の半導体素子のターンオフ時にサージ電圧の発生は抑制される。 For this reason, generation | occurrence | production of a surge voltage is suppressed at the time of the turn-off of a 3rd semiconductor element and a 2nd semiconductor element.

（１）請求項１、２に記載の発明によれば、第１の半導体素子および第４の半導体素子のオン時、又は第３の半導体素子および第２の半導体素子のオン時に、第１の導体（正極側の導体）を通して流れる電流と、第２の導体（負極側の導体）を通して流れる電流は互いに逆方向となるため、前記両電流が生成する磁束は打ち消され、第１の半導体素子および第４の半導体素子のターンオフ時、第３の半導体素子および第２の半導体素子のターンオフ時に、直流側でのサージ電圧の発生が抑制される。これによって、第１〜第４の半導体素子の破損を防ぐことができる。
（２）請求項２に記載の発明によれば、第１の半導体素子および第４の半導体素子のオン時、又は第３の半導体素子および第２の半導体素子のオン時に、第３の導体を通して流れる電流と第４の導体を通して流れる電流は互いに逆方向となるため、前記両電流が生成する磁束は打ち消され、第１の半導体素子および第４の半導体素子のターンオフ時、第３の半導体素子および第２の半導体素子のターンオフ時に、直流側でのサージ電圧の発生が抑制される。さらに、第３の導体、第４の導体を通して流れる前記電流経路における表面積が広いので、高周波であるサージ電圧は表皮効果も含めたインダクタンス低減によって抑制される。これによって、第１〜第４の半導体素子の破損を防ぐことができる。 (1) According to the first and second aspects of the invention, the first semiconductor element and the fourth semiconductor element are turned on, or the third semiconductor element and the second semiconductor element are turned on. Since the current flowing through the conductor (positive electrode side conductor) and the current flowing through the second conductor (negative electrode side conductor) are in opposite directions, the magnetic flux generated by both the currents is canceled, and the first semiconductor element and Generation of a surge voltage on the DC side is suppressed when the fourth semiconductor element is turned off and when the third semiconductor element and the second semiconductor element are turned off. Thereby, damage to the first to fourth semiconductor elements can be prevented.
(2) According to the invention described in claim 2, when the first semiconductor element and the fourth semiconductor element are turned on, or when the third semiconductor element and the second semiconductor element are turned on, the third conductor is passed through. Since the flowing current and the current flowing through the fourth conductor are opposite to each other, the magnetic flux generated by the both currents is canceled, and when the first semiconductor element and the fourth semiconductor element are turned off, the third semiconductor element and Generation of a surge voltage on the DC side is suppressed when the second semiconductor element is turned off. Furthermore, since the surface area of the current path flowing through the third conductor and the fourth conductor is large, a surge voltage having a high frequency is suppressed by inductance reduction including the skin effect. Thereby, damage to the first to fourth semiconductor elements can be prevented.

本発明の実施形態例による単相インバータ装置の電気的接続を示す回路図。The circuit diagram which shows the electrical connection of the single phase inverter apparatus by the example of embodiment of this invention. 本発明の実施形態例による単相インバータ装置の物理的接続を示す構成図。The block diagram which shows the physical connection of the single phase inverter apparatus by the example of embodiment of this invention. 本発明の実施形態例による単相インバータ装置を表し、図２のＵ導体、Ｖ導体側から見た簡略構成図。The simple block diagram showing the single phase inverter apparatus by the example of embodiment of this invention, and was seen from the U conductor and V conductor side of FIG. 本発明の実施形態例による単相インバータ装置における電流経路を示す説明図。Explanatory drawing which shows the current pathway in the single phase inverter apparatus by the example of embodiment of this invention. 従来の単相インバータにおける電流経路を示す説明図。Explanatory drawing which shows the current pathway in the conventional single phase inverter. 単相インバータ装置の従来例における電気的接続を示す回路図。The circuit diagram which shows the electrical connection in the prior art example of a single phase inverter apparatus. 単相インバータ装置の従来例における物理的接続を示す構成図。The block diagram which shows the physical connection in the prior art example of a single phase inverter apparatus.

以下、図面を参照しながら本発明の実施の形態を説明するが、本発明は下記の実施形態例に限定されるものではない。本実施形態例では、単相インバータを構成する半導体素子の配置を、直流コンデンサの正電位極から正極側（上アーム側）の半導体素子側へ流出する電流による磁束と、負極側（下アーム側）の半導体素子から直流コンデンサの負電位極側へ流入する電流による磁束とが打ち消される配置に構成することで、半導体素子のターンオフ時に発生する直流側のサージ電圧を抑制し、各半導体素子の破損を防ぐようにした。 Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. In the present embodiment example, the arrangement of the semiconductor elements constituting the single-phase inverter is determined by the magnetic flux generated by the current flowing from the positive potential electrode of the DC capacitor to the semiconductor element side on the positive electrode side (upper arm side) and the negative electrode side (lower arm side). ), The magnetic flux generated by the current flowing from the semiconductor element to the negative potential pole side of the DC capacitor is cancelled, so that the DC side surge voltage generated when the semiconductor element is turned off is suppressed and each semiconductor element is damaged. To prevent.

図１は本実施形態例による単相インバータ装置の電気的接続を示し、図２は物理的接続を示している。図１、図２において、図６、図７と同一部分は同一符号をもって示している。図１において、直流コンデンサＣおよび半導体素子ＴＲＵ，ＴＲＶ，ＴＲＸ，ＴＲＹの接続状態は図６と同一であるが、図７における半導体素子ＴＲＸとＴＲＹの配置を入れ替えて図２の配置とし、さらに図７におけるＵ導体１１、Ｖ導体１２の構造を図２のように変更した。 FIG. 1 shows the electrical connection of the single-phase inverter device according to this embodiment, and FIG. 2 shows the physical connection. 1 and 2, the same parts as those in FIGS. 6 and 7 are denoted by the same reference numerals. 1, the connection state of the DC capacitor C and the semiconductor elements TRU, TRV, TRX, TRY is the same as that in FIG. 6, but the arrangement of the semiconductor elements TRX and TRY in FIG. 7, the structure of the U conductor 11 and the V conductor 12 was changed as shown in FIG.

図１において、直流コンデンサＣの正、負電位極Ｐ，Ｎ間には、半導体素子ＴＲＵ（第１の半導体素子）およびＴＲＸ（第２の半導体素子）が直列に接続されるとともに、半導体素子ＴＲＶ（第３の半導体素子）およびＴＲＹ（第４の半導体素子）が直列に接続されている。 In FIG. 1, a semiconductor element TRU (first semiconductor element) and TRX (second semiconductor element) are connected in series between the positive and negative potential poles P and N of the DC capacitor C, and the semiconductor element TRV. (Third semiconductor element) and TRY (fourth semiconductor element) are connected in series.

半導体素子ＴＲＵ，ＴＲＶ，ＴＲＸ，ＴＲＹは自己消弧型の半導体素子、例えばＩＧＢＴで構成されている。尚、直流コンデンサＣは、例えば図７の場合と同様に、図２に示すように、分割した４つの直流コンデンサＣ１〜Ｃ４を並列接続して構成されている。 The semiconductor elements TRU, TRV, TRX, TRY are constituted by self-extinguishing type semiconductor elements, for example, IGBTs. For example, as shown in FIG. 2, the DC capacitor C is configured by connecting four divided DC capacitors C1 to C4 in parallel as shown in FIG.

図２において、１０１は、平板状の平面導体からなるＰ導体（第１の導体）であり、平板の長手方向一端側に、平板の長辺から直交する方向に突出して正極端子Ｐ１（第１の正極端子）が設けられ、平板の長手方向他端側に、平板の長辺から直交する方向に突出して正極端子Ｐ２（第２の正極端子）が設けられている。このＰ導体１０１は図示省略の直流電源の正極に接続されている。 In FIG. 2, reference numeral 101 denotes a P conductor (first conductor) made of a flat plate-like conductor, and protrudes in the direction perpendicular to the long side of the flat plate at one end side in the longitudinal direction of the flat plate, and is connected to the positive electrode terminal P1 Positive electrode terminal), and a positive electrode terminal P2 (second positive electrode terminal) is provided on the other end side in the longitudinal direction of the flat plate so as to protrude in a direction orthogonal to the long side of the flat plate. The P conductor 101 is connected to the positive electrode of a DC power supply (not shown).

１０２は、平板状の平面導体からなるＮ導体（第２の導体）であり、平板の長手方向一端側に、平板の長辺から直交する方向に突出して負極端子Ｎ２（第１の負極端子）が設けられ、平板の長手方向他端側に、平板の長辺から直交する方向に突出して負極端子Ｎ１（第２の負極端子）が設けられている。このＮ導体１０２は図示省略の直流電源の負極に接続されている。 Reference numeral 102 denotes an N conductor (second conductor) made of a flat plate-like conductor, and protrudes in the direction perpendicular to the long side of the flat plate at one end in the longitudinal direction of the flat plate, and is a negative electrode terminal N2 (first negative electrode terminal). The negative electrode terminal N1 (second negative electrode terminal) is provided on the other end in the longitudinal direction of the flat plate so as to protrude in a direction orthogonal to the long side of the flat plate. The N conductor 102 is connected to the negative electrode of a DC power supply (not shown).

Ｎ導体１０２はＰ導体１０１に対して、所定厚みを有した絶縁物１０５を介して対向配設されており、図２では、Ｐ導体１０１が奥側に配置され、Ｎ導体１０２が手前側に配置され、Ｐ導体１０１とＮ導体１０２の間に絶縁物１０５が介在する配置関係となっている。 The N conductor 102 is disposed opposite to the P conductor 101 via an insulator 105 having a predetermined thickness. In FIG. 2, the P conductor 101 is disposed on the back side, and the N conductor 102 is disposed on the near side. The arrangement relationship is such that an insulator 105 is interposed between the P conductor 101 and the N conductor 102.

また正極端子Ｐ１，Ｐ２と負極端子Ｎ２，Ｎ１は各々対向しない位置に配設されており、負極端子Ｎ２，Ｎ１は、正極端子Ｐ１，Ｐ２の配設位置に対してＰ導体１０１の長手方向一端から他端へ向かう方向に所定距離ずれた位置に各々配設されている。 The positive terminals P1, P2 and the negative terminals N2, N1 are disposed at positions that do not face each other, and the negative terminals N2, N1 are one end in the longitudinal direction of the P conductor 101 with respect to the positions at which the positive terminals P1, P2 are disposed. Are respectively disposed at positions shifted by a predetermined distance in the direction from one end to the other end.

また、図２における、前記Ｐ導体１０１のさらに奥側の部位（Ｐ導体１０１の、絶縁物１０５と反対側に対向する部位）には、Ｐ導体１０１の長辺に沿って直流コンデンサＣ１〜Ｃ４が順次配設されている。 In addition, DC capacitors C <b> 1 to C <b> 4 along the long side of the P conductor 101 are located on the further back side of the P conductor 101 in FIG. 2 (the part facing the opposite side of the insulator 105 of the P conductor 101). Are sequentially arranged.

直流コンデンサＣ１〜Ｃ４の各正電位極Ｐ_C1〜Ｐ_C4は、該コンデンサに対向するＰ導体１０１に直接、接続固定されている。直流コンデンサＣ１〜Ｃ４の各負電位極Ｎ_C1〜Ｎ_C4は、当該負電位極の大きさよりやや大きい範囲で対向するＰ導体１０１および絶縁物１０５の部位を切り欠くか又は貫通させて、Ｎ導体１０２に接続固定されている。 The positive potential electrodes P _{C1 to} P _C4 of the DC capacitors C1 to _C4 are directly connected and fixed to the P conductor 101 facing the capacitors. The negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to _C4 are formed by cutting out or penetrating portions of the P conductor 101 and the insulator 105 facing each other in a range slightly larger than the size of the negative potential electrode. The connection is fixed to 102.

尚、図２ではＮ導体１０２および絶縁物１０５にはハッチングを付与していない。また、Ｐ導体１０１とＮ導体１０２が絶縁物１０５を介して重なっている部位のＰ導体１０１にはハッチングを付与せず、重なっていない部位のＰ導体１０１にのみハッチングを付与している。 In FIG. 2, the N conductor 102 and the insulator 105 are not hatched. Moreover, hatching is not given to the P conductor 101 of the site | part with which the P conductor 101 and the N conductor 102 have overlapped via the insulator 105, but only the P conductor 101 of the site | part which has not overlapped.

前記正極端子Ｐ１の配設位置に相当し、且つＰ導体１０１の長辺に直交する部位には半導体素子ＴＲＵが配設され、半導体素子ＴＲＵのコレクタは正極端子Ｐ１に接続されている。 A semiconductor element TRU is disposed at a position corresponding to the position where the positive terminal P1 is disposed and orthogonal to the long side of the P conductor 101, and the collector of the semiconductor element TRU is connected to the positive terminal P1.

前記負極端子Ｎ２の配設位置に相当し、且つＮ導体１０２の長辺に直交する部位には半導体素子ＴＲＹが配設され、半導体素子ＴＲＹのエミッタは負極端子Ｎ２に接続されている。 A semiconductor element TRY is disposed at a portion corresponding to the position where the negative electrode terminal N2 is disposed and orthogonal to the long side of the N conductor 102, and the emitter of the semiconductor element TRY is connected to the negative electrode terminal N2.

前記正極端子Ｐ２の配設位置に相当し、且つＰ導体１０１の長辺に直交する部位には半導体素子ＴＲＶが配設され、半導体素子ＴＲＶのコレクタは正極端子Ｐ２に接続されている。 A semiconductor element TRV is disposed at a portion corresponding to the position where the positive electrode terminal P2 is disposed and orthogonal to the long side of the P conductor 101, and the collector of the semiconductor element TRV is connected to the positive electrode terminal P2.

前記負極端子Ｎ１の配設位置に相当し、且つＮ導体１０２の長辺に直交する部位には半導体素子ＴＲＸが配設され、半導体素子ＴＲＸのエミッタは負極端子Ｎ１に接続されている。 A semiconductor element TRX is disposed at a portion corresponding to the position where the negative electrode terminal N1 is disposed and orthogonal to the long side of the N conductor 102, and the emitter of the semiconductor element TRX is connected to the negative electrode terminal N1.

１０３は、半導体素子ＴＲＵ，ＴＲＸの、Ｐ導体１０１、Ｎ導体１０２と反対側に対向する部位に設けられたＵ導体（第３の導体）であり、その一端は半導体素子ＴＲＵのエミッタに接続され、他端は半導体素子ＴＲＸのコレクタに接続され、一端と他端の間の中間点にはＵ端子（第１交流出力端子）１１１が設けられている。 Reference numeral 103 denotes a U conductor (third conductor) provided on a portion of the semiconductor elements TRU, TRX opposite to the P conductor 101 and the N conductor 102, one end of which is connected to the emitter of the semiconductor element TRU. The other end is connected to the collector of the semiconductor element TRX, and a U terminal (first AC output terminal) 111 is provided at an intermediate point between the one end and the other end.

１０４は、半導体素子ＴＲＹ，ＴＲＶの、Ｐ導体１０１、Ｎ導体１０２と反対側に対向する部位に、Ｕ導体１０３に対して所定距離隔てて対向配設されたＶ導体（第４の導体）であり、その一端は半導体素子ＴＲＹのコレクタに接続され、他端は半導体素子ＴＲＶのエミッタに接続され、一端と他端の間の中間点にはＶ端子（第２交流出力端子）１１２が設けられている。 Reference numeral 104 denotes a V conductor (fourth conductor) disposed opposite to the P conductor 101 and the N conductor 102 on the opposite side of the semiconductor elements TRY and TRV with a predetermined distance from the U conductor 103. One end is connected to the collector of the semiconductor element TRY, the other end is connected to the emitter of the semiconductor element TRV, and a V terminal (second AC output terminal) 112 is provided at an intermediate point between the one end and the other end. ing.

尚、図２では図示省略しているがＵ導体１０３とＶ導体１０４の対向部位には絶縁物１０６が介挿されている。 Although not shown in FIG. 2, an insulator 106 is inserted in a portion where the U conductor 103 and the V conductor 104 face each other.

前記Ｕ端子１１１およびＶ端子１１２は、図示省略の負荷の両端に各々接続されている。 The U terminal 111 and the V terminal 112 are connected to both ends of a load (not shown).

図２のように構成された装置の、半導体素子ＴＲＵ，ＴＲＶ，ＴＲＸ，ＴＲＹ、正極端子Ｐ１，Ｐ２、負極端子Ｎ１，Ｎ２、各導体１０１〜１０４、Ｕ，Ｖ端子１１１、１１２、直流コンデンサＣ１〜Ｃ４の配置関係の一例を図３に示す。 2, the semiconductor elements TRU, TRV, TRX, TRY, positive terminals P1, P2, negative terminals N1, N2, conductors 101 to 104, U, V terminals 111, 112, DC capacitor C1 FIG. 3 shows an example of the arrangement relationship of .about.C4.

図３は図２の装置をＵ導体１０３、Ｖ導体１０４側から見た図であり、図２における直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4、負電位極Ｎ_C1〜Ｎ_C4、絶縁物１０５、１０６は図示省略している。また図３では、Ｐ導体１０１における正極端子Ｐ１，Ｐ２間、Ｎ導体１０２における負極端子Ｎ１，Ｎ２間の各距離は、図２よりも若干長く記載している。 3 is a view of the apparatus of FIG. 2 as viewed from the U conductor 103 and V conductor 104 side. The positive potential electrodes P _{C1 to} P _C4 and the negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to C4 in FIG. The insulators 105 and 106 are not shown. In FIG. 3, the distances between the positive terminals P1 and P2 in the P conductor 101 and the negative terminals N1 and N2 in the N conductor 102 are shown slightly longer than those in FIG.

図３の例では、平板状のＵ導体１０３、Ｖ導体１０４の各両端から各々所定距離隔てた部位を直角に屈曲させて平板屈曲部とし、Ｕ導体１０３の一端を半導体素子ＴＲＵのエミッタに、Ｕ導体１０３の他端を半導体素子ＴＲＸのコレクタに、Ｖ導体１０４の一端を半導体素子ＴＲＹのコレクタに、Ｖ導体１０４の他端を半導体素子ＴＲＶのエミッタに各々接続している。 In the example of FIG. 3, portions of the flat U conductor 103 and the V conductor 104 that are separated from each end by a predetermined distance are bent at right angles to form a flat plate bent portion, and one end of the U conductor 103 is used as the emitter of the semiconductor element TRU. The other end of the U conductor 103 is connected to the collector of the semiconductor element TRX, one end of the V conductor 104 is connected to the collector of the semiconductor element TRY, and the other end of the V conductor 104 is connected to the emitter of the semiconductor element TRV.

そして、Ｕ導体１０３の平板中央部とＶ導体１０４の平板中央部とが所定距離隔てて対向するように配設している。 The flat plate center portion of the U conductor 103 and the flat plate center portion of the V conductor 104 are arranged to face each other with a predetermined distance.

また、図３のようにＵ導体１０３、Ｖ導体１０４に屈曲部を設けない例としては、Ｕ導体１０３およびＶ導体１０４を各々平板で構成して互いに対向配設し、互いに屈曲部のない平板であることによりＵ導体１０３とＶ導体１０４が交叉する部位において、互いが接触しないように各々切り欠き部を設け、各々の切り欠き部を通してＵ導体１０３およびＶ導体１０４を非接触で交叉させるように構成してもよい。 In addition, as an example in which the U conductor 103 and the V conductor 104 are not provided with bent portions as shown in FIG. Therefore, at the portion where the U conductor 103 and the V conductor 104 cross each other, a notch is provided so that they do not contact each other, and the U conductor 103 and the V conductor 104 are crossed in a non-contact manner through each notch. You may comprise.

次に、上記のように構成された単相インバータ装置の動作を、各半導体素子のオン時に流れる電流経路を矢印で示した図４とともに述べる。尚、図４では直流コンデンサＣ１〜Ｃ４のうちＣ１の電流経路のみを図示している。 Next, the operation of the single-phase inverter device configured as described above will be described with reference to FIG. FIG. 4 shows only the current path of C1 among the DC capacitors C1 to C4.

図４において、例えば半導体素子ＴＲＵおよびＴＲＹがオンされた場合、実線の矢印で示すように、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１０１→正極端子Ｐ１→半導体素子ＴＲＵのコレクタ、エミッタ→Ｕ導体１０３の一端→Ｕ導体１０３の中間点のＵ端子１１１→図示省略の負荷→Ｖ導体１０４の中間点のＶ端子１１２→Ｖ導体１０４の一端→半導体素子ＴＲＹのコレクタ、エミッタ→負極端子Ｎ２→Ｎ導体１０２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 In FIG. 4, for example, when the semiconductor elements TRU and TRY are turned on, as indicated by solid arrows, the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 → P conductor 101 → positive electrode terminal P1 → semiconductor element Collector and emitter of TRU → one end of U conductor 103 → U terminal 111 at the midpoint of U conductor 103 → load not shown → V terminal 112 at the midpoint of V conductor 104 → one end of V conductor 104 → collector of semiconductor element TRY The current flows through the path of the emitter → the negative terminal N2 → the N conductor 102 → the negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to _C4 .

この際、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4からＰ導体１０１を通して、正極端子Ｐ１に流出する電流と、負極端子Ｎ２からＮ導体１０２を通して各直流コンデンサの負電位極Ｎ_C1〜Ｎ_C4に流入する電流は、互いに逆方向である。そして、半導体素子ＴＲＵ，ＴＲＹが互いに近設され、且つＰ導体１０１とＮ導体１０２が対向配設されていることから、前記各直流コンデンサの正電位極Ｐ_C1〜Ｐ_C4からＰ導体１０１を通して流出する電流が生成する磁束と、Ｎ導体１０２を通して負電位極Ｎ_C1〜Ｎ_C4へ流入する電流が生成する磁束は打ち消される。 At this time, the current flowing out from the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 through the P conductor 101 to the positive terminal P1 and the negative potential electrode N _C1 of each DC capacitor from the negative terminal N2 through the N conductor 102. The currents flowing into ˜N _C4 are in opposite directions. Since the semiconductor elements TRU and TRY are arranged close to each other and the P conductor 101 and the N conductor 102 are arranged to face each other, the positive potential electrodes P _{C1 to} P _{C4 of} each DC capacitor flow out through the P conductor 101. The magnetic flux generated by the current to be generated and the magnetic flux generated by the current flowing into the negative potential electrodes N _{C1 to} N _C4 through the N conductor 102 are canceled out.

また、半導体素子ＴＲＵのエミッタからＵ導体１０３を通してＵ端子１１１へ流れる電流と、Ｖ端子１１２からＶ導体１０４を通して半導体素子ＴＲＹのコレクタへ流れる電流は互いに逆方向である。そして半導体素子ＴＲＵとＴＲＹが互いに近設され、且つＵ導体１０３とＶ導体１０４が対向配設されていることから、Ｕ導体１０３を通して流れる電流が生成する磁束とＶ導体１０４を通して流れる電流が生成する磁束は打ち消される。このため、半導体素子ＴＲＵおよびＴＲＹのターンオフ時にサージ電圧の発生は抑制される。 The current flowing from the emitter of the semiconductor element TRU to the U terminal 111 through the U conductor 103 and the current flowing from the V terminal 112 to the collector of the semiconductor element TRY through the V conductor 104 are in opposite directions. Since the semiconductor elements TRU and TRY are disposed close to each other and the U conductor 103 and the V conductor 104 are disposed to face each other, a magnetic flux generated by the current flowing through the U conductor 103 and a current flowing through the V conductor 104 are generated. The magnetic flux is canceled out. For this reason, generation of a surge voltage is suppressed when the semiconductor elements TRU and TRY are turned off.

さらに、半導体素子ＴＲＵおよびＴＲＹと半導体素子ＴＲＶおよびＴＲＸとは離間して配設されているため、その分の距離だけＵ導体１０３の両端間距離、Ｖ導体１０４の両端間距離は各々長い。このため、Ｕ導体１０３、Ｖ導体１０４を通して流れる電流経路における表面積が広いので、高周波であるサージ電圧は表皮効果も含めたインダクタンス低減によって抑制される。これによって、半導体素子ＴＲＵ，ＴＲＶ，ＴＲＸ，ＴＲＹの破損を防ぐことができる。 Further, since the semiconductor elements TRU and TRY and the semiconductor elements TRV and TRX are arranged apart from each other, the distance between both ends of the U conductor 103 and the distance between both ends of the V conductor 104 are respectively longer by that amount. For this reason, since the surface area in the current path which flows through the U conductor 103 and the V conductor 104 is large, the surge voltage which is a high frequency is suppressed by the inductance reduction including the skin effect. Thereby, damage to the semiconductor elements TRU, TRV, TRX, TRY can be prevented.

また、半導体素子ＴＲＶおよびＴＲＸがオンされた場合、破線の矢印で示すように、各直流コンデンサの正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１０１→正極端子Ｐ２→半導体素子ＴＲＶのコレクタ、エミッタ→Ｖ導体１０４の他端→Ｖ導体１０４の中間点のＶ端子１１２→負荷→Ｕ導体１０３の中間点のＵ端子１１１→Ｕ導体１０３の他端→半導体素子ＴＲＸのコレクタ、エミッタ→負極端子Ｎ１→Ｎ導体１０２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 When the semiconductor elements TRV and TRX are turned on, as indicated by broken arrows, the positive potential electrodes P _{C1 to} P _{C4 of} each DC capacitor → P conductor 101 → the positive terminal P2 → the collector and emitter of the semiconductor element TRV → The other end of the V conductor 104 → the V terminal 112 at the midpoint of the V conductor 104 → the load → the U terminal 111 at the midpoint of the U conductor 103 → the other end of the U conductor 103 → the collector and emitter of the semiconductor element TRX → the negative terminal N1 → Current flows through the path of the N conductor 102 → the negative potential electrodes N _{C1 to} N _C4 of the DC capacitors C1 to _C4 .

この際、各直流コンデンサの正電位極Ｐ_C1〜Ｐ_C4からＰ導体１０１を通して、正極端子Ｐ２に流出する電流と、負極端子Ｎ１からＮ導体１０２を通して各直流コンデンサの負電位極Ｎ_C1〜Ｎ_C4に流入する電流は、互いに逆方向であることと、半導体素子ＴＲＶ，ＴＲＸが互いに近設され、且つＰ導体１０１とＮ導体１０２が対向配設されていることから、各直流コンデンサの正電位極Ｐ_C1〜Ｐ_C4からＰ導体１０１を通して流出する電流が生成する磁束と、Ｎ導体１０２を通して負電位極Ｎ_C1〜Ｎ_C4へ流入する電流が生成する磁束は打ち消される。 At this time, the current flowing out from the positive potential electrodes P _{C1 to} P _{C4 of} each DC capacitor to the positive terminal P2 through the P conductor 101 and the negative potential electrodes N _{C1 to} N _{C4 of} each DC capacitor from the negative terminal N1 to the N conductor 102 are obtained. Current flowing in the opposite direction, the semiconductor elements TRV and TRX are located close to each other, and the P conductor 101 and the N conductor 102 are disposed opposite to each other, so that the positive potential pole of each DC capacitor The magnetic flux generated by the current flowing from P _{C1 to} P _C4 through the P conductor 101 and the magnetic flux generated by the current flowing through the N conductor 102 to the negative potential electrodes N _{C1 to} N _C4 are canceled out.

このため、半導体素子ＴＲＶおよびＴＲＸのターンオフ時にサージ電圧の発生は抑制される。 For this reason, the generation of a surge voltage is suppressed when the semiconductor elements TRV and TRX are turned off.

また、半導体素子ＴＲＶのエミッタからＶ導体１０４を通してＶ端子１１２へ流れる電流と、Ｕ端子１１１からＵ導体１０３を通して半導体素子ＴＲＸのコレクタへ流れる電流は互いに逆方向であることと、半導体素子ＴＲＶとＴＲＸが互いに近設され、且つＵ導体１０３とＶ導体１０４が対向配設されていることとから、Ｕ導体１０３を通して流れる電流が生成する磁束とＶ導体１０４を通して流れる電流が生成する磁束は打ち消される。このため、半導体素子ＴＲＶおよびＴＲＸのターンオフ時にサージ電圧の発生は抑制される。 Further, the current flowing from the emitter of the semiconductor element TRV to the V terminal 112 through the V conductor 104 and the current flowing from the U terminal 111 to the collector of the semiconductor element TRX through the U conductor 103 are opposite to each other, and the semiconductor elements TRV and TRX Are disposed close to each other and the U conductor 103 and the V conductor 104 are disposed opposite to each other, so that the magnetic flux generated by the current flowing through the U conductor 103 and the magnetic flux generated by the current flowing through the V conductor 104 are canceled out. For this reason, the generation of a surge voltage is suppressed when the semiconductor elements TRV and TRX are turned off.

ここで、本実施形態例によるサージ電圧抑制効果と対比するために、従来の図７の構造の単相インバータ装置における電流経路を図５に示す。 Here, in order to compare with the surge voltage suppression effect according to the present embodiment, the current path in the conventional single-phase inverter device having the structure of FIG. 7 is shown in FIG.

図５は図７における各半導体素子のオン時に流れる電流経路を矢印で示しているが、直流コンデンサＣ１〜Ｃ４のうちＣ１の電流経路のみを図示している。 FIG. 5 shows current paths that flow when each semiconductor element in FIG. 7 is turned on by arrows, but only the current path of C1 among the DC capacitors C1 to C4 is illustrated.

図５において、例えば半導体素子ＴＲＵおよびＴＲＹがオンされた場合、実線の矢印で示すように、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１→正極端子Ｐ１→半導体素子ＴＲＵのコレクタ、エミッタ→Ｕ導体１１→負荷→Ｖ導体１２→半導体素子ＴＲＹのコレクタ、エミッタ→負極端子Ｎ２→Ｎ導体２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 In FIG. 5, for example, when the semiconductor elements TRU and TRY are turned on, as indicated by solid arrows, the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 → P conductor 1 → positive electrode terminal P1 → semiconductor element TRU collector / emitter → U conductor 11 → load → V conductor 12 → semiconductor element TRY collector / emitter → negative electrode terminal N2 → N conductor 2 → negative potential electrodes N _{C1 to} N _C4 of DC capacitors C1 to _C4 Current flows.

この際、Ｕ導体１１およびＶ導体１２は図４のＵ導体１０３、Ｖ導体１０４と比較して小さい面積であるため、該Ｕ導体１１、Ｖ導体１２を通る電流によるインダクタンスは大きい。また、Ｕ導体１１とＶ導体１２は、図４のように互いの面どうしを対向配設したものではなく、また互いに離間しているため、両者に各々流れる電流が生成する磁束どうしは干渉せず、図４の場合のように打ち消されることはない。 At this time, since the U conductor 11 and the V conductor 12 have a smaller area than the U conductor 103 and the V conductor 104 in FIG. 4, the inductance due to the current passing through the U conductor 11 and the V conductor 12 is large. Further, the U conductor 11 and the V conductor 12 are not arranged so as to face each other as shown in FIG. 4, and are separated from each other, so that magnetic fluxes generated by currents flowing through the U conductor 11 and the V conductor 12 do not interfere with each other. In other words, it is not canceled as in the case of FIG.

さらに、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4からＰ導体１を通して正極端子Ｐ１に流出する電流が生成する磁束と、負極端子Ｎ２からＮ導体２を通して各負電位極Ｎ_C1〜Ｎ_C4に流入する電流が生成する磁束は、半導体素子ＴＲＵとＴＲＹが離間して配設されているため、干渉力が弱く、図４の場合のように打ち消されることはない。 Further, the magnetic flux generated by the current flowing out from the positive potential electrodes P _{C1 to} P _{C4 of} each DC capacitor C1 to _C4 through the P conductor 1 to the positive terminal P1, and the negative potential electrodes N _C1 to N _C1 through the N conductor 2 from the negative terminal N2. The magnetic flux generated by the current flowing into N _C4 has a weak interference force because the semiconductor elements TRU and TRY are arranged apart from each other, and is not canceled as in the case of FIG.

このため、Ｐ導体１、Ｎ導体２を通流する各電流のインダクタンスが大きい。これによって、半導体素子ＴＲＵ，ＴＲＹのターンオフ時に発生するサージ電圧が大きくなり各半導体素子が破損しやすくなる。 For this reason, the inductance of each current flowing through the P conductor 1 and the N conductor 2 is large. As a result, a surge voltage generated when the semiconductor elements TRU and TRY are turned off increases and each semiconductor element is easily damaged.

また、半導体素子ＴＲＶおよびＴＲＸがオンされた場合、破線の矢印で示すように、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4→Ｐ導体１→正極端子Ｐ２→半導体素子ＴＲＶのコレクタ、エミッタ→Ｖ導体１２→負荷→Ｕ導体１１→半導体素子ＴＲＸのコレクタ、エミッタ→負極端子Ｎ１→Ｎ導体２→各直流コンデンサＣ１〜Ｃ４の負電位極Ｎ_C1〜Ｎ_C4の経路で電流が流れる。 When the semiconductor elements TRV and TRX are turned on, as indicated by broken arrows, the positive potential electrodes P _{C1 to} P _{C4 of the} DC capacitors C1 to _C4 → P conductor 1 → the positive terminal P2 → the collector of the semiconductor element TRV , Emitter → V conductor 12 → load → U conductor 11 → collector of semiconductor element TRX, emitter → negative electrode terminal N1 → N conductor 2 → current flows through a path of negative potential electrodes N _{C1 to} N _C4 of DC capacitors C1 to _C4. .

さらに、各直流コンデンサＣ１〜Ｃ４の正電位極Ｐ_C1〜Ｐ_C4からＰ導体１を通して正極端子Ｐ２に流出する電流が生成する磁束と、負極端子Ｎ１からＮ導体２を通して各負電位極Ｎ_C1〜Ｎ_C4に流入する電流が生成する磁束は、半導体素子ＴＲＶとＴＲＸが離間して配設されているため、干渉力が弱く、図４の場合のように打ち消されることはない。 Further, the magnetic flux generated by the current flowing out from the positive potential electrodes P _{C1 to} P _{C4 of} each DC capacitor C1 to _C4 through the P conductor 1 to the positive terminal P2, and the negative potential electrodes N _C1 to N _C1 through the N conductor 2 from the negative terminal N1. The magnetic flux generated by the current flowing into N _C4 has a weak interference force because the semiconductor elements TRV and TRX are spaced apart from each other, and is not canceled as in the case of FIG.

このため、Ｐ導体１、Ｎ導体２を通流する各電流のインダクタンスが大きい。これによって、半導体素子ＴＲＶ，ＴＲＸのターンオフ時に発生するサージ電圧が大きくなり各半導体素子が破損しやすくなる。 For this reason, the inductance of each current flowing through the P conductor 1 and the N conductor 2 is large. As a result, a surge voltage generated when the semiconductor elements TRV and TRX are turned off increases, and each semiconductor element is easily damaged.

尚、直流電源の正、負極端間に並列接続される直流コンデンサの個数は４個に限らず５個以上であってもよい。 Note that the number of DC capacitors connected in parallel between the positive and negative terminals of the DC power supply is not limited to four and may be five or more.

１０１…Ｐ導体
１０２…Ｎ導体
１０３…Ｕ導体
１０４…Ｖ導体
１０５，１０６…絶縁物
１１１…Ｕ端子
１１２…Ｖ端子
Ｃ，Ｃ１〜Ｃ４…直流コンデンサ
Ｐ１，Ｐ２…正極端子
Ｐ_C1〜Ｐ_C4…正電位極
Ｎ１，Ｎ２…負極端子
Ｎ_C1〜Ｎ_C4…負電位極
ＴＲＵ，ＴＲＹ，ＴＲＶ，ＴＲＸ…半導体素子 101 ... P conductors 102 ... N conductors 103 ... U conductors 104 ... V conductors 105, 106 ... insulator 111 ... U terminals 112 ... V terminal C, C1 -C4 ... DC capacitor P1, P2 ... positive terminal P _C1 to P _C4 ... Positive potential electrode N1, N2 ... Negative electrode terminal N _{C1 to} N _C4 ... Negative potential electrode TRU, TRY, TRV, TRX ... Semiconductor element

Claims

直流電源の正、負極端間に並列に接続した複数の直流コンデンサと、前記直流電源の正、負極端間に第１および第２の半導体素子を順次直列に接続した第１の直列回路と、前記直流電源の正、負極端間に第３および第４の半導体素子を順次直列に接続した第２の直列回路と、を備え、
前記第１の直列回路の第１および第２の半導体素子の共通接続点と、前記第２の直列回路の第３および第４の半導体素子の共通接続点との間に交流出力を得る単相インバータにおいて、
第１の半導体素子および第４の半導体素子を互いに近設し、第３の半導体素子および第２の半導体素子を前記第１および第４の半導体素子から離間して互いに近設し、
前記直流電源の正極および前記各直流コンデンサの正電位極が接続される平面導体であって、該平面導体の一端側に設けられ、前記第１の半導体素子のコレクタが接続された第１の正極端子と、該平面導体の他端側に設けられ、前記第３の半導体素子のコレクタが接続された第２の正極端子とを有した第１の導体と、
前記第１の導体に対して所定距離隔てて対向配設され、前記直流電源の負極および前記各直流コンデンサの負電位極が接続される平面導体であって、該平面導体の一端側で且つ前記第１の正極端子の近傍に設けられ、前記第４の半導体素子のエミッタが接続された第１の負極端子と、該平面導体の他端側で且つ前記第２の正極端子の近傍に設けられ、前記第２の半導体素子のエミッタが接続された第２の負極端子と、を有した第２の導体と、
を備えたことを特徴とする単相インバータ装置。 A plurality of DC capacitors connected in parallel between the positive and negative terminals of the DC power supply; a first series circuit in which first and second semiconductor elements are sequentially connected in series between the positive and negative terminals of the DC power supply; A second series circuit in which third and fourth semiconductor elements are sequentially connected in series between the positive and negative terminals of the DC power supply,
A single phase that obtains an AC output between a common connection point of the first and second semiconductor elements of the first series circuit and a common connection point of the third and fourth semiconductor elements of the second series circuit In the inverter,
A first semiconductor element and a fourth semiconductor element are placed close to each other; a third semiconductor element and a second semiconductor element are spaced apart from the first and fourth semiconductor elements;
A planar conductor to which a positive electrode of the DC power source and a positive potential electrode of each DC capacitor are connected, the first positive electrode being provided on one end side of the planar conductor and connected to the collector of the first semiconductor element A first conductor having a terminal and a second positive electrode terminal provided on the other end side of the planar conductor and connected to a collector of the third semiconductor element;
A planar conductor disposed opposite to the first conductor at a predetermined distance to which a negative electrode of the DC power source and a negative potential electrode of each DC capacitor are connected, on one end side of the planar conductor and A first negative electrode terminal provided near the first positive electrode terminal, to which the emitter of the fourth semiconductor element is connected, and provided at the other end of the planar conductor and in the vicinity of the second positive electrode terminal. A second conductor having a second negative electrode terminal to which an emitter of the second semiconductor element is connected;
A single-phase inverter device comprising:

一端が前記第１の半導体素子のエミッタに接続され、他端が前記第２の半導体素子のコレクタに接続され、前記一端と他端の間の中間点を第１交流出力端子とした第３の導体と、
前記第３の導体に対して所定距離隔てて対向配設され、一端が前記第４の半導体素子のコレクタに接続され、他端が前記第３の半導体素子のエミッタに接続され、前記一端と他端の間の中間点を第２交流出力端子とした第４の導体と、
を備えたこと特徴とする請求項１に記載の単相インバータ装置。 One end is connected to the emitter of the first semiconductor element, the other end is connected to the collector of the second semiconductor element, and an intermediate point between the one end and the other end is a first AC output terminal. Conductors,
It is disposed opposite to the third conductor at a predetermined distance, one end is connected to the collector of the fourth semiconductor element, the other end is connected to the emitter of the third semiconductor element, and the other end is connected to the other end. A fourth conductor having a middle point between the ends as a second AC output terminal;
The single-phase inverter device according to claim 1, comprising: