JP2017116455A5 - - Google Patents
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- JP2017116455A5 JP2017116455A5 JP2015253585A JP2015253585A JP2017116455A5 JP 2017116455 A5 JP2017116455 A5 JP 2017116455A5 JP 2015253585 A JP2015253585 A JP 2015253585A JP 2015253585 A JP2015253585 A JP 2015253585A JP 2017116455 A5 JP2017116455 A5 JP 2017116455A5
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- dcir
- input terminal
- differential amplifier
- inverting input
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- 102100004330 CLEC4A Human genes 0.000 description 5
- 101710026577 CLEC4A Proteins 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 1
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Description
蓄電素子の一例としてキャパシタでは直流内部抵抗(DCIR)がキャパシタ性能を表すパラメータのひとつとして用いられる。このDCIRは搭載機器の性能を維持する上で極めて重要である。このDCIRは一定値ではなく、使用状態や使用時間によって劣化する。従って、DCIRは製造時に測定し、その良否の判定は不可欠であるが、搭載機器の性能を維持する上で搭載時ないし搭載後のDCIR特性の監視が求められている。
As an example of a storage element, in a capacitor, a direct current internal resistance (DCIR ) is used as one of the parameters representing the capacitor performance. This DCIR is extremely important in maintaining the performance of the on-board equipment. This DCIR is not a constant value, but deteriorates depending on the use state and use time. Therefore, although DCIR is measured at the time of manufacture and it is indispensable to determine whether it is good or bad, monitoring of the DCIR characteristics during or after mounting is required to maintain the performance of the mounted device.
差動増幅器10の非反転入力端子(+)には電圧Vdが加えられ、その反転入力端子(−)には電圧Vcが加えられる。差動増幅器10では、これら電圧Vd−Vc間の差電圧ΔVの検出が行われると同時に、この差電圧ΔVの増幅が行われる。
A voltage Vd is applied to the non- inverting input terminal (+) of the
この実施例においても、差動増幅器10の非反転入力端子(+)には電圧Vdが加えられ、その反転入力端子(−)には電圧Vcが加えられる。差動増幅器10では、これら電圧Vd−Vc間の差電圧ΔVの検出が行われると同時に、この差電圧ΔVの増幅が行われる。
Also in this embodiment, the voltage Vd is applied to the non- inverting input terminal (+) of the
スイッチ18を閉じる放電停止時点t1の被測定キャパシタ4の電圧Vcが電圧Vdとして電解コンデンサ22に保持される。この電圧Vdが差動増幅器10の非反転入力端子(+)に入力される。
The voltage Vc of the capacitor 4 to be measured at the discharge stop time t1 when the
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2015253585A JP6662033B2 (en) | 2015-12-25 | 2015-12-25 | Method and apparatus for measuring resistance of storage element |
Applications Claiming Priority (1)
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JP2015253585A JP6662033B2 (en) | 2015-12-25 | 2015-12-25 | Method and apparatus for measuring resistance of storage element |
Publications (3)
Publication Number | Publication Date |
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JP2017116455A JP2017116455A (en) | 2017-06-29 |
JP2017116455A5 true JP2017116455A5 (en) | 2018-12-06 |
JP6662033B2 JP6662033B2 (en) | 2020-03-11 |
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JP2015253585A Active JP6662033B2 (en) | 2015-12-25 | 2015-12-25 | Method and apparatus for measuring resistance of storage element |
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JP (1) | JP6662033B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7153458B2 (en) * | 2018-03-26 | 2022-10-14 | ラピスセミコンダクタ株式会社 | Semiconductor equipment and electronic equipment |
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2015
- 2015-12-25 JP JP2015253585A patent/JP6662033B2/en active Active
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