JP2016167473A - Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate - Google Patents

Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate Download PDF

Info

Publication number
JP2016167473A
JP2016167473A JP2013146715A JP2013146715A JP2016167473A JP 2016167473 A JP2016167473 A JP 2016167473A JP 2013146715 A JP2013146715 A JP 2013146715A JP 2013146715 A JP2013146715 A JP 2013146715A JP 2016167473 A JP2016167473 A JP 2016167473A
Authority
JP
Japan
Prior art keywords
nitride semiconductor
substrate
layer
semiconductor multilayer
multilayer substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013146715A
Other languages
Japanese (ja)
Inventor
淳 小河
Atsushi Ogawa
淳 小河
信明 寺口
Nobuaki Teraguchi
信明 寺口
伸之 伊藤
Nobuyuki Ito
伸之 伊藤
雄史 井上
Yushi Inoue
雄史 井上
舞 岡崎
Mai Okazaki
舞 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2013146715A priority Critical patent/JP2016167473A/en
Priority to PCT/JP2014/066197 priority patent/WO2015005083A1/en
Publication of JP2016167473A publication Critical patent/JP2016167473A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor lamination substrate, a nitride semiconductor device, and a method of manufacturing a nitride semiconductor lamination substrate, capable of suppressing generation of pits on a nitride semiconductor layer.SOLUTION: A nitride semiconductor lamination substrate 111 comprises: an Si substrate 101 that uses a plane inclined at an off angle equal to or more than 0.11 degrees and equal to or less than 0.50 degrees in a (011) direction from a (111) plane as a principal surface; and at least one nitride semiconductor layer 102, 103 epitaxially grown on the Si substrate 101.SELECTED DRAWING: Figure 1

Description

この発明は、窒化物半導体積層基板、窒化物半導体装置および窒化物半導体積層基板の製造方法に関する。   The present invention relates to a nitride semiconductor multilayer substrate, a nitride semiconductor device, and a method for manufacturing a nitride semiconductor multilayer substrate.

窒化物半導体は、一般式ＩｎｘＡｌyＧａ1−x−yＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｘ＋ｙ≦１）で表される。この窒化物半導体は、その組成によって、バンドギャップを１．９５ｅＶ〜６ｅＶの範囲で変化させることができることから、紫外域から赤外域に及ぶ広波長範囲の発光デバイスの材料として研究開発され、実用化されている。 Nitride semiconductor is represented by the general formula In x Al y Ga 1-x -y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1). Since this nitride semiconductor can change the band gap in the range of 1.95 eV to 6 eV depending on its composition, it has been researched and developed as a material for light emitting devices in a wide wavelength range from the ultraviolet region to the infrared region, and put into practical use. Has been.

また、窒化物半導体を用いた制御デバイスは、高周波かつ高出力で動作するパワー素子などに用いられており、中でも、高周波帯域での増幅に適した制御デバイスとして、例えば高電子移動度トランジスタ（ＨＥＭＴ）などのＦＥＴが知られている。   A control device using a nitride semiconductor is used for a power element that operates at high frequency and high output. Among them, as a control device suitable for amplification in a high frequency band, for example, a high electron mobility transistor (HEMT) is used. ) And the like are known.

従来、窒化物半導体積層基板としては、特開２００８−１６６３４９号公報（特許文献１）に記載のものがある。この従来の窒化物半導体積層基板は、Ｓｉ基板上に、バリア層としてＡｌＮ層と、Ａｌ組成を層厚方向に変化させたバッファ層としてのＡｌＧａＮ層と、ＧａＮ層を順次エピタキシャル成長している。   Conventionally, as a nitride semiconductor multilayer substrate, there is one described in JP 2008-166349 A (Patent Document 1). In this conventional nitride semiconductor multilayer substrate, an AlN layer as a barrier layer, an AlGaN layer as a buffer layer in which the Al composition is changed in the layer thickness direction, and a GaN layer are sequentially epitaxially grown on a Si substrate.

このように、上記従来の窒化物半導体積層基板は、Ｓｉ基板を用いているから、サファイア基板やＳｉＣ（炭化シリコン）基板を用いる場合に比べて、安価であり、また、ＡｌＮ層とＧａＮ層との間に、Ａｌ組成を層厚方向に変化させたＡｌＧａＮ層を挟み込んでいるから、反り、クラックの発生が少ないという利点を有する。   Thus, since the conventional nitride semiconductor multilayer substrate uses a Si substrate, it is less expensive than the case of using a sapphire substrate or a SiC (silicon carbide) substrate, and the AlN layer and the GaN layer Since an AlGaN layer having an Al composition changed in the layer thickness direction is sandwiched between them, there is an advantage that warpage and generation of cracks are small.

特開２００８−１６６３４９号公報JP 2008-166349 A

しかしながら、上記従来の窒化物半導体積層基板には、Ｓｉ基板上に形成されたＡｌＮ層の表面、および、そのＡｌＮ直上のＡｌＧａＮ層の表面にピットが発生しやすいという問題がある。   However, the conventional nitride semiconductor multilayer substrate has a problem that pits are easily generated on the surface of the AlN layer formed on the Si substrate and the surface of the AlGaN layer immediately above the AlN.

このピットは、ＳｉとＡｌＮの格子定数差から生じる貫通転位が発生起源になっていると考えられ、そのピット上にＧａＮ層などの窒化物半導体層を成長させて、窒化物半導体装置を製造した場合、リーク等の要因となるため、発光デバイスならびに制御デバイスともに、その特性に悪い影響を与える。   These pits are thought to originate from threading dislocations resulting from the difference in lattice constant between Si and AlN, and a nitride semiconductor layer such as a GaN layer was grown on the pits to produce a nitride semiconductor device. In this case, since it becomes a factor such as a leak, both the light emitting device and the control device adversely affect the characteristics.

そこで、この発明の課題は、窒化物半導体層にピットが発生するのを抑制することが可能な窒化物半導体積層基板、窒化物半導体装置および窒化物半導体積層基板の製造方法を提供することにある。   Accordingly, an object of the present invention is to provide a nitride semiconductor multilayer substrate, a nitride semiconductor device, and a method for manufacturing the nitride semiconductor multilayer substrate capable of suppressing the occurrence of pits in the nitride semiconductor layer. .

上記課題を解決するため、この発明の窒化物半導体積層基板は、
（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板と、
このＳｉ基板の上にエピタキシャル成長した少なくとも１つの窒化物半導体層と
を備えることを特徴としている。 In order to solve the above problems, the nitride semiconductor multilayer substrate of the present invention is
A Si substrate having a main surface that is inclined at an off angle of 0.11 degrees or more and 0.50 degrees or less in the (011) direction from the (111) plane;
And at least one nitride semiconductor layer epitaxially grown on the Si substrate.

また、この発明の窒化物半導体装置は、
上述の窒化物半導体積層基板と、
上記窒化物半導体積層基板上に積層された窒化物半導体層と、
上記窒化物半導体層上に設けた電極と
を備えることを特徴としている。 The nitride semiconductor device of the present invention is
The above-mentioned nitride semiconductor multilayer substrate;
A nitride semiconductor layer stacked on the nitride semiconductor multilayer substrate;
And an electrode provided on the nitride semiconductor layer.

また、この発明の窒化物半導体積層基板の製造方法は、
（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板を準備する工程と、
上記Ｓｉ基板の主面の上に、少なくとも１つの窒化物半導体層をエピタキシャル成長する工程と
を備えることを特徴としている。 In addition, the method for manufacturing the nitride semiconductor multilayer substrate of the present invention includes:
Preparing a Si substrate whose main surface is a plane inclined at an off angle of 0.11 degree or more and 0.50 degree or less in the (011) direction from the (111) plane;
And a step of epitaxially growing at least one nitride semiconductor layer on the main surface of the Si substrate.

この発明によれば、窒化物半導体層のピットを抑制することができて、窒化物半導体装置の特性を大幅に改善することができる。   According to the present invention, pits in the nitride semiconductor layer can be suppressed, and the characteristics of the nitride semiconductor device can be greatly improved.

この発明の第１実施形態の窒化物半導体積層基板の断面模式図である。1 is a schematic cross-sectional view of a nitride semiconductor multilayer substrate according to a first embodiment of the present invention. Ｓｉ基板の主面の（１１１）面から（０１１）方向へのオフ角と、ピット数との関係を示すグラフである。It is a graph which shows the relationship between the off angle from the (111) plane of the main surface of a Si substrate to the (011) direction, and the number of pits. この発明の第２実施形態の窒化物半導体積層基板の断面模式図である。It is a cross-sectional schematic diagram of the nitride semiconductor multilayer substrate of 2nd Embodiment of this invention. Ａｌ層の層厚とピット数と関係を示すグラフである。It is a graph which shows the layer thickness and the number of pits of an Al layer. この発明の第３実施形態の窒化物半導体積層基板の断面模式図である。It is a cross-sectional schematic diagram of the nitride semiconductor multilayer substrate of 3rd Embodiment of this invention. ＡｌＮ層の（０００２）面のＸ線回折におけるロッキングカーブの半値幅とピット数との関係を示すグラフである。It is a graph which shows the relationship between the half value width of the rocking curve in the X-ray diffraction of the (0002) plane of an AlN layer, and the number of pits. この発明の第４実施形態の窒化物半導体積層基板の断面模式図である。It is a cross-sectional schematic diagram of the nitride semiconductor multilayer substrate of 4th Embodiment of this invention. この発明の第６実施形態のヘテロ接合電界効果トランジスタ（ＨＦＥＴ）の要部を示す概略断面図である。It is a schematic sectional drawing which shows the principal part of the heterojunction field effect transistor (HFET) of 6th Embodiment of this invention.

（第１実施形態）（ＡｌＮ層／Ｓｉ基板 オフ角依存性）
図１に示すように、第１実施形態の窒化物半導体積層基板１１１は、Ｓｉ基板１０１と、このＳｉ基板１０１上にエピタキシャル成長した窒化物半導体層の一例としてのＡｌＮ層１０２と、このＡｌＮ層１０２上にエピタキシャル成長した窒化物半導体層の一例としてのＡｌＧａＮ層１０３とからなる。 First Embodiment (AlN layer / Si substrate off angle dependency)
As shown in FIG. 1, a nitride semiconductor multilayer substrate 111 according to the first embodiment includes a Si substrate 101, an AlN layer 102 as an example of a nitride semiconductor layer epitaxially grown on the Si substrate 101, and the AlN layer 102. The AlGaN layer 103 is an example of a nitride semiconductor layer epitaxially grown thereon.

上記Ｓｉ基板１０１は、（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面としている。   The Si substrate 101 has a main surface inclined from the (111) plane in the (011) direction at an off angle of 0.11 degrees or more and 0.50 degrees or less.

上記ＡｌＮ層１０２は、バリア層として機能し、ＡｌＧａＮ層１０３は、バッファ層として機能する。   The AlN layer 102 functions as a barrier layer, and the AlGaN layer 103 functions as a buffer layer.

この明細書で、窒化物半導体とは、例えば、ＧａＮ、ＡｌＮ、ＡｌＧａＮ、ＩｎＧａＮ等のことを言い、より詳しくは、一般式ＩｎｘＡｌyＧａ1−x−yＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｘ＋ｙ≦１）で表される半導体のことを言う。 In this specification, the nitride semiconductor, e.g., GaN, said AlN, AlGaN, that of InGaN or the like, and more particularly, the general formula In x Al y Ga 1-x -y N (0 ≦ x ≦ 1, A semiconductor represented by 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

次に、上記窒化物半導体積層基板１１１の製造工程を、比較例と対比しつつ、説明する。下記のサンプル１，５は、比較例であり、サンプル２〜４は、この第１実施形態に含まれるものである。   Next, the manufacturing process of the nitride semiconductor multilayer substrate 111 will be described in comparison with a comparative example. Samples 1 and 5 below are comparative examples, and Samples 2 to 4 are included in the first embodiment.

まず、Ｓｉ基板のサンプルとして、
（１１１）面から（０１１）方向に、０．０７度のオフ角度で傾斜した面を主面とするサンプル１のＳｉ基板（図示せず）と、
（１１１）面から（０１１）方向に、０．１１度のオフ角度で傾斜した面を主面とするサンプル２のＳｉ基板１０１と、
（１１１）面から（０１１）方向に、０．２０度のオフ角度で傾斜した面を主面とするサンプル３のＳｉ基板１０１と、
（１１１）面から（０１１）方向に、０．５０度のオフ角度で傾斜した面を主面とするサンプル４のＳｉ基板１０１と、
（１１１）面から（０１１）方向に、０．６０度のオフ角度で傾斜した面を主面とするサンプル５のＳｉ基板（図示せず）と
の５種類のサンプルのＳｉ基板を準備した。 First, as a sample of the Si substrate,
A Si substrate (not shown) of Sample 1 whose main surface is a surface inclined at an off angle of 0.07 degrees in the (011) direction from the (111) plane;
Si substrate 101 of sample 2 whose main surface is a plane inclined at an off angle of 0.11 degrees from the (111) plane to the (011) direction;
Si substrate 101 of sample 3 whose main surface is a surface inclined at an off angle of 0.20 degrees in the (011) direction from the (111) plane;
Si substrate 101 of sample 4 whose main surface is a surface inclined at an off angle of 0.50 degrees in the (011) direction from the (111) plane;
Five types of sample Si substrates were prepared: a sample 5 Si substrate (not shown) whose main surface is a surface inclined at an off angle of 0.60 degrees from the (111) plane to the (011) direction.

比較例のサンプル１，５のＳｉ基板（図示せず）は、図１に示すＳｉ基板１０１に相当しなく、一方、サンプル２〜４のＳｉ基板１０１は、図１に示すＳｉ基板１０１に相当する。   The Si substrates (not shown) of samples 1 and 5 of the comparative example do not correspond to the Si substrate 101 shown in FIG. 1, while the Si substrates 101 of samples 2 to 4 correspond to the Si substrate 101 shown in FIG. To do.

この５種類のサンプルのＳｉ基板を希釈フッ酸で処理し、Ｓｉ基板の自然酸化膜を除去した。その後、Ｓｉ基板をＭＯＣＶＤ（有機金属気相成長：Metal Organic Chemical Vapor Deposition）装置のリアクタ内に導入した。次に、５種類のサンプルのＳｉ基板の温度を１１００℃に昇温した後、ＮＨ3（アンモニア）およびＴＭＡ（トリメチルアルミニウム）を供給し、Ｓｉ基板の主面に、ＡｌＮ層１０２を成長速度４００ｎｍ／ｈｒで、１８０ｎｍ成長した。 The Si substrates of these five types of samples were treated with diluted hydrofluoric acid to remove the natural oxide film on the Si substrate. Thereafter, the Si substrate was introduced into a reactor of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus. Next, after raising the temperature of the Si substrate of the five types of samples to 1100 ° C., NH 3 (ammonia) and TMA (trimethylaluminum) are supplied, and an AlN layer 102 is grown on the main surface of the Si substrate at a growth rate of 400 nm. / Hr at 180 nm.

次に、５種類のサンプルのＳｉ基板の温度を１１００℃にしたまま、ＮＨ3、ＴＭＡおよびＴＭＧ（トリメチルガリウム）を供給し、上記ＡｌＮ層１０２上に、厚さ２００ｎｍでＡｌ組成比０．６のＡｌＧａＮバッファ層１０３をエピタキシャル成長した。 Next, NH 3 , TMA, and TMG (trimethylgallium) are supplied while keeping the temperature of the Si substrate of the five types of samples at 1100 ° C., and an Al composition ratio of 0.6 nm is formed on the AlN layer 102. The AlGaN buffer layer 103 was epitaxially grown.

以上の製造工程により、Ｓｉ基板１０１の主面上に、ＡｌＮ層１０２、ＡｌＧａＮバッファ層１０３が設けられた窒化物半導体積層基板が得られた。   Through the above manufacturing process, a nitride semiconductor multilayer substrate in which the AlN layer 102 and the AlGaN buffer layer 103 were provided on the main surface of the Si substrate 101 was obtained.

上記製造方法により製造した
上述の０．０７度のオフ角度のサンプル１のＳｉ基板を用いた窒化物半導体積層基板（サンプル１−１：比較例）と、
上述の０．１１度のオフ角度のサンプル２のＳｉ基板１０１を用いた窒化物半導体積層基板１１１（サンプル１−２）と、
上述の０．２０度オフ角度のサンプル３のＳｉ基板１０１を用いた窒化物半導体積層基板１１１（サンプル１−３）と、
上述の０．５０度のオフ角度のサンプル４のＳｉ基板を用いた窒化物半導体積層基板１１１（サンプル１−４）と、
上述の０．６０度のオフ角度のサンプル５のＳｉ基板を用いた窒化物半導体積層基板１１１（サンプル１−５：比較例）と
の５種類の窒化物半導体積層基板夫々に対して、ＡｌＧａＮ層１０３の表面状態をＳＥＭ（走査型電子顕微鏡）で観察した。 A nitride semiconductor multilayer substrate (sample 1-1: comparative example) using the Si substrate of sample 1 having an off-angle of 0.07 degrees manufactured by the above-described manufacturing method;
A nitride semiconductor multilayer substrate 111 (sample 1-2) using the Si substrate 101 of the sample 2 having an off angle of 0.11 degrees as described above;
A nitride semiconductor multilayer substrate 111 (sample 1-3) using the Si substrate 101 of the sample 3 having the 0.20 degree off-angle described above;
A nitride semiconductor multilayer substrate 111 (sample 1-4) using the Si substrate of sample 4 having an off angle of 0.50 degrees as described above;
For each of the five types of nitride semiconductor multilayer substrates with the above-described nitride semiconductor multilayer substrate 111 (sample 1-5: comparative example) using the Si substrate of sample 5 having an off angle of 0.60 degrees, an AlGaN layer is provided. The surface state of 103 was observed with an SEM (scanning electron microscope).

その結果、ＡｌＧａＮ層１０３の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数について、２０μｍ□エリア（５箇所）内の平均数は、
サンプル１−１は１５.５個、
サンプル１−２は０．９個、
サンプル１−３は０．５個、
サンプル１−４は０．８個、
サンプル１−５は１１．３個
であった。 As a result, with respect to the number of pits having a diameter of 10 nm or more and 50 nm or less on the surface of the AlGaN layer 103, the average number in a 20 μm square area (5 locations) is:
Sample 1-1 is 15.5 pieces,
Sample 1-2 is 0.9 pieces,
Sample 1-3 is 0.5 pieces,
Sample 1-4 is 0.8 pieces
Sample 1-5 was 11.3 pieces.

この状態を、図２に片対数グラフで示している。   This state is shown in a semilogarithmic graph in FIG.

この図２から、この第１実施形態にように、Ｓｉ基板１０１が、（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角を有すると、窒化物半導体積層基板１１１の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数が著しく低減できることが分かる。この第１実施形態のように、窒化物半導体積層基板１１１の表面のピット数が少ないと、この窒化物半導体積層基板１１１を用いた窒化物半導体装置（図示せず）のリーク電流を低減できる。   As shown in FIG. 2, when the Si substrate 101 has an off angle of 0.11 degree or more and 0.50 degree or less in the (011) direction from the (111) plane as in the first embodiment, nitride is obtained. It can be seen that the number of pits having a diameter of 10 nm or more and 50 nm or less can be remarkably reduced on the surface of the semiconductor laminated substrate 111. If the number of pits on the surface of the nitride semiconductor multilayer substrate 111 is small as in the first embodiment, the leakage current of a nitride semiconductor device (not shown) using the nitride semiconductor multilayer substrate 111 can be reduced.

上記の現象に関して、上記オフ角が０．１１度以上の場合は、成長表面のテラス幅が短くなり、ＡｌＮとＳｉの格子定数差から生じる歪を緩和しやすくでき、貫通転位の発生、しいては貫通転位から生じるピットを抑制することができると推定される。また、上記オフ角が０．５０度より大きい場合は、ＡｌＮが成長表面をマイグレーションする能力が小さいため、テラス上に核が形成されて、マクロ的には３次元状に成長し、核同士が会合したエリアで転位が発生すると考えられる。   Regarding the above phenomenon, when the off angle is 0.11 degrees or more, the terrace width of the growth surface is shortened, the strain caused by the difference in lattice constant between AlN and Si can be easily relaxed, and threading dislocations are generated. Is presumed to be able to suppress pits resulting from threading dislocations. When the off angle is larger than 0.50 degrees, AlN has a small ability to migrate the growth surface, so that nuclei are formed on the terrace and grow macroscopically in a three-dimensional manner. Dislocations are thought to occur in the meeting area.

この第１実施形態では、Ｓｉ基板１０１が、（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角を有するので、エピタキシャル成長表面のテラス幅が短くなって、ＡｌＮとＳｉの格子定数差から生じる歪を緩和しやすくでき、貫通転位の発生を抑制でき、ひいては、貫通転位から生じるピットの発生を抑制することができる。   In the first embodiment, since the Si substrate 101 has an off angle of 0.11 degrees or more and 0.50 degrees or less in the (011) direction from the (111) plane, the terrace width of the epitaxial growth surface is shortened. Further, it is possible to easily relax the strain caused by the difference in lattice constant between AlN and Si, to suppress the generation of threading dislocations, and to suppress the generation of pits resulting from threading dislocations.

（第２実施形態）（ＡｌＮ層/Ｓｉ基板 ＡｌＮ層層厚依存性）
図３は、第２実施形態の窒化物半導体積層基板２１１の断面模式図であり、この窒化物半導体積層基板２１１は、Ｓｉ基板２０１上に、ＡｌＮ層２０２と、ＡｌＧａＮ層２０３とを積層してなる。 Second Embodiment (AlN Layer / Si Substrate AlN Layer Thickness Dependence)
FIG. 3 is a schematic cross-sectional view of the nitride semiconductor multilayer substrate 211 of the second embodiment. The nitride semiconductor multilayer substrate 211 is formed by laminating an AlN layer 202 and an AlGaN layer 203 on an Si substrate 201. Become.

上記窒化物半導体積層基板２１１は、第１実施形態と同様の方法で作製し、Ｓｉ基板２０１上に、バリア層として機能するＡｌＮ層２０２と、バッファ層として機能するＡｌＧａＮ層２０３とを順次エピタキシャル成長している。   The nitride semiconductor multilayer substrate 211 is produced by the same method as in the first embodiment, and an AlN layer 202 functioning as a barrier layer and an AlGaN layer 203 functioning as a buffer layer are sequentially epitaxially grown on the Si substrate 201. ing.

詳細は、以下の通りである。上記Ｓｉ基板２０１は、（１１１）面から（０１１）方向に、０．２０度のオフ角で傾斜した面を主面としている。   Details are as follows. The Si substrate 201 has a main surface inclined from the (111) plane in the (011) direction at an off angle of 0.20 degrees.

上記Ｓｉ基板２０１上のＡｌＮ層２０２は、層厚が
４０ｎｍ（サンプル２−１）と、
５０ｎｍ（サンプル２−２）と、
１００ｎｍ（サンプル２−３）と、
１８０ｎｍ（サンプル２−４）と、
４００ｎｍ（サンプル２−５）と、
４５０ｎｍ（サンプル２−６）と、
５００ｎｍ（サンプル２−７）と
の７種類のものを作成し、それらのＡｌＮ層２０２上に、同じＡｌＧａＮ層２０３を積層して、７種類の半導体積層基板２１１を製造した。 The AlN layer 202 on the Si substrate 201 has a layer thickness of 40 nm (Sample 2-1).
50 nm (Sample 2-2),
100 nm (Sample 2-3),
180 nm (sample 2-4),
400 nm (sample 2-5),
450 nm (sample 2-6),
Seven types of 500 nm (sample 2-7) were prepared, and the same AlGaN layer 203 was laminated on the AlN layer 202 to produce seven types of semiconductor laminated substrates 211.

上述の７種類の半導体積層基板２１１の夫々に対して、ＡｌＧａＮ層２０３の表面状態をＳＥＭ（走査型電子顕微鏡）で観察した。   The surface state of the AlGaN layer 203 was observed with a scanning electron microscope (SEM) for each of the seven types of semiconductor multilayer substrates 211 described above.

その結果、上記ＡｌＧａＮ層２０３の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数について、２０μｍ□エリア（５箇所）内の平均数は、
サンプル２−１は２５．６個、
サンプル２−２は１．３個、
サンプル２−３は０．８個、
サンプル２−４は０．５個、
サンプル２−５は１．４個
サンプル２−６は１３．８個、
サンプル２−７は２１．７個
であった。 As a result, with respect to the number of pits having a diameter of 10 nm or more and 50 nm or less on the surface of the AlGaN layer 203, the average number in a 20 μm square area (5 locations) is:
Sample 2-1 is 25.6,
1.3 samples 2-2
Sample 2-3 is 0.8 pieces,
Sample 2-4 is 0.5 pieces,
Sample 2-5 is 1.4 Sample 2-6 is 13.8
There were 21.7 samples 2-7.

この状態を、図４に片対数グラフで示している。   This state is shown in a semilogarithmic graph in FIG.

この図４から、ＡｌＮ層２０３の層厚が５０ｎｍ以上、４００ｎｍ以下であると、ＡｌＧａＮ層２０３の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数が著しく減少することが分かる。この第２実施形態では、ＡｌＮ層２０２の層厚を、５０ｎｍ以上、４００ｎｍ以下にしている。   4 that the number of pits having a diameter of 10 nm or more and 50 nm or less on the surface of the AlGaN layer 203 is remarkably reduced when the thickness of the AlN layer 203 is 50 nm or more and 400 nm or less. In the second embodiment, the thickness of the AlN layer 202 is set to 50 nm or more and 400 nm or less.

なお、ここでは、上記Ｓｉ基板２０１は、（１１１）面から（０１１）方向に、０．２０度のオフ角で傾斜した面を主面としているが、Ｓｉ基板２０１が、（１１１）面から（０１１）方向に、０．１１から０．５０度のオフ角で傾斜した面を主面としていても、図４と同じ傾向が得られた。   Here, the Si substrate 201 has a main surface inclined at an off angle of 0.20 degrees in the (011) direction from the (111) plane, but the Si substrate 201 is separated from the (111) plane. The same tendency as in FIG. 4 was obtained even when the main surface was inclined at an off angle of 0.11 to 0.50 degrees in the (011) direction.

この第２施形態のように、窒化物半導体積層基板２１の表面のピット数が少ないと、この窒化物半導体積層基板２１１を用いた窒化物半導体装置（図示せず）は、リーク電流の低減等の電気的な特性が改善できる。   If the number of pits on the surface of the nitride semiconductor multilayer substrate 21 is small as in the second embodiment, a nitride semiconductor device (not shown) using the nitride semiconductor multilayer substrate 211 can reduce leakage current, etc. The electrical characteristics of can be improved.

上記の現象に関して、ＡｌＮ層２０２の層厚が５０ｎｍより薄い場合、ＡｌＮ層２０２がバリア層つまりカバー層として充分に機能せず、ＡｌＧａＮ層２０３の成長時に使用するＴＭＧのＧａとＳｉ基板が反応して、基板表面を荒らして、ピット等の発生要因となる貫通転位が発生しやすくなったと推定される。   Regarding the above phenomenon, when the thickness of the AlN layer 202 is thinner than 50 nm, the AlN layer 202 does not sufficiently function as a barrier layer, that is, a cover layer, and the TMG Ga used during the growth of the AlGaN layer 203 reacts with the Si substrate. Thus, it is presumed that the surface of the substrate is roughened, and threading dislocations that cause pits are more likely to occur.

また、ＡｌＮ層２０２の層厚が４００ｎｍよりも厚い場合、ＡｌＮ層２０２およびＡｌＧａＮ層２０３の成長中に、ＳｉとＡｌＮの格子定数差が要因となる基板の反りが大きくなって、ＡｌＮ層２０２、ＡｌＧａＮ層２０３に歪応力が加わって、ピットが発生しやすくなったと考えられる。   Further, when the thickness of the AlN layer 202 is larger than 400 nm, during the growth of the AlN layer 202 and the AlGaN layer 203, the warpage of the substrate due to the difference in lattice constant between Si and AlN increases, and the AlN layer 202, It is considered that strain was applied to the AlGaN layer 203 and pits were easily generated.

（第３実施形態）（ＡｌＮ層／Ｓｉ基板 結晶性依存性）
図５は、第３実施形態の窒化物半導体積層基板３１１の断面模式図であり、この窒化物半導体積層基板３１１は、Ｓｉ基板３０１上に、ＡｌＮ層３０２、ＡｌＧａＮ層３０３をエピタキシャル成長してなる。 Third Embodiment (AlN layer / Si substrate crystallinity dependency)
FIG. 5 is a schematic cross-sectional view of the nitride semiconductor multilayer substrate 311 of the third embodiment. The nitride semiconductor multilayer substrate 311 is obtained by epitaxially growing an AlN layer 302 and an AlGaN layer 303 on a Si substrate 301.

上記窒化物半導体積層基板３１１は、第１および第２実施形態と同様の方法で作製し、Ｓｉ基板３０１上に、バリア層として機能するＡｌＮ層３０２と、バッファ層として機能するＡｌＧａＮ層３０３とを順次エピタキシャル成長している。   The nitride semiconductor multilayer substrate 311 is manufactured by the same method as in the first and second embodiments. On the Si substrate 301, an AlN layer 302 that functions as a barrier layer and an AlGaN layer 303 that functions as a buffer layer are formed. Sequentially epitaxial growth.

詳細は、以下の通りである。上記Ｓｉ基板３０１は、（１１１）面から（０１１）方向に、０．２０度のオフ角で傾斜した面を主面としている。上記ＡｌＮ層３０２は、層厚が１８０ｎｍであり、そのＡｌＮ層３０２の成長速度を変化させて、（０００２）面のＸ線回折におけるロッキングカーブの半値幅が異なるサンプルを製造した。ＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅の調整は、Ｓｉ基板３０１上に、各ＡｌＮ層３０２を成長させるときの成長速度を変化させて行った。   Details are as follows. The Si substrate 301 has a main surface inclined from the (111) plane in the (011) direction at an off angle of 0.20 degrees. The AlN layer 302 had a layer thickness of 180 nm, and samples with different half-value widths of rocking curves in (0002) plane X-ray diffraction were manufactured by changing the growth rate of the AlN layer 302. The half-value width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 was adjusted by changing the growth rate when each AlN layer 302 was grown on the Si substrate 301.

そして、ＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅が
１９００arcsec（サンプル３−１）と、
２２００arcsec（サンプル３−２）と、
２５００arcsec（サンプル３−３）と、
２６５０arcsec（サンプル３−４）と
の４種類の窒化物半導体積層基板３１１を製造した。 And the half width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 is 1900 arcsec (sample 3-1),
2200 arcsec (sample 3-2),
2500 arcsec (sample 3-3),
Four types of nitride semiconductor multilayer substrates 311 with 2650 arcsec (sample 3-4) were manufactured.

この４種類の窒化物半導体積層基板３１１の夫々に対して、ＡｌＧａＮ層３０３の表面状態をＳＥＭ（走査型電子顕微鏡）で観察した。   The surface state of the AlGaN layer 303 was observed with an SEM (scanning electron microscope) for each of the four types of nitride semiconductor multilayer substrates 311.

その結果、上記ＡｌＧａＮ層３０３の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数について、２０μｍ□エリア（５箇所）内の平均数は、
サンプル３−１は０．５個、
サンプル３−２は０．８個、
サンプル３−３は１．８個、
サンプル３−４は１２．３個、
であった。 As a result, with respect to the number of pits having a diameter of 10 nm or more and 50 nm or less on the surface of the AlGaN layer 303, the average number in a 20 μm square area (5 locations) is:
Sample 3-1 is 0.5 pieces,
Sample 3-2 is 0.8 pieces,
Sample 3-3 is 1.8 pieces,
Sample 3-4 has 12.3 pieces,
Met.

この状態を、図６に片対数グラフで示している。   This state is shown in a semilogarithmic graph in FIG.

この図６から、Ｓｉ基板３０１上のＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅は、２５００arcsec以下が好ましいことが分かる。   FIG. 6 shows that the half-value width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 on the Si substrate 301 is preferably 2500 arcsec or less.

この現象に関して、ＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅が２５００arcsecよりも大きくなると、結晶性が悪い場合に、ピットの要因となる貫通転位等が入り易くなったと考えられる。   Regarding this phenomenon, it is considered that when the half-value width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 is larger than 2500 arcsec, threading dislocations and the like that cause pits are likely to occur when the crystallinity is poor. It is done.

逆に、上記ＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅が２５００arcsec以下であると貫通転位が比較的少なくなって、ＡｌＧａＮ層３０を積層する際に、ＳｉとＧａの反応を抑制し、また結晶性が良好なため貫通転位の発生、ひいてはピットの発生を抑制することが可能となったと考えられる。   Conversely, if the half-value width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 is 2500 arcsec or less, threading dislocations are relatively small, and when the AlGaN layer 30 is stacked, Si and Ga It is considered that the reaction was suppressed and the crystallinity was good, so that it was possible to suppress the occurrence of threading dislocations, and hence the generation of pits.

なお、ここでは、上記Ｓｉ基板３０１は、（１１１）面から（０１１）方向に、０．２０度のオフ角で傾斜した面を主面としているが、Ｓｉ基板２０１が、（１１１）面から（０１１）方向に、０．１１から０．５０度のオフ角で傾斜した面を主面としていても、図６と同じ傾向が得られる。また、上記ＡｌＮ層３０２は、層厚が１８０ｎｍであったが、ＡｌＮ層３０２の層厚が５０ｎｍ以上、４００ｎｍ以下であっても、層厚が１８０ｎｍの場合と略同様の結果が得られた。   Here, the Si substrate 301 has a main surface inclined at an off angle of 0.20 degrees in the (011) direction from the (111) plane, but the Si substrate 201 is separated from the (111) plane. The same tendency as in FIG. 6 can be obtained even if the main surface is an inclined surface with an off angle of 0.11 to 0.50 degrees in the (011) direction. The AlN layer 302 had a thickness of 180 nm. However, even when the thickness of the AlN layer 302 was not less than 50 nm and not more than 400 nm, substantially the same result as that obtained when the layer thickness was 180 nm was obtained.

（第４実施形態）（ＧａＮ層／ＡｌＧａＮ層／ＡｌＮ層／Ｓｉ基板 ＡｌＮ層混晶比、ＧａＮ層の層厚）
図７は、第４実施形態の窒化物半導体積層基板４１１の断面模式図である。この窒化物半導体積層基板４１１は、Ｓｉ基板１０１上に、ＡｌＮ層１０２とＡｌＧａＮ層４０３とＧａＮ層４０４とを順次エピタキシャル成長してなる。 (Fourth Embodiment) (GaN layer / AlGaN layer / AlN layer / Si substrate AlN layer mixed crystal ratio, GaN layer thickness)
FIG. 7 is a schematic cross-sectional view of the nitride semiconductor multilayer substrate 411 of the fourth embodiment. The nitride semiconductor multilayer substrate 411 is obtained by epitaxially growing an AlN layer 102, an AlGaN layer 403, and a GaN layer 404 on a Si substrate 101 in order.

上記Ｓｉ基板１０１およびＡｌＮ層１０２は、第１実施形態のＳｉ基板１０１およびＡｌＮ層１０２と同じ構成を有するので、第１実施形態と同じ参照番号を付して、詳しい説明は省略する。   Since the Si substrate 101 and the AlN layer 102 have the same configuration as the Si substrate 101 and the AlN layer 102 of the first embodiment, the same reference numerals as those in the first embodiment are assigned and detailed description thereof is omitted.

上記ＡｌＧａＮ層４０３は、ＡｌｘＧａ1−xＮ層（０.３≦ｘ≦０．８）である。つまり、上記ＡｌＧａＮ層４０３のＡｌ組成は、３０％以上、８０％以下である。また、上記ＧａＮ層４０４は、１００ｎｍ以上の層厚を有する。 The AlGaN layer 403 is an Al x Ga 1-x N layer (0.3 ≦ x ≦ 0.8). That is, the Al composition of the AlGaN layer 403 is 30% or more and 80% or less. The GaN layer 404 has a layer thickness of 100 nm or more.

上記構成の窒化物半導体積層基板４１１によれば、その窒化物半導体積層基板４１１全体の反りを抑えることができて、窒化物半導体層、つまり、ＡｌＮ層１０２，ＡｌＧａＮ層４０３，ＧａＮ層４０４に与える歪応力を低減して、転位およびピットの発生を抑制することができる。   According to the nitride semiconductor multilayer substrate 411 having the above configuration, warpage of the entire nitride semiconductor multilayer substrate 411 can be suppressed, and is given to the nitride semiconductor layer, that is, the AlN layer 102, the AlGaN layer 403, and the GaN layer 404. Distortion stress can be reduced and the occurrence of dislocations and pits can be suppressed.

（第５実施形態）（ＡｌＮ層／Ｓｉ基板 Ｓｉ基板を凹凸加工）
この第５実施形態の窒化物半導体積層基板は、図示しないが、図１の第１実施形態の窒化物半導体積層基板１１１とは、Ｓｉ基板の表面を除いて同じ構成を有する。したがって、第１実施形態の構成要素と同じ構成要素については、第１実施形態の図１を援用する。 (Fifth Embodiment) (AlN layer / Si substrate Si substrate is processed unevenly)
Although not shown, the nitride semiconductor multilayer substrate of the fifth embodiment has the same configuration as the nitride semiconductor multilayer substrate 111 of the first embodiment of FIG. 1 except for the surface of the Si substrate. Therefore, about the same component as the component of 1st Embodiment, FIG. 1 of 1st Embodiment is used.

この第５実施形態の窒化物半導体積層基板のＳｉ基板は、（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面が上記Ｓｉ基板の表面の３０％以上となるように、上記Ｓｉ基板の表面に凹凸を有する。   The Si substrate of the nitride semiconductor multilayer substrate of the fifth embodiment has a surface inclined from the (111) plane in the (011) direction at an off angle of 0.11 degrees or more and 0.50 degrees or less of the Si substrate. The surface of the Si substrate has irregularities so as to be 30% or more of the surface.

こうした場合でも、第１実施形態で検証した結果と略同じ結果が得られた。また、この第５実施形態のＳｉ基板に、第２および第３実施形態と同じ窒化物半導体層を積層しても、第２および第３実施形態と略同じ効果が得られた。   Even in such a case, substantially the same result as the result verified in the first embodiment was obtained. Even when the same nitride semiconductor layer as in the second and third embodiments was stacked on the Si substrate of the fifth embodiment, substantially the same effect as in the second and third embodiments was obtained.

この第５実施形態の窒化物半導体積層基板によれば、上記Ｓｉ基板の表面の３０％以上の領域で、成長表面のテラス幅が短くなって、ＡｌＮとＳｉの格子定数差から生じる歪を緩和しやすくでき、貫通転位の発生を少なくでき、ひいては貫通転位から生じるピットを抑制することができる。したがって、この窒化物半導体積層基板を用いて、窒化物半導体装置を作れば、リーク電流の減少等ができて、電気的特性を改善できる。   According to the nitride semiconductor multilayer substrate of the fifth embodiment, the terrace width of the growth surface is shortened in a region of 30% or more of the surface of the Si substrate, and the strain caused by the difference in lattice constant between AlN and Si is alleviated. Therefore, the occurrence of threading dislocations can be reduced, and as a result, pits generated from threading dislocations can be suppressed. Therefore, if a nitride semiconductor device is made using this nitride semiconductor multilayer substrate, the leakage current can be reduced and the electrical characteristics can be improved.

（第６実施形態）（窒化物半導体装置）
図８は、この発明の窒化物半導体装置の一例としての第６実施形態のヘテロ接合電界効果トランジスタ（ＨＦＥＴ）の要部を示す断面図である。図８において、Ｓｉ基板１０１、ＡｌＮ層１０２、ＡｌＧａＮ層１０３および窒化物半導体積層基板１１１は、図１に示す第１実施形態のＳｉ基板１０１、ＡｌＮ層１０２、ＡｌＧａＮ層１０３および窒化物半導体積層基板１１１と全く同じ構成を有するので、第１実施形態と同じ参照番号を付して、その詳しい説明は省略する。 Sixth Embodiment (Nitride Semiconductor Device)
FIG. 8 is a cross-sectional view showing a main part of a heterojunction field effect transistor (HFET) of a sixth embodiment as an example of the nitride semiconductor device of the present invention. In FIG. 8, the Si substrate 101, the AlN layer 102, the AlGaN layer 103, and the nitride semiconductor multilayer substrate 111 are the Si substrate 101, the AlN layer 102, the AlGaN layer 103, and the nitride semiconductor multilayer substrate of the first embodiment shown in FIG. Since it has exactly the same configuration as 111, the same reference numerals as those in the first embodiment are assigned, and detailed description thereof is omitted.

図８に示すように、この第６実施形態のＨＦＥＴは、上記ＡｌＧａＮ層１０３上に、アンドープＧａＮ層２、アンドープＡｌＧａＮ層３をエピタキシャル成長により形成している。このアンドープＧａＮ層２とアンドープＡｌＧａＮ層３とがヘテロ接合を有するＧａＮ系積層体５を構成している。上記アンドープＧａＮ層２とアンドープＡｌＧａＮ層３との界面に２ＤＥＧ(２次元電子ガス)６が発生する。   As shown in FIG. 8, in the HFET of the sixth embodiment, an undoped GaN layer 2 and an undoped AlGaN layer 3 are formed on the AlGaN layer 103 by epitaxial growth. The undoped GaN layer 2 and the undoped AlGaN layer 3 constitute a GaN-based laminate 5 having a heterojunction. 2DEG (two-dimensional electron gas) 6 is generated at the interface between the undoped GaN layer 2 and the undoped AlGaN layer 3.

また、上記ＧａＮ系積層体５には、アンドープＧａＮ層２に達するリセスを形成し、このリセスにドレイン電極１１とソース電極１２とをオーミック電極として形成している。このドレイン電極１１とソース電極１２は、例えば、一例として、Ｔｉ層、Ａｌ層、ＴｉＮ層が順に積層されたＴｉ/Ａｌ/ＴｉＮ電極である。また、上記アンドープＡｌＧａＮ層３上に、ゲート電極１３を形成している。このゲート電極１３は、例えば、アンドープＡｌＧａＮ層３とショットキー接合するショットキー電極であり、例えば、ＴｉＮで作製している。尤も、ゲート電極は、絶縁膜上に形成して、絶縁ゲート電極構造としてもよい。   Further, a recess reaching the undoped GaN layer 2 is formed in the GaN-based stacked body 5, and a drain electrode 11 and a source electrode 12 are formed as ohmic electrodes in the recess. For example, the drain electrode 11 and the source electrode 12 are Ti / Al / TiN electrodes in which a Ti layer, an Al layer, and a TiN layer are sequentially stacked. A gate electrode 13 is formed on the undoped AlGaN layer 3. The gate electrode 13 is, for example, a Schottky electrode that forms a Schottky junction with the undoped AlGaN layer 3 and is made of, for example, TiN. However, the gate electrode may be formed on an insulating film to have an insulated gate electrode structure.

上記アンドープＡｌＧａＮ層３、ドレイン電極１１、ソース電極１２およびゲート電極１３上に、図示しない層間絶縁膜を形成し、この層間絶縁膜上に図示しないドレイン電極パッド、ソース電極パッドおよびゲート電極パッドを設けている。そして、上記ドレイン電極１１、ソース電極１２およびゲート電極１３を、夫々、図示しないビアホールを介して、ドレイン電極パッド、ソース電極パッドおよびゲート電極パッドに電気接続している。   An interlayer insulating film (not shown) is formed on the undoped AlGaN layer 3, the drain electrode 11, the source electrode 12, and the gate electrode 13, and a drain electrode pad, a source electrode pad, and a gate electrode pad (not shown) are provided on the interlayer insulating film. ing. The drain electrode 11, the source electrode 12, and the gate electrode 13 are electrically connected to the drain electrode pad, the source electrode pad, and the gate electrode pad through via holes (not shown), respectively.

この第６実施形態のＨＦＥＴは、第１実施形態の窒化物半導体積層基板１１１を有するので、貫通転位に起因するピットの発生を抑制することができ、したがって、リーク電流等を低減できる。   Since the HFET of the sixth embodiment has the nitride semiconductor multilayer substrate 111 of the first embodiment, generation of pits due to threading dislocations can be suppressed, and therefore leakage current and the like can be reduced.

なお、第１実施形態の窒化物半導体積層基板１１１に代えて、第２〜第５実施形態の窒化物半導体積層基板２１１，３１１，４１１を用いても、同様の効果が得られる。   The same effect can be obtained by using the nitride semiconductor multilayer substrates 211, 311 and 411 of the second to fifth embodiments instead of the nitride semiconductor multilayer substrate 111 of the first embodiment.

この第６実施形態では、ＧａＮ系積層体５は、アンドープＧａＮ層２とアンドープＡｌＧａＮ層３を積層して構成していたが、ＧａＮ系積層体は、ＡlＸＩｎＹＧａ１−Ｘ−ＹＮ(Ｘ≧０、Ｙ≧０、０≦Ｘ＋Ｙ＜１)で表されるＧａＮ系半導体層を積層したものであればよい。例えば、ＧａＮ系積層体は、ＡｌＧａＮ、ＧａＮ、ＩｎＧａＮ等を含むものであってもよい。 In the sixth embodiment, the GaN-based stacked body 5 is configured by stacking the undoped GaN layer 2 and the undoped AlGaN layer 3, but the GaN-based stacked body is made of Al X In Y Ga 1-XY N. What is necessary is just to laminate | stack the GaN-type semiconductor layer represented by ( X> = 0, Y> = 0, 0 <= X + Y <1 ). For example, the GaN-based laminate may include AlGaN, GaN, InGaN, or the like.

また、この第６実施形態では、ＡｌＧａＮ層３に、アンドープＧａＮ層２に達するリセスを形成し、このリセスにドレイン電極１１とソース電極１２をオーミック電極として形成したが、上記リセスを形成しないで、上記アンドープＧａＮ層上のアンドープＡlＧａＮ層上にドレイン電極とソース電極を形成し、アンドープＡｌＧａＮ層の層厚を薄くすることによってドレイン電極とソース電極がオーミック電極になるようにしてもよい。   In the sixth embodiment, a recess reaching the undoped GaN layer 2 is formed in the AlGaN layer 3, and the drain electrode 11 and the source electrode 12 are formed as ohmic electrodes in the recess. However, without forming the recess, A drain electrode and a source electrode may be formed on the undoped AlGaN layer on the undoped GaN layer, and the drain electrode and the source electrode may be ohmic electrodes by reducing the thickness of the undoped AlGaN layer.

この第６実施形態では、窒化物半導体装置の一例として、ＨＦＥＴについて説明したが、この発明の窒化物半導体装置は、第１〜第５実施形態等の窒化物半導体積層基板１１１，２１１，３１１，４１１等を用いるものであればどのようなものであってもよく、例えば、ＨＥＭＴ（高電子移動度トランジスタ：High Electron Mobility Transistor）、ＭＩＳＦＥＴ（金属−絶縁体−半導体 電界効果トランジスタ：Metal Insulator Semiconductor Field Effect Transistor）、接合型ＦＥＴ、ＬＥＤ（発光ダイオード）、半導体レーザ等であってもよい。   In the sixth embodiment, the HFET has been described as an example of the nitride semiconductor device. However, the nitride semiconductor device of the present invention includes the nitride semiconductor multilayer substrates 111, 211, 311 of the first to fifth embodiments. For example, HEMT (High Electron Mobility Transistor), MISFET (Metal-Insulator-Semiconductor Field Effect Transistor: Metal Insulator Semiconductor Field) It may be an effect transistor, a junction FET, an LED (light emitting diode), a semiconductor laser, or the like.

また、窒化物半導体装置の種類に応じて、電極は、ドレイン電極、ソース電極、ゲート電極、エミッタ電極、コレクタ電極、ベース電極、アノード電極、カソード電極等となることは勿論である。   Of course, depending on the type of the nitride semiconductor device, the electrode may be a drain electrode, a source electrode, a gate electrode, an emitter electrode, a collector electrode, a base electrode, an anode electrode, a cathode electrode, or the like.

また、上記第１〜第６実施形態では、バリア層としてＡｌＮ層１０２，２０２，３０２を用いていたが、それに代えて、例えば、ｐ−ＧａＮ、ｐ−ＡｌＧａＮ等からなる層を用いることができる。また、バッファ層としてのＡｌＧａＮ層は、特許文献１のように、Ａｌ組成を層厚方向に変化させてもよい。   In the first to sixth embodiments, the AlN layers 102, 202, and 302 are used as the barrier layer. Instead, for example, a layer made of p-GaN, p-AlGaN, or the like can be used. . Further, the AlGaN layer as the buffer layer may change the Al composition in the layer thickness direction as in Patent Document 1.

この発明および実施形態を纏めると、次のようになる。   The present invention and the embodiment are summarized as follows.

この発明の窒化物半導体積層基板１１１，２１１、３１１，４１１は、
（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板１０１，２０１，３０１と、
このＳｉ基板１０１，２０１，３０１の上にエピタキシャル成長した少なくとも１つの窒化物半導体層１０２，１０３，２０２，２０３，３０２，３０３，４０３，４０４と
を備えることを特徴としている。 The nitride semiconductor multilayer substrates 111, 211, 311 and 411 of the present invention are:
Si substrates 101, 201, 301 having a main surface as a main surface inclined at an off angle of 0.11 degrees or more and 0.50 degrees or less in the (011) direction from the (111) plane;
It is characterized by comprising at least one nitride semiconductor layer 102, 103, 202, 203, 302, 303, 403, 404 epitaxially grown on the Si substrate 101, 201, 301.

上記構成の窒化物半導体積層基板によれば、Ｓｉ基板１０１，２０１，３０１が、（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角を有するので、エピタキシャル成長表面のテラス幅が短くなって、例えばＡｌＮとＳｉの格子定数差から生じる歪を緩和しやすくでき、貫通転位の発生を抑制でき、ひいては、貫通転位から生じるピットを抑制することができる。   According to the nitride semiconductor multilayer substrate having the above structure, the Si substrates 101, 201, 301 have an off angle of 0.11 ° or more and 0.50 ° or less in the (011) direction from the (111) plane. The terrace width on the surface of the epitaxial growth is shortened, and for example, the distortion caused by the difference in lattice constant between AlN and Si can be easily relaxed, the occurrence of threading dislocations can be suppressed, and hence the pits generated from threading dislocations can be suppressed.

このように、上記窒化物半導体積層基板１１１，２１１、３１１，４１１の表面のピット数が少ないので、この窒化物半導体積層基板１１１，２１１、３１１，４１１を用いた窒化物半導体装置のリーク電流等を低減できる。   As described above, since the number of pits on the surface of the nitride semiconductor multilayer substrates 111, 211, 311, 411 is small, the leakage current of the nitride semiconductor device using the nitride semiconductor multilayer substrates 111, 211, 311, 411, etc. Can be reduced.

１実施形態では、
上記Ｓｉ基板２０１上に、層厚が５０ｎｍ以上、４００ｎｍ以下のＡｌＮ層２０２を積層している。 In one embodiment,
An AlN layer 202 having a layer thickness of 50 nm or more and 400 nm or less is stacked on the Si substrate 201.

上記実施形態によれば、ＡｌＮ層２０３の層厚が５０ｎｍ以上、４００ｎｍ以下であるので、ＳｉとＧａとの反応を抑制して、例えば、ＡｌＧａＮ層２０３の表面において、直径１０ｎｍ以上、５０ｎｍ以下のサイズのピットの数を著しく減少することができる。   According to the embodiment, since the layer thickness of the AlN layer 203 is 50 nm or more and 400 nm or less, the reaction between Si and Ga is suppressed, for example, on the surface of the AlGaN layer 203, the diameter is 10 nm or more and 50 nm or less. The number of size pits can be significantly reduced.

１実施形態では、
上記ＡｌＮ層３０２は、（０００２）面のＸ線回折におけるロッキングカーブの半値幅が２５００arcsec以下である。 In one embodiment,
In the AlN layer 302, the half-value width of the rocking curve in the (0002) plane X-ray diffraction is 2500 arcsec or less.

上記実施形態によれば、上記ＡｌＮ層３０２の（０００２）面のＸ線回折におけるロッキングカーブの半値幅が２５００arcsec以下であるので、貫通転位の発生、ひいてはピットの発生を抑制することが可能となる。   According to the above embodiment, since the half-value width of the rocking curve in the X-ray diffraction of the (0002) plane of the AlN layer 302 is 2500 arcsec or less, it is possible to suppress the occurrence of threading dislocations and hence the generation of pits. .

１実施形態の窒化物半導体積層基板４１１は、
上記ＡｌＮ層１０２上に、ＡｌｘＧａ1−xＮ層４０３（０.３≦ｘ≦０．８）を積層し、
このＡｌｘＧａ1−xＮ層４０３の上に、１００ｎｍ以上の厚さのＧａＮ層４０４を積層している。 In one embodiment, the nitride semiconductor multilayer substrate 411 includes:
An Al x Ga 1-x N layer 403 (0.3 ≦ x ≦ 0.8) is laminated on the AlN layer 102,
On this Al x Ga 1-x N layer 403, a GaN layer 404 having a thickness of 100 nm or more is laminated.

上記実施形態によれば、窒化物半導体積層基板４１１全体の反りを抑えることができて、窒化物半導体層、つまり、ＡｌＮ層１０２，ＡｌＧａＮ層４０３，ＧａＮ層４０４に与える歪応力を低減して、転位およびピットの発生を抑制することができる。   According to the above embodiment, warpage of the entire nitride semiconductor multilayer substrate 411 can be suppressed, strain stress applied to the nitride semiconductor layer, that is, the AlN layer 102, the AlGaN layer 403, and the GaN layer 404 can be reduced, Generation of dislocations and pits can be suppressed.

１実施形態では、
（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した上記面が上記Ｓｉ基板の表面の３０％以上となるように、上記Ｓｉ基板の表面が凹凸を有する。 In one embodiment,
The surface of the Si substrate so that the surface inclined at an off angle of 0.11 degree or more and 0.50 degree or less from the (111) plane to the (011) direction is 30% or more of the surface of the Si substrate. Have irregularities.

上記実施形態によれば、上記Ｓｉ基板の表面の３０％以上の領域で、成長表面のテラス幅が短くなって、ＡｌＮとＳｉの格子定数差から生じる歪を緩和しやすくでき、貫通転位の発生を少なくでき、ひいては貫通転位から生じるピットを抑制することができる。したがって、リーク電流の減少等ができる。   According to the above embodiment, the terrace width of the growth surface is shortened in a region of 30% or more of the surface of the Si substrate, the strain caused by the difference in lattice constant between AlN and Si can be easily relaxed, and the occurrence of threading dislocations. As a result, pits resulting from threading dislocations can be suppressed. Therefore, the leakage current can be reduced.

この発明の窒化物半導体装置は、
上述の窒化物半導体積層基板１１１と、
上記窒化物半導体積層基板１１１上に積層された窒化物半導体層２，３と、
上記窒化物半導体層２、３上に設けた電極１１，１２，１３と
を備えることを特徴としている。 The nitride semiconductor device of the present invention is
The aforementioned nitride semiconductor multilayer substrate 111;
Nitride semiconductor layers 2 and 3 stacked on the nitride semiconductor multilayer substrate 111;
Electrodes 11, 12, and 13 provided on the nitride semiconductor layers 2 and 3 are provided.

この発明の窒化物半導体装置によれば、貫通転位に起因するピットの発生を抑制して、リーク電流を少なくすることができる。   According to the nitride semiconductor device of the present invention, the generation of pits due to threading dislocations can be suppressed and the leakage current can be reduced.

この発明の窒化物半導体積層基板の製造方法は、
（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板１０１，２０１，３０１を準備する工程と、
上記Ｓｉ基板１０１，２０１，３０１の主面の上に、少なくとも１つの窒化物半導体層１０２，２０２，３０２，１０３，２０３，３０３，４０３，４０４をエピタキシャル成長する工程と
を備えることを特徴としている。 The manufacturing method of the nitride semiconductor multilayer substrate of the present invention is as follows.
A step of preparing Si substrates 101, 201, 301 having a main surface as a main surface inclined at an off angle of 0.11 degrees or more and 0.50 degrees or less in the (011) direction from the (111) plane;
And a step of epitaxially growing at least one nitride semiconductor layer 102, 202, 302, 103, 203, 303, 403, 404 on the main surface of the Si substrate 101, 201, 301.

この発明の窒化物半導体積層基板の製造方法によれば、貫通転位に起因するピットを低減できて、リーク電流等の少ない電気的特性が改善された窒化物半導体積層基板を得ることができる。   According to the method for manufacturing a nitride semiconductor multilayer substrate of the present invention, it is possible to obtain a nitride semiconductor multilayer substrate in which pits due to threading dislocations can be reduced and electrical characteristics such as leakage current are improved.

上記第１〜第６実施形態および変形例で述べた構成要素は、適宜、組み合わせてもよく、また、適宜、選択、置換、あるいは、削除してもよいのは、勿論である。   Of course, the constituent elements described in the first to sixth embodiments and the modification examples may be combined as appropriate, and may be appropriately selected, replaced, or deleted.

２，４０４ ＧａＮ層
３，１０３，２０３，３０３，４０３ ＡｌＧａＮ層
１０１，２０１，３０１ Ｓｉ基板
１０２，２０２，３０２ ＡｌＮ層
１１ ドレイン電極
１２ ソース電極
１３ ゲート電極
１１１，２１１、３１１，４１１ 窒化物半導体積層基板 2,404 GaN layer 3,103,203,303,403 AlGaN layer 101,201,301 Si substrate 102,202,302 AlN layer 11 Drain electrode 12 Source electrode 13 Gate electrode 1111, 211, 311, 411 Nitride semiconductor stack substrate

Claims (5)

（１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板と、
このＳｉ基板の上にエピタキシャル成長した少なくとも１つの窒化物半導体層と
を備えることを特徴とする窒化物半導体積層基板。 A Si substrate having a main surface that is inclined at an off angle of 0.11 degrees or more and 0.50 degrees or less in the (011) direction from the (111) plane;
A nitride semiconductor multilayer substrate comprising: at least one nitride semiconductor layer epitaxially grown on the Si substrate. 請求項１に記載の窒化物半導体積層基板において、
上記Ｓｉ基板上に、層厚が５０ｎｍ以上、４００ｎｍ以下のＡｌＮ層を積層したことを特徴とする窒化物半導体積層基板。 The nitride semiconductor multilayer substrate according to claim 1,
A nitride semiconductor multilayer substrate, wherein an AlN layer having a thickness of 50 nm or more and 400 nm or less is laminated on the Si substrate. 請求項２に記載の窒化物半導体積層基板において、
上記ＡｌＮ層は、（０００２）面のＸ線回折におけるロッキングカーブの半値幅が２５００arcsec以下であることを特徴とする窒化物半導体積層基板。 The nitride semiconductor multilayer substrate according to claim 2,
A nitride semiconductor multilayer substrate, wherein the AlN layer has a rocking curve half-value width of 2500 arcsec or less in X-ray diffraction of a (0002) plane. 請求項１から３の何れか１つに記載の窒化物半導体積層基板と、
上記窒化物半導体積層基板上に積層された窒化物半導体層と、
上記窒化物半導体層上に設けた電極と
を備えることを特徴とする窒化物半導体装置。 The nitride semiconductor multilayer substrate according to any one of claims 1 to 3,
A nitride semiconductor layer stacked on the nitride semiconductor multilayer substrate;
A nitride semiconductor device comprising: an electrode provided on the nitride semiconductor layer. （１１１）面から（０１１）方向に、０．１１度以上、０．５０度以下のオフ角で傾斜した面を主面とするＳｉ基板を準備する工程と、
上記Ｓｉ基板の主面の上に、少なくとも１つの窒化物半導体層をエピタキシャル成長する工程と
を備えることを特徴とする窒化物半導体積層基板の製造方法。 Preparing a Si substrate whose main surface is a plane inclined at an off angle of 0.11 degree or more and 0.50 degree or less in the (011) direction from the (111) plane;
And a step of epitaxially growing at least one nitride semiconductor layer on the main surface of the Si substrate.
JP2013146715A 2013-07-12 2013-07-12 Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate Pending JP2016167473A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013146715A JP2016167473A (en) 2013-07-12 2013-07-12 Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate
PCT/JP2014/066197 WO2015005083A1 (en) 2013-07-12 2014-06-18 Nitride semiconductor multilayer substrate, nitride semiconductor device, and method for manufacturing nitride semiconductor multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013146715A JP2016167473A (en) 2013-07-12 2013-07-12 Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate

Publications (1)

Publication Number Publication Date
JP2016167473A true JP2016167473A (en) 2016-09-15

Family

ID=52279769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013146715A Pending JP2016167473A (en) 2013-07-12 2013-07-12 Nitride semiconductor lamination substrate, nitride semiconductor device, and method of manufacturing nitride semiconductor lamination substrate

Country Status (2)

Country Link
JP (1) JP2016167473A (en)
WO (1) WO2015005083A1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015304A (en) * 2010-06-30 2012-01-19 Sumitomo Electric Ind Ltd Semiconductor device

Also Published As

Publication number Publication date
WO2015005083A1 (en) 2015-01-15

Similar Documents

Publication Publication Date Title
JP5634681B2 (en) Semiconductor element
JP4530171B2 (en) Semiconductor device
CN108807507B (en) P-type doping of group III nitride buffer layer structures on heterogeneous substrates
JP4908886B2 (en) Semiconductor device
JP6035721B2 (en) Manufacturing method of semiconductor device
JP5782033B2 (en) Epitaxial substrate for semiconductor element, semiconductor element, PN junction diode element, and method for manufacturing epitaxial substrate for semiconductor element
CN103828030B (en) The manufacture method of semiconductor element, HEMT elements and semiconductor element
JP2005158889A (en) Plate-shaped substrate for forming semiconductor element, its manufacturing method, and semiconductor element using it
WO2012026396A1 (en) Epitaxial substrate for semiconductor element, semiconductor element, method for fabricating epitaxial substrate for semiconductor element, and method for fabricating semiconductor element
US8405067B2 (en) Nitride semiconductor element
JP2012015304A (en) Semiconductor device
JP2016058693A (en) Semiconductor device, semiconductor wafer, and method of manufacturing semiconductor device
WO2013168371A1 (en) Epitaxial substrate, semiconductor device, and semiconductor device manufacturing method
JP6244769B2 (en) Semiconductor device and manufacturing method of semiconductor device
US10332975B2 (en) Epitaxial substrate for semiconductor device and method for manufacturing same
US20120168771A1 (en) Semiconductor element, hemt element, and method of manufacturing semiconductor element
JP6089122B2 (en) Nitride semiconductor laminate, method for manufacturing the same, and nitride semiconductor device
KR20150000753A (en) Nitride semiconductor and method thereof
JP2006032524A (en) Nitride semiconductor heterostructure field-effect transistor and its manufacturing method
JP5806545B2 (en) Semiconductor device, HEMT device, and method for manufacturing semiconductor device
JP5776344B2 (en) Semiconductor device
JP2008186952A (en) Semiconductor substrate and semiconductor device
WO2015005083A1 (en) Nitride semiconductor multilayer substrate, nitride semiconductor device, and method for manufacturing nitride semiconductor multilayer substrate
JP6205497B2 (en) Manufacturing method of nitride semiconductor
JP7422271B1 (en) Semiconductor device and semiconductor device manufacturing method