JP2015144168A - semiconductor device - Google Patents

semiconductor device Download PDF

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JP2015144168A
JP2015144168A JP2014016568A JP2014016568A JP2015144168A JP 2015144168 A JP2015144168 A JP 2015144168A JP 2014016568 A JP2014016568 A JP 2014016568A JP 2014016568 A JP2014016568 A JP 2014016568A JP 2015144168 A JP2015144168 A JP 2015144168A
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electrode pad
layer
semiconductor device
bonding
wiring layer
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JP6066941B2 (en
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祥久 内田
Yoshihisa Uchida
祥久 内田
菊池　正雄
Masao Kikuchi
正雄 菊池
進吾 須藤
Shingo Sudo
進吾 須藤
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To inhibit breaking of a lower layer structure of an electrode pad and separation of a junction part while ensuring workability and reliability of wiring in a semiconductor device.SOLUTION: In a semiconductor device, a barrier metal layer 2a, a wiring layer 1, an electrode pad layer 4 and a passivation film 3 are formed on a base material 10. The wiring layer 1 is formed on an interlayer insulation film 8. The wiring layer 1 is sandwiched by the barrier metal layer 2a and the passivation film 3. The electrode pad layer 4 is exposed from openings of the passivation film 3 which covers a circumference of the electrode pad layer 4. The electrode pad layer 4 which is higher in Cu than the wiring layer 1.

Description

本発明は、半導体装置に関し、特に、半導体チップに形成されている電極パッドの構成に特徴のある半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device characterized by the configuration of electrode pads formed on a semiconductor chip.

外部電極を備えた半導体装置では、半導体チップは基板やリードフレームに載置されている。半導体装置の製造工程において、半導体チップの上に形成された電極パッドを外部電極と電気的に接続する方法として、超音波圧着あるいは超音波併用熱圧着により金属ワイヤを接合させるワイヤボンディング法が用いられる。ワイヤボンディング法は、超音波圧着によるウェッジボンディング法と超音波併用熱圧着によるボールボンディング法に大きく分類されている。   In a semiconductor device having an external electrode, a semiconductor chip is placed on a substrate or a lead frame. In a manufacturing process of a semiconductor device, a wire bonding method in which a metal wire is bonded by ultrasonic pressure bonding or ultrasonic heat combined pressure bonding is used as a method of electrically connecting an electrode pad formed on a semiconductor chip to an external electrode. . The wire bonding method is roughly classified into a wedge bonding method using ultrasonic bonding and a ball bonding method using thermocompression bonding with ultrasonic waves.

ウェッジボンディング法では、楔型のツールを使用する。ツールの先端に形成された溝に金属ワイヤを把持し、このツールを被接合部に押圧する。その状態で、ワイヤボンディング装置から発振される超音波振動をツールを介して金属ワイヤに印加すると、接合面の酸化膜や不純物が除去される。同時に、摩擦により生じる熱によって金属ワイヤは塑性変形し、金属ワイヤと被接合部との固相接合が進展する。   In the wedge bonding method, a wedge-shaped tool is used. A metal wire is held in a groove formed at the tip of the tool, and this tool is pressed against the joined portion. In this state, when an ultrasonic vibration oscillated from the wire bonding apparatus is applied to the metal wire through the tool, the oxide film and impurities on the bonding surface are removed. At the same time, the metal wire is plastically deformed by the heat generated by the friction, and solid-phase bonding between the metal wire and the bonded portion progresses.

ボールボンディング法では、金属ワイヤをキャピラリと呼ばれる筒状のツールから突出させて使用する。金属ワイヤ先端部とトーチロッドの間に高電圧を印加すると、空中放電が起こり、放電に伴う熱エネルギで金属ワイヤの先端がボール状に溶融する。この溶融形成したボールを加熱された被接合部に押付けながら超音波振動を印加すると、ウェッジボンディング法と同様に固相接合が得られる。   In the ball bonding method, a metal wire is used by protruding from a cylindrical tool called a capillary. When a high voltage is applied between the tip of the metal wire and the torch rod, air discharge occurs, and the tip of the metal wire is melted into a ball shape by the heat energy accompanying the discharge. When ultrasonic vibration is applied while pressing the melted ball against the heated bonded portion, solid phase bonding can be obtained in the same manner as the wedge bonding method.

この種のワイヤボンディングでは、金属ワイヤの材料として、Ａｌ（特にウェッジボンディング法の場合）またはＡｕ（特にボールボンディング法の場合）が、一般的に用いられてきた。一方で、半導体装置の信頼性向上や、実装工程に掛かる材料費低減の観点から、Ｃｕを主な材料とするＣｕ系ボンディングワイヤへの切り替えが行われつつある。特に、ボールボンディングの分野においては、２００９年頃からのＡｕ価格の高騰をきっかけに、Ｃｕ系ボンディングワイヤの使用量が伸びた。２０１２年の一年間に使用された金属ワイヤは半分以上がＣｕ系ボンディングワイヤであったとまで言われている。   In this type of wire bonding, Al (especially in the case of the wedge bonding method) or Au (especially in the case of the ball bonding method) has been generally used as the metal wire material. On the other hand, switching to Cu-based bonding wires containing Cu as a main material is being performed from the viewpoint of improving the reliability of semiconductor devices and reducing material costs in the mounting process. In particular, in the field of ball bonding, the usage amount of Cu-based bonding wires has increased due to the rise in the price of Au since around 2009. It is said that more than half of the metal wires used in 2012 were Cu-based bonding wires.

半導体チップに形成される電極パッド材としては、Ａｌが一般的である。Ａｌは、Ｃｕよりも軟らかく、超音波印加中に選択的に変形するため、電極パッド材に過剰に荷重や超音波を印加した場合には、金属ワイヤの外周部に多くのＡｌが排斥される。ＣｕはＡｌやＡｕと比較して硬く、変形しにくいため、健全な接合部を得るには、接合時に、より大きな荷重や超音波出力が必要となる。金属ワイヤが電極パッドの下層構造に直接接触すると、電極パッドの下層構造にクラック等のダメージが生じたり、接合部が電極パッドごと剥離する。   Al is generally used as the electrode pad material formed on the semiconductor chip. Since Al is softer than Cu and selectively deforms during application of ultrasonic waves, when an excessive load or ultrasonic wave is applied to the electrode pad material, a large amount of Al is eliminated from the outer periphery of the metal wire. . Since Cu is harder than Al and Au and hard to be deformed, a larger load and ultrasonic output are required at the time of joining in order to obtain a sound joint. When the metal wire is in direct contact with the lower layer structure of the electrode pad, damage such as a crack occurs in the lower layer structure of the electrode pad, or the joint part peels off together with the electrode pad.

ワイヤボンディング時における電極パッドのダメージを抑制し、接合部の剥離を防止する技術の開発が進んでいる。チップ内配線層の一部を開口して電極パッドとして用いる半導体チップでは、配線材として一般的に用いられているＡｌに高濃度のＣｕを添加することで電極パッドの硬度を増大させている（例えば特許文献１）。高濃度のＣｕは、電極パッドの変形を抑制し、電極パッドの下層構造の破壊や接合部の剥離を抑制する効果を生み出す。   Development of a technique for suppressing damage to the electrode pad during wire bonding and preventing separation of the joint portion is in progress. In a semiconductor chip used as an electrode pad by opening a part of the in-chip wiring layer, the hardness of the electrode pad is increased by adding high-concentration Cu to Al generally used as a wiring material ( For example, Patent Document 1). A high concentration of Cu suppresses the deformation of the electrode pad, and produces an effect of suppressing the destruction of the underlying structure of the electrode pad and the peeling of the joint.

半導体チップの配線層の材料として２〜１２％のＣｕが含まれているＡｌを用いると、Ａｌ中に析出したＣｕが原因で配線層が腐食しやすくなり、加工性も悪くなる。すなわち、Ａｌ系配線層における信頼性の向上とワイヤボンディング時の電極パッドへのダメージの抑制は両立しにくい。   When Al containing 2 to 12% Cu is used as the material of the wiring layer of the semiconductor chip, the wiring layer is easily corroded due to Cu deposited in Al, and the workability is also deteriorated. That is, it is difficult to achieve both improvement in reliability in the Al-based wiring layer and suppression of damage to the electrode pad during wire bonding.

特開平1-187832号公報Japanese Unexamined Patent Publication No. 1-187832

本発明は、ワイヤボンディング工程でＣｕ系のボンディングワイヤを用いる場合に生じる上記のような課題を解決するためになされたものである。半導体装置（および半導体チップ）におけるチップ内配線の加工性と信頼性を確保したまま、電極パッドの下層構造の破壊や、接合部の剥離を抑制することを目的とするものである。   The present invention has been made to solve the above-described problems that occur when a Cu-based bonding wire is used in a wire bonding process. An object of the present invention is to suppress destruction of the lower layer structure of the electrode pad and separation of the joint portion while ensuring the workability and reliability of the in-chip wiring in the semiconductor device (and semiconductor chip).

本発明に係わる半導体装置は、外部機器に接続される外部電極と、層間絶縁膜の上に第１バリアメタル層とＡｌ系配線層とＡｌ系電極パッド層がこの順番で形成されてなる半導体チップと、Ａｌ系電極パッド層と外部電極を接続するボンディングワイヤと、外部電極と半導体チップとボンディングワイヤを封止する樹脂部材と、を備え、Ａｌ系電極パッド層は開口部を有するパッシベーション膜で周囲を被覆されていて、Ａｌ系電極パッド層はＡｌ系配線層よりも多くのＣｕを含んでいることを特徴とする。   A semiconductor device according to the present invention includes a semiconductor chip in which an external electrode connected to an external device, a first barrier metal layer, an Al-based wiring layer, and an Al-based electrode pad layer are formed in this order on an interlayer insulating film. A bonding wire that connects the Al-based electrode pad layer and the external electrode, and a resin member that seals the external electrode, the semiconductor chip, and the bonding wire, and the Al-based electrode pad layer is surrounded by a passivation film having an opening. The Al-based electrode pad layer contains more Cu than the Al-based wiring layer.

この発明の半導体装置（および半導体チップ）によれば、Ｃｕ系のボンディングワイヤを用いてワイヤボンディングを行っても、配線の加工性と信頼性を確保したまま、電極パッドの下層構造の破壊や、接合部の剥離を抑制できる。   According to the semiconductor device (and semiconductor chip) of the present invention, even when wire bonding is performed using a Cu-based bonding wire, destruction of the lower layer structure of the electrode pad, while maintaining the workability and reliability of the wiring, Separation of the joint can be suppressed.

本発明の実施の形態に係る半導体装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. 実施の形態１に係る半導体チップにおける単層配線構造を示す説明図である。4 is an explanatory diagram showing a single-layer wiring structure in the semiconductor chip according to the first embodiment. FIG. 実施の形態１に係る電極パッド層の構造を示す断面図である。3 is a cross-sectional view showing a structure of an electrode pad layer according to Embodiment 1. FIG. 実施の形態１に係る電極パッド層にＣｕ系のボンディングワイヤをボールボンディングした断面図である。FIG. 3 is a cross-sectional view in which a Cu-based bonding wire is ball bonded to the electrode pad layer according to the first embodiment. 比較例に係る電極パッド層の構造を示す断面図である。It is sectional drawing which shows the structure of the electrode pad layer which concerns on a comparative example. 比較例に係る電極パッド層にＣｕ系のボンディングワイヤをボールボンディングした断面図である。It is sectional drawing which carried out the ball bonding of the Cu-type bonding wire to the electrode pad layer which concerns on a comparative example. 実施の形態１に係る電極パッド層に荷重制御法を用いてＣｕ系のボンディングワイヤをボールボンディングした断面図である。FIG. 3 is a cross-sectional view in which a Cu-based bonding wire is ball bonded to the electrode pad layer according to the first embodiment using a load control method. 実施の形態２に係る電極パッド層の構造を示す説明図である。6 is an explanatory diagram showing a structure of an electrode pad layer according to Embodiment 2. FIG.

以下に本発明にかかる半導体装置の実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。図において、同一符号が付与されている構成要素は、同一の、または、相当する構成要素を表している。   Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the figure, the components given the same reference numerals represent the same or corresponding components.

実施の形態１．
図１に、Ｔ−ＰＭ（トランスファーパワーモールド）と呼ばれている半導体装置１００の全体構成を示す。半導体装置１００は、半導体チップ（トランジスタ１１Ａ、ダイオード１１Ｂおよび制御素子１１Ｃ）、ボンディングワイヤ７、外部電極１４、モールド樹脂部材１５、ヒートシンク１６、リードフレーム２４などから構成されている。半導体チップ１１、ボンディングワイヤ７、ヒートシンク１６、リードフレーム２４はモールド樹脂部材１５で封止されている。パッケージタイプの半導体装置１００は、ワイヤボンディングの終わったリードフレームを金型にセットして、熱硬化性のエポキシ樹脂を流し込んで成形されている。トランジスタ１１Ａには、MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor）、IGBT（Insulated Gate Bipolar Transistor）などが用いられる。半導体装置１００は外部電極１４を使って外部機器に接続される。 Embodiment 1 FIG.
FIG. 1 shows an overall configuration of a semiconductor device 100 called T-PM (transfer power mold). The semiconductor device 100 includes a semiconductor chip (a transistor 11A, a diode 11B, and a control element 11C), a bonding wire 7, an external electrode 14, a mold resin member 15, a heat sink 16, a lead frame 24, and the like. The semiconductor chip 11, the bonding wire 7, the heat sink 16, and the lead frame 24 are sealed with a mold resin member 15. The package type semiconductor device 100 is formed by setting a lead frame after wire bonding to a mold and pouring a thermosetting epoxy resin. As the transistor 11A, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like is used. The semiconductor device 100 is connected to an external device using the external electrode 14.

半導体チップ１１は、珪素（Ｓｉ）によって形成されたものの他、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成したものも好適に使用することができる。ワイドバンドギャップ半導体としては、炭化珪素（ＳｉＣ）、窒化ガリウム系材料またはダイヤモンドなどがある。ワイドバンドギャップ半導体を用いた場合、許容電流密度が高く、電力損失も低いため、電力用半導体チップを用いた装置の小型化が可能となる。   As the semiconductor chip 11, in addition to those formed of silicon (Si), those formed of a wide band gap semiconductor having a band gap larger than that of silicon can be suitably used. Examples of the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride material, and diamond. When a wide bandgap semiconductor is used, the allowable current density is high and the power loss is low, so that a device using the power semiconductor chip can be downsized.

図２は、半導体チップにおける単層配線構造を示している。半導体チップの基材（Ｓｉ）１０には層間絶縁膜（ＳｉＯ２）８が形成されている。配線層１は、０．５質量％のＣｕを含むＡｌから成る。配線層１の厚さは、０．５μｍとしている。配線層１の表面側には、Ｃｕを３質量％含むＡｌから成る、厚さ２μｍの電極パッド層４が形成されている。パッシベーション膜３は、電極パッド層４の表面の一部が１００μｍ角に取り除かれている。電極パッド層４の上に形成されている開口部が金属ワイヤとの接合領域なる。配線層１の下層側と上層側には、それぞれ、バリアメタル層２ａとバリアメタル層２ｂが成膜されている。電極パッド層４はビアにより直下の配線層１と接続されている。Ｃｕ系のボンディングワイヤ７は、一端が電極パッド層４に、他端は外部電極１４に接合される。 FIG. 2 shows a single-layer wiring structure in a semiconductor chip. An interlayer insulating film (SiO 2 ) 8 is formed on the substrate (Si) 10 of the semiconductor chip. The wiring layer 1 is made of Al containing 0.5% by mass of Cu. The thickness of the wiring layer 1 is 0.5 μm. On the surface side of the wiring layer 1, an electrode pad layer 4 having a thickness of 2 μm and made of Al containing 3% by mass of Cu is formed. In the passivation film 3, a part of the surface of the electrode pad layer 4 is removed to a 100 μm square. The opening formed on the electrode pad layer 4 is a bonding region with the metal wire. On the lower layer side and the upper layer side of the wiring layer 1, a barrier metal layer 2a and a barrier metal layer 2b are formed, respectively. The electrode pad layer 4 is connected to the wiring layer 1 immediately below by a via. One end of the Cu-based bonding wire 7 is bonded to the electrode pad layer 4 and the other end is bonded to the external electrode 14.

図３は、半導体チップにおける単層配線構造の詳細図である。基材１０の上にバリアメタル層２ａと配線層１と電極パッド層４とパッシベーション膜３が形成されている。配線層１は層間絶縁膜８の上に形成されている。配線層１はバリアメタル層２ａとパッシベーション膜３に挟持されている。電極パッド層４は周囲を覆うパッシベーション膜３の開口部２０から露呈している。電極パッド層４は配線層１よりも多くのＣｕを含んでいる。電極パッド層４はビア５により直下の配線層１と接続されている。配線層１の下層側には、厚さ５００ｎｍのＴｉＮから成るバリアメタル層２ａが成膜されている。配線層１と電極パッド層４との間には、厚さ５００ｎｍのＴｉＮから成るバリアメタル層２ｂが成膜されている。厚さ１μｍのポリイミドからなるパッシベーション膜３は、配線層１と電極パッド層４の一部を被っている。   FIG. 3 is a detailed view of a single-layer wiring structure in a semiconductor chip. A barrier metal layer 2 a, a wiring layer 1, an electrode pad layer 4, and a passivation film 3 are formed on the substrate 10. The wiring layer 1 is formed on the interlayer insulating film 8. The wiring layer 1 is sandwiched between the barrier metal layer 2 a and the passivation film 3. The electrode pad layer 4 is exposed from the opening 20 of the passivation film 3 covering the periphery. The electrode pad layer 4 contains more Cu than the wiring layer 1. The electrode pad layer 4 is connected to the wiring layer 1 immediately below by a via 5. On the lower layer side of the wiring layer 1, a barrier metal layer 2a made of TiN having a thickness of 500 nm is formed. A barrier metal layer 2 b made of TiN having a thickness of 500 nm is formed between the wiring layer 1 and the electrode pad layer 4. A passivation film 3 made of polyimide having a thickness of 1 μm covers the wiring layer 1 and part of the electrode pad layer 4.

半導体チップは、高速化や高集積化により配線パターンが細くなる傾向にある。配線パターンにはチップ内配線の微細化に伴い、エレクトロマイグレーションや腐食による断線が懸念されている。耐エレクトロマイグレーション性を向上させる手段として、配線層の主材料であるＡｌにＣｕを意図的に添加する方法が知られている。Ｃｕの混合比が高すぎると、加工性が悪くなったり、Ａｌ中に析出したＣｕが配線層のパターニングに用いる塩素系のエッチングガスと反応して腐食が生じやすくなるため、配線層のＡｌには０．５質量％のＣｕを一般的に添加する。   Semiconductor chips tend to have thinner wiring patterns due to higher speed and higher integration. With the miniaturization of the wiring in the chip, there is a concern about disconnection due to electromigration and corrosion. As a means for improving electromigration resistance, a method is known in which Cu is intentionally added to Al, which is the main material of the wiring layer. If the mixing ratio of Cu is too high, workability deteriorates or Cu precipitated in Al reacts with a chlorine-based etching gas used for patterning of the wiring layer, and corrosion easily occurs. Generally adds 0.5% by weight of Cu.

配線層の一部を開口させて電極パッドとして用いる構造では、ワイヤボンディング時のＡｌの変形を考慮すると、一定以上の厚みが必要となる。配線幅を細くして、高集積化を図る場合、配線のアスペクト比が大きくなり、配線倒れが生じやすい。この実施の形態による半導体チップは、配線層１がＣｕを０．５質量％含むＡｌから形成されているため、加工性と耐腐食性を低下させること無く、エレクトロマイグレーションを抑制でき、配線部の信頼性を確保することが可能となる。さらに、一部を電極パッドとして用いることなく、専用の配線層とするため、金属ワイヤとの接合性を考慮する必要がなく、配線層１は配線幅を細くしても配線倒れが生じない厚みにすることができる。   In a structure in which a part of the wiring layer is opened and used as an electrode pad, a certain thickness or more is required in consideration of Al deformation during wire bonding. When the wiring width is narrowed to achieve high integration, the aspect ratio of the wiring becomes large and the wiring collapse easily occurs. In the semiconductor chip according to this embodiment, since the wiring layer 1 is made of Al containing 0.5% by mass of Cu, electromigration can be suppressed without reducing workability and corrosion resistance. Reliability can be ensured. Furthermore, since a part of the wiring layer is a dedicated wiring layer without being used as an electrode pad, it is not necessary to consider the bonding property with a metal wire, and the wiring layer 1 has a thickness that does not cause a wiring collapse even if the wiring width is reduced. Can be.

電極パッド層４は、Ｃｕを３質量％含むＡｌからなる。電極パッド層４が硬くなり、接合時のＡｌ排斥が軽減される結果、電極パッドの下層構造の破壊や、接合部の剥離を防止することができる。電極パッド層４は、金属ワイヤとの接合にのみ用いる。チップ面内の配線として機能しないため、電極パッド層４の厚みを変化させても、配線層１の厚みは電極パッド層４の厚みに影響されることがない。   The electrode pad layer 4 is made of Al containing 3% by mass of Cu. As a result of the electrode pad layer 4 becoming hard and Al rejection during bonding being reduced, it is possible to prevent destruction of the lower layer structure of the electrode pad and peeling of the bonded portion. The electrode pad layer 4 is used only for bonding with a metal wire. Since it does not function as wiring in the chip surface, even if the thickness of the electrode pad layer 4 is changed, the thickness of the wiring layer 1 is not affected by the thickness of the electrode pad layer 4.

配線層１はアスペクトを理想的な状態で形成できるので、チップ内配線の微細化による高集積化を確保でき、信頼性も維持できる。さらに、配線層１は電極パッド層４の材料と同じＡｌ−Ｃｕ系にしている。配線層１と電極パッド層４を同一装置でスパッタ法により形成する場合であっても、スパッタ装置はチャンバーの内部が異元素により汚染されることがなく、異元素の混入による配線層１の信頼性の低下も防止できる。   Since the wiring layer 1 can be formed with an ideal aspect, it is possible to ensure high integration by miniaturizing the wiring in the chip and maintain reliability. Furthermore, the wiring layer 1 is made of the same Al—Cu system as the material of the electrode pad layer 4. Even when the wiring layer 1 and the electrode pad layer 4 are formed by sputtering with the same apparatus, the sputtering apparatus does not contaminate the inside of the chamber with different elements, and the reliability of the wiring layer 1 due to the mixing of different elements. It is possible to prevent a decrease in sex.

上記のように、半導体装置１００は本実施の形態の電極パッド層構造を有する半導体チップを用いている。配線層１をチップ内の配線専用層に、電極パッド層４をワイヤとの接合専用層に、というように電極パッド層構造を機能分離することで、配線部の信頼性と、ワイヤボンディング時のダメージ抑制を両立している。バリアメタル層２ａは、基材１０のＳｉが配線層１に拡散するのを防止する目的で形成されている。バリアメタル層２ｂは電極パッド層４のＣｕが配線層１に拡散するのを防止する目的で形成されている。これにより、ＳｉやＣｕの拡散により半導体チップの電気特性が過渡的に変化することを抑制できる。   As described above, the semiconductor device 100 uses the semiconductor chip having the electrode pad layer structure of the present embodiment. By separating the function of the electrode pad layer structure such that the wiring layer 1 is a dedicated layer for wiring in the chip and the electrode pad layer 4 is a dedicated layer for bonding to wires, the reliability of the wiring part and the wire bonding can be improved. Both damage control is achieved. The barrier metal layer 2 a is formed for the purpose of preventing Si of the base material 10 from diffusing into the wiring layer 1. The barrier metal layer 2 b is formed for the purpose of preventing Cu of the electrode pad layer 4 from diffusing into the wiring layer 1. Thereby, it can suppress that the electrical property of a semiconductor chip changes transiently by diffusion of Si or Cu.

パッシベーション膜３は、水分による配線層１の腐食を抑制するためのものである。通常、半導体チップを搭載するデバイス（半導体装置）は、エポキシ樹脂でパッケージされている。パッシベーション膜３は、半導体チップの表面まで到達する微量な水分による配線層１または電極パッド層４の腐食を防止する。なお、この実施の形態においては、配線層が一層の場合について述べたが、これに限るものではなく、電極パッド層の下層に、多層の配線層があってもよい。また、この実施の形態においては、チップ内の配線層が厚さ０．５μｍの場合について述べたが、これに限るものではなく、配線倒れが生じないアスペクト比で厚さと幅を設定すれば良い。   The passivation film 3 is for suppressing corrosion of the wiring layer 1 due to moisture. Usually, a device (semiconductor device) on which a semiconductor chip is mounted is packaged with an epoxy resin. The passivation film 3 prevents corrosion of the wiring layer 1 or the electrode pad layer 4 due to a small amount of moisture reaching the surface of the semiconductor chip. In this embodiment, the case where the number of wiring layers is one has been described. However, the present invention is not limited to this, and a multilayer wiring layer may be provided below the electrode pad layer. In this embodiment, the case where the wiring layer in the chip has a thickness of 0.5 μm has been described. However, the present invention is not limited to this, and the thickness and width may be set with an aspect ratio that does not cause wiring collapse. .

この実施の形態においては、厚さ５００ｎｍのＴｉＮからなるバリアメタル層について述べた。バリアメタル層はこれに限るものではなく、配線層への基材（Ｓｉ）および電極パッド層（Ｃｕ）の拡散を防止できる材料および厚さであれば良い。例えば、Ｔｉ、ＴｉＯ２、Ｔａ、ＴａＮ、これらの組合せなどでも良い。また、この実施の形態においては、厚さ１μｍのポリイミドからなるパッシベーション膜について述べた。パッシベーション膜はこれに限るものではなく、ＳｉＮ膜やリンシリケートガラス膜であっても良い。   In this embodiment, a barrier metal layer made of TiN having a thickness of 500 nm has been described. The barrier metal layer is not limited to this, and may be any material and thickness that can prevent the base material (Si) and the electrode pad layer (Cu) from diffusing into the wiring layer. For example, Ti, TiO2, Ta, TaN, or a combination thereof may be used. In this embodiment, a passivation film made of polyimide having a thickness of 1 μm has been described. The passivation film is not limited to this, and may be a SiN film or a phosphorus silicate glass film.

この実施の形態においては、電極パッド層４の上層側のパッシベーション膜３を１００μｍ角の大きさで取り除くことで、金属ワイヤとの接合領域を設ける場合について述べたが、これに限るものではない。接合領域はボンディング後の変形したワイヤより開口寸法が大きければ良い。例えば、ボールボンド法の場合は、使用するワイヤ径の２倍以上あれば良い。ウェッジボンド法の場合は、長手方向はウェッジツールの先端と同じ長さ以上、短手方向はワイヤ径の１．５倍以上あれば良い。   In this embodiment, the case where the bonding region with the metal wire is provided by removing the passivation film 3 on the upper layer side of the electrode pad layer 4 with a size of 100 μm square is described, but the present invention is not limited to this. The bonding area only needs to have a larger opening size than the deformed wire after bonding. For example, in the case of the ball bond method, it is sufficient that the wire diameter to be used is twice or more. In the case of the wedge bond method, the longitudinal direction may be equal to or longer than the tip of the wedge tool, and the short direction may be 1.5 times the wire diameter or more.

この実施の形態においては、配線層１と電極パッド層４はスパッタ方により成膜させる場合について述べた。成膜法はこれに限るものではなく、蒸着法、ＣＶＤ（Chemical Vapor Deposition）法などでもよい。配線層１と電極パッド層４との接続にはビア５を用いる場合について述べているが、これに限るものではない。導電性のバリアメタルを用いた場合はビアによる接続は必要なくなる。絶縁性のバリアメタルを用いた場合であっても、バリアメタルが薄ければトンネル効果で電気的な接続が得られる。   In this embodiment, the case where the wiring layer 1 and the electrode pad layer 4 are formed by sputtering is described. The film forming method is not limited to this, and an evaporation method, a CVD (Chemical Vapor Deposition) method, or the like may be used. Although the case where the via 5 is used for the connection between the wiring layer 1 and the electrode pad layer 4 is described, it is not limited to this. When a conductive barrier metal is used, connection by via is not necessary. Even when an insulating barrier metal is used, if the barrier metal is thin, electrical connection can be obtained by the tunnel effect.

この実施の形態においては、Ｃｕを３質量％含むＡｌから形成された電極パッド層について述べた。電極パッド層はこれに限るものではなく、Ａｌの硬度を増大させ、Ｃｕの析出物を形成できればよく、たとえば１〜５質量％のＣｕを添加すればよい。また、この実施の形態においては、厚さ２μｍの電極パッド層について述べたが、これに限るものではなく、電極パッドの下層構造の破壊や接合部の剥離を抑制できる厚さであれば良いことは言うまでもない。配線層１は０．５質量％のＣｕを含むＡｌから形成されたものについて述べているが、０質量％（純Ａｌ）〜０．７質量％の範囲であればよい。   In this embodiment, the electrode pad layer formed of Al containing 3% by mass of Cu has been described. The electrode pad layer is not limited to this, and it is sufficient if the hardness of Al can be increased and Cu precipitates can be formed. For example, 1 to 5% by mass of Cu may be added. In this embodiment, the electrode pad layer having a thickness of 2 μm has been described. However, the present invention is not limited to this, and any thickness that can suppress the destruction of the lower layer structure of the electrode pad and the peeling of the joint portion may be used. Needless to say. The wiring layer 1 is described as being formed from Al containing 0.5% by mass of Cu, but may be in the range of 0% by mass (pure Al) to 0.7% by mass.

この実施の形態においては、Ｓｉを基材とした半導体チップについて述べた。基材はこれに限るものではなく、ＳｉＣ、ＧａＮ、ＧａＡｓ、ＩｎＧａＡｓなどでもよい。特に、ＳｉＣ、ＧａＮなどの素材を材料とする、Ｓｉよりもバンドギャップが大きい、ワイドギャップ半導体を用いる場合、半導体装置はその利点を活かすためには高温で動作されることが多くなる。高温動作時の信頼性を保証するために、Ｃｕ系のボンディングワイヤの必要性が増している。   In this embodiment, the semiconductor chip based on Si has been described. The substrate is not limited to this, and may be SiC, GaN, GaAs, InGaAs, or the like. In particular, when a wide gap semiconductor using a material such as SiC or GaN having a band gap larger than that of Si is used, the semiconductor device is often operated at a high temperature in order to take advantage of the advantages. In order to ensure reliability during high temperature operation, the need for Cu-based bonding wires is increasing.

次に、図４を用いて、実施の形態１による電極パッド構造のダメージ抑制効果を説明する。同図はＣｕ系の金属ワイヤを用いてワイヤボンディングした電極パッド部の断面図である。配線層１はＣｕを０．５質量％含むＡｌからなる。電極パッド層４は配線層１よりも多くのＣｕを含む。電極パッド層４の一部はパッシベーション膜３の開口部から露出している。この露出部にＣｕ系のボンディングワイヤがＡｕワイヤで一般的な接合方法で接合されている。   Next, the damage suppression effect of the electrode pad structure according to the first embodiment will be described with reference to FIG. This figure is a cross-sectional view of an electrode pad portion wire-bonded using a Cu-based metal wire. The wiring layer 1 is made of Al containing 0.5% by mass of Cu. The electrode pad layer 4 contains more Cu than the wiring layer 1. A part of the electrode pad layer 4 is exposed from the opening of the passivation film 3. A Cu-based bonding wire is bonded to the exposed portion with an Au wire by a general bonding method.

Ａｕワイヤを用いるワイヤボンディングでは、一般的に超音波印加により初期ボールを塑性変形させながら接合を行う。超音波は初期ボールおよび接合部に形成され、接合を阻害する、酸化膜や有機皮膜を破壊し、新生面を露出させる。本実施の形態に係る電極パッド構造によれば、Ｃｕの添加量を増大させているため、電極パッド層４が固くなり、初期ボールを大きく変形させながら接合させる方法を用いても、超音波印加時の電極パッド層４の排斥が少ない。ワイヤボンディング後の圧着ボール直下のＡｌの残存量が多くなる結果、電極パッドの下層構造の破壊や、電極パッドの剥離を抑制することが出来る。   In wire bonding using an Au wire, bonding is generally performed while plastic deformation of the initial ball is performed by application of ultrasonic waves. Ultrasound is formed on the initial ball and the joint, destroying the oxide film and organic film, which hinders the joint, and exposing the new surface. According to the electrode pad structure according to the present embodiment, since the amount of Cu added is increased, the electrode pad layer 4 becomes hard, and ultrasonic waves can be applied even when a method of joining the initial ball while largely deforming is used. There is little rejection of the electrode pad layer 4 at the time. As a result of an increase in the amount of Al directly under the press-bonded ball after wire bonding, it is possible to suppress the destruction of the lower layer structure of the electrode pad and the peeling of the electrode pad.

図５は、比較例として、一般的な半導体チップの電極パッド部を示している。Ｓｉを基材１０とする半導体チップの内部配線には、０．５質量％のＣｕを含むＡｌから成る配線層１が用いられている。配線層１の厚さは、２μｍとしている。配線層１の下層側には、厚さ５００ｎｍのＴｉＮから成るバリアメタル層２ａが成膜されている。厚さ１μｍのポリイミドからなるパッシベーション膜３は、配線層１の表面の一部が１００μｍ角に取り除かれている。配線層１の上に形成されているパッシベーション膜３の開口部２０が金属ワイヤとの接合領域となる。   FIG. 5 shows an electrode pad portion of a general semiconductor chip as a comparative example. A wiring layer 1 made of Al containing 0.5% by mass of Cu is used for internal wiring of a semiconductor chip having Si as a base material 10. The thickness of the wiring layer 1 is 2 μm. On the lower layer side of the wiring layer 1, a barrier metal layer 2a made of TiN having a thickness of 500 nm is formed. In the passivation film 3 made of polyimide having a thickness of 1 μm, a part of the surface of the wiring layer 1 is removed to a 100 μm square. The opening 20 of the passivation film 3 formed on the wiring layer 1 becomes a bonding region with the metal wire.

図６は、比較例に係る電極パッド部を、Ｃｕ系のボンディングワイヤを使ってＡｕワイヤと同様の方法でワイヤボンディングした断面図である。Ａｕワイヤによる一般的なボンディングでは、超音波印加時に初期ボールの大きな変形を伴う。この方法で、Ｃｕ系のボンディングワイヤを電極パッド部に、ワイヤボンディングすると、ボンディングワイヤより軟らかく、Ｃｕを０．５質量％含むＡｌを材料とする配線層１が超音波印加時に選択的に変形する。電極パッド材（Ａｌ：配線層１）が圧着ボールの外周に大量に排斥された結果、圧着ボール直下の電極パッド材がかなり薄くなっている。最悪の場合には、圧着ボールが電極パッド部の下層構造に接触し、そこを起点に亀裂が生じる。   FIG. 6 is a cross-sectional view in which the electrode pad portion according to the comparative example is wire-bonded using a Cu-based bonding wire in the same manner as the Au wire. In general bonding using an Au wire, the initial ball is greatly deformed when an ultrasonic wave is applied. In this method, when a Cu-based bonding wire is wire-bonded to the electrode pad portion, the wiring layer 1 made of Al containing 0.5% by mass of Cu, which is softer than the bonding wire, is selectively deformed when an ultrasonic wave is applied. . As a result of a large amount of electrode pad material (Al: wiring layer 1) being rejected on the outer periphery of the press-bonded ball, the electrode pad material immediately below the press-bonded ball is considerably thinned. In the worst case, the press-bonded ball comes into contact with the lower layer structure of the electrode pad portion, and a crack is generated from that point.

図７は、実施の形態１に記載の半導体チップの電極パッド部に、荷重制御法を用いて Ｃｕ系のボンディングワイヤをワイヤボンディングした断面を示す図である。Ｃｕ系のボンディングワイヤを用いる場合、上記のように、初期ボールを超音波印加により塑性変形させる方法で接合を得ようとすると、Ａｌの排斥が大きくなる。荷重制御法でＣｕ系のボンディングワイヤを用いる場合、先ず荷重のみで初期ボールを所望の圧着径になるまで変形させた後、荷重を低下させた状態で超音波を印加する。この方法を用いることで、電極パッド層４の排斥をさらに軽減することができる。圧着ボールの形状は、初期の大きな荷重で決定される。初期ボールの変形に超音波振動が作用しないため、圧着ボールの真円度がよくなる効果もある。   FIG. 7 is a diagram showing a cross-section in which a Cu-based bonding wire is wire-bonded to the electrode pad portion of the semiconductor chip described in the first embodiment using a load control method. In the case of using a Cu-based bonding wire, as described above, if an attempt is made to obtain bonding by a method in which the initial ball is plastically deformed by application of ultrasonic waves, the rejection of Al increases. When using a Cu-based bonding wire in the load control method, first, the initial ball is deformed to a desired pressure-bonding diameter only by the load, and then an ultrasonic wave is applied in a state where the load is reduced. By using this method, the exclusion of the electrode pad layer 4 can be further reduced. The shape of the press-bonded ball is determined by an initial large load. Since ultrasonic vibration does not act on the deformation of the initial ball, the roundness of the press-bonded ball is also improved.

荷重制御法を用いてワイヤボンディングする場合には、初期ボールの巨視的な変形を伴う酸化膜や有機皮膜の破壊ではなく、接合界面の微視的な変形により、新生面を露出させることが必要となる。その際、接合界面に微細な凹凸があった方が、酸化膜や有機皮膜を破壊する起点となり、新生面を露出させやすい。本実施の形態の半導体チップは、ワイヤと接触する電極パッド層４の材料を、Ｃｕを３質量％含むＡｌから形成しているため、Ｃｕの析出物が表面に微細な凹凸を形成し、超音波印加時に酸化膜や有機皮膜を破壊する起点となる。新生面が露出しやすくなることで接合性が向上し、低い超音波出力でも接合が可能となり、Ｃｕ系のボンディングワイヤに特有の荷重制御法を用いた場合でも、半導体チップへのダメージは抑制される。なお，この実施の形態では，最も効果的であるＣｕ系のボンディングワイヤを用いた場合について述べたが，金属ワイヤはこれに限るものではない。ボンディングワイヤとして，Ａｕワイヤ、Ａｇワイヤなどのその他の金属ワイヤを用いた場合であっても、本実施例に示す電極パッド構造を適用することで不良率低減や信頼性向上の効果が得られることは言うまでもない。   When wire bonding is performed using the load control method, it is necessary to expose the new surface not by destroying the oxide film or organic film accompanying macroscopic deformation of the initial ball, but by microscopic deformation of the bonding interface. Become. At that time, if the bonding interface has fine irregularities, it becomes a starting point for destroying the oxide film and the organic film, and the new surface is easily exposed. In the semiconductor chip of this embodiment, since the material of the electrode pad layer 4 in contact with the wire is made of Al containing 3% by mass of Cu, Cu precipitates form fine irregularities on the surface, It becomes a starting point for destroying the oxide film and organic film when applying sound waves. The new surface can be easily exposed to improve the bondability, enabling bonding even with low ultrasonic output, and even when using a load control method specific to Cu-based bonding wires, damage to the semiconductor chip is suppressed. . In this embodiment, the case of using the most effective Cu-based bonding wire has been described, but the metal wire is not limited to this. Even when other metal wires such as Au wires and Ag wires are used as the bonding wires, the effect of reducing the defect rate and improving the reliability can be obtained by applying the electrode pad structure shown in this embodiment. Needless to say.

実施の形態２．
図８は、本発明の実施の形態２に係る半導体チップにおける電極パッド部の断面図である。配線層１は、０．５質量％のＣｕを含むＡｌから成り、Ｓｉを基材１０とする半導体チップの配線に用いられている。配線層１の厚さは、０．５μｍとしている。配線層１の表面側には、Ｃｕを３質量％含むＡｌから成る、厚さ２μｍの電極パッド層４が形成されている。電極パッド層４はビア５により直下の配線層１と接続されている。 Embodiment 2. FIG.
FIG. 8 is a cross-sectional view of the electrode pad portion in the semiconductor chip according to the second embodiment of the present invention. The wiring layer 1 is made of Al containing 0.5% by mass of Cu, and is used for wiring of a semiconductor chip using Si as a base material 10. The thickness of the wiring layer 1 is 0.5 μm. On the surface side of the wiring layer 1, an electrode pad layer 4 having a thickness of 2 μm and made of Al containing 3% by mass of Cu is formed. The electrode pad layer 4 is connected to the wiring layer 1 immediately below by a via 5.

配線層１の下層側には、厚さ５００ｎｍのＴｉＮから成るバリアメタル層２ａが成膜されている。配線層１と電極パッド層４との間には、厚さ５００ｎｍのＴｉＮから成るバリアメタル層２ｂが成膜されている。電極パッド層４の上層側には０．１μｍのＡｕからなる腐食防止膜６が形成されている。パッシベーション膜３は、配線層１と腐食防止膜６を被っている。腐食防止膜６の上には開口部２０が設けられていて、金属ワイヤとの接合領域を形成している。   On the lower layer side of the wiring layer 1, a barrier metal layer 2a made of TiN having a thickness of 500 nm is formed. A barrier metal layer 2 b made of TiN having a thickness of 500 nm is formed between the wiring layer 1 and the electrode pad layer 4. A corrosion prevention film 6 made of 0.1 μm Au is formed on the upper side of the electrode pad layer 4. The passivation film 3 covers the wiring layer 1 and the corrosion prevention film 6. An opening 20 is provided on the corrosion prevention film 6 to form a bonding region with the metal wire.

一般的な半導体パッケージは、エポキシ樹脂により封止されている。環境中の水分はエポキシ樹脂を透過するので、パッシベーション膜３で覆われていない金属ワイヤとの接合領域が腐食する場合がある。腐食防止膜６を最表面に形成することで、電極パッド層４の腐食を防止することができる。   A general semiconductor package is sealed with an epoxy resin. Since moisture in the environment permeates the epoxy resin, the joint region with the metal wire not covered with the passivation film 3 may corrode. The corrosion of the electrode pad layer 4 can be prevented by forming the corrosion prevention film 6 on the outermost surface.

腐食防止膜６は電極パッド層４の表面酸化を防止する効果もあるため、ボンディング時に酸化膜を破壊するために必要なエネルギが少なくなる。金属ワイヤを接合するときに、より小さい超音波出力でボンディングワイヤの接合が可能となり、電極パッドの下層の破
壊や接合部の剥離を抑制することができる。なお、この実施の形態においては、厚さ０．１μｍのＡｕからなる腐食防止膜について述べた。腐食防止膜はこれに限定するものではなく、貴金属（たとえば、Ｐｄ、Ｐｔ）など腐食しにくい物質であれば、同様の効果が得られる。 Since the corrosion prevention film 6 also has an effect of preventing the surface oxidation of the electrode pad layer 4, energy required for destroying the oxide film during bonding is reduced. When bonding metal wires, bonding wires can be bonded with a smaller ultrasonic output, and destruction of the lower layer of the electrode pad and peeling of the bonded portion can be suppressed. In this embodiment, the corrosion prevention film made of Au having a thickness of 0.1 μm has been described. The corrosion prevention film is not limited to this, and the same effect can be obtained as long as it is a substance that hardly corrodes, such as a noble metal (for example, Pd, Pt).

半導体チップにＳｉＣなどのワイドバンドギャップ半導体を用いた場合、半導体チップはその高温耐量を生かすために、Ｓｉを用いた場合と比較してより高温で動作させることになる。ワイドバンドギャップ半導体デバイスを搭載する半導体装置においては、高温動作に対応するために、より高い信頼性が求められるため、高信頼の半導体装置を実現するという本発明のメリットはより効果的なものとなる。   When a wide band gap semiconductor such as SiC is used for the semiconductor chip, the semiconductor chip is operated at a higher temperature than when Si is used in order to make use of the high temperature tolerance. In a semiconductor device equipped with a wide band gap semiconductor device, higher reliability is required in order to cope with high-temperature operation. Therefore, the merit of the present invention to realize a highly reliable semiconductor device is more effective. Become.

なお、本発明は、その発明の範囲内において、実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

この発明は、ボンディングワイヤを使用した半導体装置（および半導体チップ）において、外部電極と電極パッドの接合信頼性を向上することを目的にするものである。   An object of the present invention is to improve the bonding reliability between an external electrode and an electrode pad in a semiconductor device (and a semiconductor chip) using a bonding wire.

１ 配線層、２ａ バリアメタル層、２ｂ バリアメタル層、３ パッシベーション膜、４ 電極パッド層、５ ビア、６ 腐食防止膜、７ ボンディングワイヤ、８ 層間絶縁膜、１０ 基材、１１ 半導体チップ、１１Ａ トランジスタ、１１Ｂ ダイオード、１１Ｃ 制御素子、１４ 外部電極、１５ モールド樹脂部材、１６ ヒートシンク、２０ 開口部、２４ リードフレーム、１００ 半導体装置
DESCRIPTION OF SYMBOLS 1 Wiring layer, 2a Barrier metal layer, 2b Barrier metal layer, 3 Passivation film, 4 Electrode pad layer, 5 Via, 6 Corrosion prevention film, 7 Bonding wire, 8 Interlayer insulation film, 10 Base material, 11 Semiconductor chip, 11A Transistor , 11B diode, 11C control element, 14 external electrode, 15 mold resin member, 16 heat sink, 20 opening, 24 lead frame, 100 semiconductor device

Claims (12)

外部機器に接続される外部電極と、
層間絶縁膜の上に第１バリアメタル層とＡｌ系配線層とＡｌ系電極パッド層がこの順番で形成されてなる半導体チップと、
前記Ａｌ系電極パッド層と前記外部電極を接続するボンディングワイヤと、
前記外部電極と前記半導体チップと前記ボンディングワイヤを封止する樹脂部材と、を備え、
前記Ａｌ系電極パッド層は開口部を有するパッシベーション膜で周囲を被覆されていて、前記Ａｌ系電極パッド層は前記Ａｌ系配線層よりも多くのＣｕを含んでいることを特徴とする半導体装置。 An external electrode connected to an external device;
A semiconductor chip in which a first barrier metal layer, an Al-based wiring layer, and an Al-based electrode pad layer are formed in this order on the interlayer insulating film;
A bonding wire connecting the Al-based electrode pad layer and the external electrode;
A resin member for sealing the external electrode, the semiconductor chip, and the bonding wire;
The Al-based electrode pad layer is covered with a passivation film having an opening, and the Al-based electrode pad layer contains more Cu than the Al-based wiring layer. 前記ボンディングワイヤは、Ｃｕを主成分とすることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the bonding wire contains Cu as a main component. 前記Ａｌ系電極パッド層と前記Ａｌ系配線層の間に形成されている第２バリアメタル層を備えていることを特徴とする請求項１または２に記載の半導体装置。   3. The semiconductor device according to claim 1, further comprising a second barrier metal layer formed between the Al-based electrode pad layer and the Al-based wiring layer. 前記Ａｌ系電極パッド層と前記Ａｌ系配線層は、前記第２バリアメタル層を貫通するビアによって導通していることを特徴とする請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the Al-based electrode pad layer and the Al-based wiring layer are electrically connected by a via penetrating the second barrier metal layer. 前記Ａｌ系電極パッド層は腐食防止膜で被覆されていることを特徴とする請求項１から４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the Al-based electrode pad layer is covered with a corrosion prevention film. 前記Ａｌ系配線層は、０質量％から０．７質量％の範囲のＣｕを含んでいることを特徴とする請求項１から５のいずれか１項に記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the Al-based wiring layer contains Cu in a range of 0 mass% to 0.7 mass%. 前記Ａｌ系電極パッド層は、１質量％から５質量％の範囲のＣｕを含んでいることを特徴とする請求項１から６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the Al-based electrode pad layer includes Cu in a range of 1% by mass to 5% by mass. 前記腐食防止膜は、Ａｕ，ＰｄまたはＰｔを含んでなることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the corrosion prevention film contains Au, Pd, or Pt. 前記パッシベーション膜は、ポリイミドからなることを特徴とする請求項１から８のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the passivation film is made of polyimide. 前記第１バリアメタル層と前記第２バリアメタル層は、ＴｉＮ，Ｔｉ，ＴｉＯ２，ＴａまたはＴａＮからなることを特徴とする請求項３から９のいずれか１項に記載の半導体装置。   10. The semiconductor device according to claim 3, wherein the first barrier metal layer and the second barrier metal layer are made of TiN, Ti, TiO 2, Ta, or TaN. 11. 前記半導体チップの少なくとも一部がワイドバンドギャップ半導体により形成されていることを特徴とする請求項１から１０のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein at least a part of the semiconductor chip is formed of a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化珪素，窒化ガリウム系材料，ダイヤモンドのいずれかの半導体であることを特徴とする請求項１１に記載の半導体装置。
The semiconductor device according to claim 11, wherein the wide band gap semiconductor is one of silicon carbide, a gallium nitride-based material, and diamond.
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