JP2015119121A - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- JP2015119121A JP2015119121A JP2013263209A JP2013263209A JP2015119121A JP 2015119121 A JP2015119121 A JP 2015119121A JP 2013263209 A JP2013263209 A JP 2013263209A JP 2013263209 A JP2013263209 A JP 2013263209A JP 2015119121 A JP2015119121 A JP 2015119121A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract
Description
本発明は半導体装置に関するものであり、特に絶縁ゲート型バイポーラトランジスタ（Insulated Gate Bipolar Transistor：以下、「ＩＧＢＴ」と表記する）等のパワー半導体素子を有するパワー半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a power semiconductor device having a power semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as “IGBT”).
従来、パワー半導体の組立てに関する技術として、パワー回路に接続されるボンディングワイヤ等の配線部が外部振動によって断線するのを防止することを目的とし、パワー回路を覆う充填剤が樹脂プレートにより押えられる構造とすることで外部振動を受けたときの変位を防止するものや、制御回路と中継端子との半田接合部の破損を防止することを目的とし、制御回路基板が制御端子ブロックと樹脂プレートとの間に挟まれるように固定される構造とすることでそれらのねじ接合時における制御回路基板の変形を防止するものがあった（例えば、特許文献１参照）。 Conventionally, as a technique for assembling a power semiconductor, a structure in which a filler covering a power circuit is pressed by a resin plate for the purpose of preventing a wiring portion such as a bonding wire connected to the power circuit from being disconnected by an external vibration. In order to prevent displacement when external vibration is applied and to prevent damage to the solder joint between the control circuit and the relay terminal, the control circuit board is connected between the control terminal block and the resin plate. There has been a structure that prevents the control circuit board from being deformed at the time of screw joining by adopting a structure that is fixed so as to be sandwiched between them (see, for example, Patent Document 1).
また、従来、パワー半導体の組立てに関する技術として、外装樹脂ケース、ケース蓋、金属ベース板を組み合わせたパッケージに、絶縁基板にマウントした複数個の半導体素子、外部接続用の主回路端子および補助端子、内部接続用端子などを組み込んで構成した半導体装置において、各端子および異極端子間を連結するタイバーを導体金属板に展開して打ち抜き、かつ個々の端子にリード曲げ加工を施して立体的に構築した端子組立体を、外装樹脂ケースの内方に配置して該ケースと一体にモールド成形すると共に、金属ベース板と絶縁基板との半田付け、絶縁基板の導体パターンと内部端子との半田付け、および金属ベース板と外装樹脂ケースとの接着を同時に行って半導体装置を組立て構成するものがあった（例えば、特許文献２参照）。 Conventionally, as a technology related to the assembly of power semiconductors, a package combining an exterior resin case, a case lid, and a metal base plate, a plurality of semiconductor elements mounted on an insulating substrate, main circuit terminals and auxiliary terminals for external connection, In semiconductor devices built with internal connection terminals, etc., tie bars that connect each terminal and different-polarity terminals are developed on a conductive metal plate and punched, and lead bending is performed on each terminal to create a three-dimensional structure. The terminal assembly is placed inside the exterior resin case and molded integrally with the case, and soldering between the metal base plate and the insulating substrate, soldering between the conductor pattern of the insulating substrate and the internal terminal, In some cases, the metal base plate and the exterior resin case are bonded at the same time to assemble a semiconductor device (see, for example, Patent Document 2). .
また、従来、パワー半導体の端子接続に関する技術として、パワーチップが絶縁層を介して金属基板上に搭載され、蓋状ケースに設けた外部接続端子がパワーチップと接続され、金属基板上に取り付けられた外囲ケースと蓋状ケースとによりパワーチップを収納するパッケージケースを構成し、パワーチップがゲル状樹脂で封止されているパワーモジュール装置であって、外部接続端子部を除きパッケージケースの上部内面はフラットに形成され、蓋状ケースに設けた注入孔よりパッケージ内上部に空間を形成して注入されたゲル状樹脂の硬化物でパワーチップが封止されているものがあった（例えば、特許文献３参照）。 Conventionally, as a technology related to power semiconductor terminal connection, a power chip is mounted on a metal substrate via an insulating layer, and an external connection terminal provided on the lid-like case is connected to the power chip and attached to the metal substrate. A power module device in which a power chip is housed by an enclosed case and a lid-shaped case, and the power chip is sealed with a gel-like resin, and the upper part of the package case excluding external connection terminal portions The inner surface is formed in a flat shape, and the power chip is sealed with a cured product of a gel-like resin injected by forming a space in the upper part of the package from the injection hole provided in the lid-like case (for example, (See Patent Document 3).
パワー半導体装置は、大出力のモータや発電機等の電気機器の制御や電力変換のために用いられる半導体装置である。近年は、電車、電気自動車、ハイブリッド車や風力の電力制御装置としてパワー半導体装置の需要が拡大しており、高速化・高密度化による最高温度の上昇の要求も高まっている。 The power semiconductor device is a semiconductor device used for control of electric equipment such as a high-output motor and a generator and power conversion. In recent years, the demand for power semiconductor devices as electric power control devices for trains, electric vehicles, hybrid vehicles, and wind power has increased, and the demand for higher maximum temperatures due to higher speed and higher density has also increased.
家電製品に使用されている弱電系の半導体は、２００６年７月１日に施行されたＲｏＨＳ指令に基づき、鉛フリー化されている。パワー半導体を用いる輸送機器、医療関係は安全性の観点からＲｏＨＳ指令の対象でなかったが、近年の環境意識の高まりにより、鉛フリー化の要求が高くなっている。 Low-power semiconductors used in home appliances have been lead-free based on the RoHS directive enforced on July 1, 2006. Transportation equipment and medical care using power semiconductors were not subject to the RoHS Directive from the viewpoint of safety, but due to the recent increase in environmental awareness, there is a growing demand for lead-free.
従来、パワー半導体において、外部電流の出入り口の役割を果たす端子は回路と接続するが、その端子接続材は、実績のある鉛入りはんだを用いていた。回路上に予め設置した鉛入りはんだ、およびその近傍を、鉛入りはんだの融点以上の温度にしてはんだを溶かし、その溶けた鉛入りはんだの上に端子接続部を搭載した後、冷却し、固めることで接続していた。 Conventionally, in a power semiconductor, a terminal that serves as an entrance and exit port for an external current is connected to a circuit, and the terminal connecting material has used a proven lead-containing solder. Lead-containing solder installed on the circuit and its vicinity are heated to a temperature equal to or higher than the melting point of lead-containing solder, the solder is melted, and the terminal connection is mounted on the melted lead-containing solder, and then cooled and hardened. I was connected by that.
空調用や電車用など大電流・高耐圧のパワー半導体装置は端子の外部電流出入り口がモジュール中央部にある。鉛入りはんだに端子接続部を搭載するために、樹脂ケースに端子をインサートして固定して位置決めをする、ケース中央に端子を挿入する挿入口を設けて位置決めをする、などを実施している。樹脂ケースに端子をインサートする場合はコストが高くなるという課題がある。 Power semiconductor devices with high current and high withstand voltage, such as those for air conditioning and trains, have an external current inlet / outlet of the terminal in the center of the module. In order to mount the terminal connection part on lead-containing solder, the terminal is inserted and fixed in the resin case for positioning, and the insertion port for inserting the terminal is provided in the center of the case for positioning. . When a terminal is inserted into a resin case, there is a problem that the cost increases.
電力変換機や電車のインバータに搭載されるパワー半導体装置は、大電流に耐えられる高信頼性が要求される。そのパワー半導体は稼動時に高温にさらされるため、電気的接続を行う接続部の信頼性を確保することが重要である。従来、その端子と回路との接続には実績がある鉛はんだを接続材に用いていた。しかし鉛フリー化を図るために、端子と回路とをメタルボンディングで接続する。メタルボンディングは端子接続部の上面に超音波振動を与え、その振動により接続面を溶かし、接続する技術である。このメタルボンディング時には接続部に負荷がかかるため、端子の固定が必要である。また、このメタルボンディングで発生する残材除去、かつメタルボンディング後の接続面確認作業が必要である。 Power semiconductor devices mounted on power converters and train inverters are required to have high reliability capable of withstanding large currents. Since the power semiconductor is exposed to a high temperature during operation, it is important to ensure the reliability of the connecting portion for electrical connection. Conventionally, lead solder with a proven track record has been used for connection between the terminal and the circuit. However, in order to achieve lead-free, terminals and circuits are connected by metal bonding. Metal bonding is a technique in which ultrasonic vibration is applied to the upper surface of the terminal connection portion, and the connection surface is melted and connected by the vibration. Since a load is applied to the connection portion during the metal bonding, it is necessary to fix the terminals. In addition, it is necessary to remove the remaining material generated in the metal bonding and to confirm the connection surface after the metal bonding.
したがって、本発明が解決しようとする課題は、大電流にも耐えられ、かつ厳しい温度環境下においても接続部の信頼性を維持し、従来のパワー半導体装置と共通の接続位置と端子出入り口が確保でき、かつ接続部の位置決めが簡単で、かつ接続後の検査や異物除去が可能で、かつ組立が複雑ではないことを目的としたパワー半導体装置を提供することである。 Therefore, the problem to be solved by the present invention is that it can withstand a large current, maintain the reliability of the connection part even in a severe temperature environment, and ensure a common connection position and terminal entrance / exit with the conventional power semiconductor device. It is an object of the present invention to provide a power semiconductor device that is capable of being positioned easily, positioning a connecting portion, inspecting and removing foreign matter after connection, and not complicated to assemble.
上記課題を解決するために、本発明のパワー半導体装置は、端子とケースふたと回路とを有するパワー半導体装置であって、前記ケースふたに１つ以上の端子挿入口を有し、前記端子の前記回路との接続部が、上から見た場合、前記ケースふたに隠れることなく、概観できることを特徴とする。 In order to solve the above problems, a power semiconductor device according to the present invention is a power semiconductor device having a terminal, a case lid, and a circuit, the case lid having one or more terminal insertion ports, The connection portion with the circuit can be viewed without being hidden by the case lid when viewed from above.
より具体的には、本発明のパワー半導体装置は、ベースと、前記ベースの一方の面に基板下はんだを介して搭載される基板と、前記基板の前記ベースとは反対側の面にチップ下はんだを介して搭載されるチップと、ワイヤを介して前記チップと電気的に接続されると共に前記基板の前記チップが搭載される面と同じ面に形成される回路と、端子接続部を介して前記回路と電気的に接続される端子とを備えたパワー半導体装置であって、前記端子を収容しつつ、前記パワー半導体装置が前記端子を介して前記パワー半導体装置外部の装置と電気的に接続できるよう、前記端子の先端の一部を露出させるよう構成されたケースふたを更に備え、前記端子は、前記回路と前記端子とをメタルボンディング接続するために超音波を与える部分であり、かつ、前記パワー半導体装置の外部から目視可能に構成された端子接続部を有することを特徴とする。 More specifically, the power semiconductor device of the present invention includes a base, a substrate mounted on one surface of the base via solder under the substrate, and a chip below the surface of the substrate opposite to the base. A chip mounted via solder, a circuit electrically connected to the chip via a wire and formed on the same surface as the surface on which the chip is mounted, via a terminal connection portion A power semiconductor device comprising a terminal electrically connected to the circuit, wherein the power semiconductor device is electrically connected to a device outside the power semiconductor device via the terminal while housing the terminal. The terminal further includes a case lid configured to expose a part of the tip of the terminal, and the terminal is a portion for applying an ultrasonic wave to connect the circuit and the terminal by metal bonding, One, characterized in that it has the power terminal connection configured externally visible in the semiconductor device.
本発明によれば、メタルボンディングで端子と回路とを接続して製造されるパワー半導体装置において、端子と回路との接続のための位置決めを容易ならしめて組立工数の低減を可能にすると共に、メタルボンディング後に目視などの検査を可能にすることができる。 According to the present invention, in a power semiconductor device manufactured by connecting a terminal and a circuit by metal bonding, positioning for connecting the terminal and the circuit is facilitated, and the number of assembly steps can be reduced. Inspection such as visual inspection can be made possible after bonding.
以下、本発明の実施に好適な実施例を説明する。 Hereinafter, preferred examples for carrying out the present invention will be described.
本発明の実施例１について、図面を参照しながら詳細に説明する。 Embodiment 1 of the present invention will be described in detail with reference to the drawings.
図１は本実施例に係るパワー半導体装置の上面模式図である。図２は当該パワー半導体装置の断面模式図である。 FIG. 1 is a schematic top view of a power semiconductor device according to this embodiment. FIG. 2 is a schematic cross-sectional view of the power semiconductor device.
図１、図２において、パワー半導体装置は、ベース５と、当該ベース５の一方の面に基板下はんだ９を介して搭載される基板８と、当該基板８のベース５とは反対側の面にチップ下はんだ７を介して搭載されるチップ３と、ワイヤ６を介してチップ３と電気的に接続されると共に基板８のチップ３が搭載される面と同じ面に形成される回路４と、端子接続部１ａを介して回路４と電気的に接続される端子１と、当該端子１を収容しつつ、パワー半導体装置が端子１を介してパワー半導体装置外部の装置と電気的に接続できるよう、端子１の先端の一部を露出させるよう構成されたケースふた２とを備えて構成される。 1 and 2, the power semiconductor device includes a base 5, a substrate 8 mounted on one surface of the base 5 via a sub-substrate solder 9, and a surface of the substrate 8 opposite to the base 5. And a circuit 4 formed on the same surface as the surface on which the chip 3 of the substrate 8 is mounted, while being electrically connected to the chip 3 via the wire 6. The terminal 1 electrically connected to the circuit 4 via the terminal connection portion 1a, and the power semiconductor device can be electrically connected to a device outside the power semiconductor device via the terminal 1 while accommodating the terminal 1. The case lid 2 is configured to expose a part of the tip of the terminal 1.
端子１は、パワー半導体装置の外部と当該パワー半導体装置の内部に設けられた回路４との間の電流のやり取りを行うための電流出入り口として機能するものであって、２本で１対を成しており、一方が電流取入れ口であり、他方が電流取り出し口である。端子１の一方である電流取入れ口の端子で取り入れられた入力電流は、回路４およびワイヤ６を通じてチップ３に流れ、当該チップ３にて周波数応答制御が行われる。周波数応答制御を通して得られた出力電流は、ワイヤ６および回路４を通じて端子１の他方である電流取出し口の端子を通ってパワー半導体装置の外部へ出て行く。端子１にはバスバーが取り付けられるため、端子１の上部（パワー半導体装置のベース５側を下方とした場合の上方すなわち図２における上方の、ケースふた２より上方に突出している部分であって、図１においてケースふた２の領域内で露出している部分）の穴（図１において「○」で示した部分）はバスバーを止めるためのボルト穴である。尚、図１ではワイヤ６の図示は省略している。 The terminal 1 functions as a current inlet / outlet for exchanging current between the outside of the power semiconductor device and the circuit 4 provided inside the power semiconductor device, and two terminals form a pair. One is a current inlet and the other is a current outlet. The input current taken in at the terminal of the current inlet that is one of the terminals 1 flows to the chip 3 through the circuit 4 and the wire 6, and frequency response control is performed in the chip 3. The output current obtained through the frequency response control goes out of the power semiconductor device through the wire 6 and the circuit 4 through the terminal of the current extraction port which is the other of the terminals 1. Since the bus bar is attached to the terminal 1, the upper portion of the terminal 1 (the portion protruding above the case lid 2 above the upper side in FIG. In FIG. 1, holes (portions exposed in the region of the case lid 2) (portions indicated by “◯” in FIG. 1) are bolt holes for stopping the bus bar. In FIG. 1, the wire 6 is not shown.
ケースふた２は、図１に示すように、隙間部２ａを有している。当該隙間部２ａは、端子１と同じ形状の凹凸部のある隙間部であれば好適であるが、本発明はそれに限定されるものではなく、端子１と異なる形状であっても、端子１を挿入可能に形成され、かつ、凹凸部などがあることによってその端子１を固定することができる形状であればよい。隙間部２ａは、端子１を挿入し、かつ固定することができるよう、端子１を隙間部２ａに挿入したときの端子１と隙間部２ａの縁（へり）との間隔が０．５ｍｍ以下になるよう隙間厚さが調整されるのが好適である。また、隙間部２ａは、挿入された端子１を固定するために、端子１と同様の凹凸形状を有するのが好適である。この凹凸形状の隙間部２ａに端子１を挿入口からケースふた２の中央方向に向かって押し込むことにより、端子１はケースふた２に固定される。それと共に、押し込むことにより端子１が固定される位置が端子１と回路４との接続部の規定位置になっており、端子１と回路４とを電気的に接続するメタルボンディングが実施されるべき当該接続部の位置がこのとき決定する。 As shown in FIG. 1, the case lid 2 has a gap 2a. The gap 2a is preferably a gap having an uneven portion having the same shape as that of the terminal 1, but the present invention is not limited thereto, and the terminal 1 may be formed even if it has a shape different from that of the terminal 1. Any shape can be used as long as the terminal 1 can be fixed by being formed so as to be insertable and having an uneven portion. The gap portion 2a has a distance of 0.5 mm or less between the terminal 1 and the edge (edge) of the gap portion 2a when the terminal 1 is inserted into the gap portion 2a so that the terminal 1 can be inserted and fixed. It is preferable that the gap thickness is adjusted so as to be. Moreover, it is preferable that the gap portion 2 a has the same uneven shape as the terminal 1 in order to fix the inserted terminal 1. The terminal 1 is fixed to the case lid 2 by pushing the terminal 1 from the insertion port toward the center of the case lid 2 into the uneven gap 2a. At the same time, the position where the terminal 1 is fixed by being pushed in is the specified position of the connection portion between the terminal 1 and the circuit 4, and metal bonding for electrically connecting the terminal 1 and the circuit 4 should be performed. The position of the connecting portion is determined at this time.
端子接続部１ａは端子１の一部であって、回路４と端子１とをメタルボンディング接続するために超音波を与える部分である。この部分にメタルボンディング装置により超音波荷重が与えられ、端子１の端子接続部１ａの表面と回路４の表面とが結合する。従来はこの接続を鉛入りはんだで実施していたが、本発明においては、この端子接続部１ａがパワー半導体装置の外部から目視可能に構成されるため、超音波を用いたメタルボンディングで実施可能である。 The terminal connection portion 1a is a part of the terminal 1, and is a portion that applies ultrasonic waves to connect the circuit 4 and the terminal 1 by metal bonding. An ultrasonic load is applied to this portion by a metal bonding apparatus, and the surface of the terminal connection portion 1a of the terminal 1 and the surface of the circuit 4 are coupled. Conventionally, this connection has been performed with lead-containing solder. However, in the present invention, this terminal connection portion 1a is configured to be visible from the outside of the power semiconductor device, and therefore can be performed by metal bonding using ultrasonic waves. It is.
ケースふた２の隙間部２ａに端子１を押し込むことにより端子１と回路４との位置関係は決定するが、メタルボンディングの超音波振動により端子１と回路４との相対的位置がずれないように、クランプ（図示せず）などを用いて、端子１とケースふた２との複合体と、それ以外の部材とを互いに固定するのが好適である。ここで、「それ以外の部材」とは、チップ３、回路４、ベース５、ワイヤ６、チップ下はんだ７、基板８、および基板下はんだ９の一部または全部である。その各々は、はんだ接続もしくは圧着により直接的または間接的にベース５に固定されている。そのため、クランプなどの固定用部材による荷重、メタルボンディングによる荷重、またははんだ接続のための温度荷重などで各部材がベース５から分離して互いにばらばらになることはない。 Although the positional relationship between the terminal 1 and the circuit 4 is determined by pushing the terminal 1 into the gap 2a of the case lid 2, the relative position between the terminal 1 and the circuit 4 is not shifted due to ultrasonic vibration of metal bonding. It is preferable that the composite of the terminal 1 and the case lid 2 and the other members are fixed to each other using a clamp (not shown) or the like. Here, the “other members” are a part or all of the chip 3, the circuit 4, the base 5, the wire 6, the under-chip solder 7, the substrate 8, and the under-substrate solder 9. Each of them is fixed to the base 5 directly or indirectly by solder connection or crimping. Therefore, the members are not separated from the base 5 and separated from each other by a load due to a fixing member such as a clamp, a load due to metal bonding, or a temperature load for solder connection.
また、メタルボンディング実施に伴い残材が発生することがあるが、パワー半導体装置にケース側面が無い、つまり、ケースふた２を装着した状態でも端子１と回路４との接続部を含む基板８上の要素が外部に晒される構造であるため、気体噴射等によって当該残材を除去することが容易であり、さらに、ケースふた２の下部やチップ３の周辺などに残材が残っていないかを目視などにより検査することが容易である。また、回路４と端子１とを超音波接続するために超音波が与えられる部分である端子接続部１ａがケースふた２より外側に位置していることにより、上からも横からもメタルボンディングが可能である。 In addition, there is a case where a remaining material may be generated due to the metal bonding, but the power semiconductor device has no case side surface, that is, on the substrate 8 including the connection portion between the terminal 1 and the circuit 4 even when the case lid 2 is attached. Since the element is exposed to the outside, it is easy to remove the remaining material by gas injection or the like. Further, whether the remaining material remains in the lower part of the case lid 2 or the periphery of the chip 3 is checked. It is easy to inspect visually. In addition, since the terminal connection portion 1a, which is a portion to which ultrasonic waves are applied in order to ultrasonically connect the circuit 4 and the terminal 1, is located outside the case lid 2, metal bonding can be performed from above and from the side. Is possible.
チップ３は、例えばＩＧＢＴ等のパワー半導体素子や、そのパワー半導体素子と電気的に接続されることによりスイッチング動作を実現する半導体ダイオード素子などであるが、パワー半導体素子としては、ＩＧＢＴに代えて、例えばシリコン（Si）または炭化シリコン（SiC）を主成分として形成されたＭＯＳ型電界効果トランジスタ（ＭＯＳＦＥＴ）を用いることもできる。本発明はチップ３のパワー半導体素子の種類に限定されることはなく、チップ３が上記のＩＧＢＴやＭＯＳＦＥＴ以外のパワー半導体素子とされたパワー半導体装置も本発明の技術的範囲に含まれる。 The chip 3 is, for example, a power semiconductor element such as an IGBT, or a semiconductor diode element that realizes a switching operation by being electrically connected to the power semiconductor element. However, as the power semiconductor element, instead of the IGBT, For example, a MOS field effect transistor (MOSFET) formed using silicon (Si) or silicon carbide (SiC) as a main component can also be used. The present invention is not limited to the type of power semiconductor element of the chip 3, and a power semiconductor device in which the chip 3 is a power semiconductor element other than the above-described IGBT and MOSFET is also included in the technical scope of the present invention.
回路４は、端子１から入力された入力電流をチップ３へ伝送し、また、チップ３から出力された出力電流を端子１へ伝送するための配線（図示せず）、および当該配線に対して電気的に接続されたコンデンサ（容量）等の単体回路部品（図示せず）を備えて構成されるが、本発明は回路４を構成する要素の種類に限定されることはなく、回路４が端子１とチップ３との間の電流の受け渡しに供する回路となっているパワー半導体装置であれば本発明の技術的範囲に含まれる。 The circuit 4 transmits an input current input from the terminal 1 to the chip 3, a wiring (not shown) for transmitting the output current output from the chip 3 to the terminal 1, and the wiring Although it is configured with a single circuit component (not shown) such as an electrically connected capacitor (capacitance), the present invention is not limited to the types of elements constituting the circuit 4, and the circuit 4 Any power semiconductor device that is a circuit for passing current between the terminal 1 and the chip 3 is included in the technical scope of the present invention.
ワイヤ６は、チップ３の外部端子（図示せず）と回路４とを電気的に接続する導体であるが、本発明はワイヤ６を構成する材料の種類やワイヤ６のチップ３上または回路４上の位置に限定されることはなく、ワイヤ６がチップ３と回路４との間の電流の受け渡しに供する物体となっているパワー半導体装置であれば本発明の技術的範囲に含まれる。 The wire 6 is a conductor that electrically connects an external terminal (not shown) of the chip 3 and the circuit 4, but in the present invention, the type of material constituting the wire 6, the chip 6 of the wire 6, or the circuit 4 is used. The power position is not limited to the above position, and any power semiconductor device in which the wire 6 is an object for passing current between the chip 3 and the circuit 4 is included in the technical scope of the present invention.
基板８は、一方の面にチップ３が搭載されると共にその同じ面に回路４が形成され、他方の面がベース５との接続面とされる板状の物体であって、例えばエポキシ樹脂等の樹脂あるいはセラミック等を主成分として形成されるものである。本発明は基板８を構成する材料の種類に限定されることはなく、基板８が、その一方の面にチップ３を搭載することができると共にその同じ面に回路４を形成することができ、かつ、他方の面をベース５との接続面とすることができる板状の物体となっているパワー半導体装置であれば、本発明の技術的範囲に含まれる。 The substrate 8 is a plate-like object in which the chip 3 is mounted on one surface and the circuit 4 is formed on the same surface, and the other surface is a connection surface with the base 5. The resin or ceramic is used as a main component. The present invention is not limited to the type of material constituting the substrate 8, and the substrate 8 can mount the chip 3 on one surface thereof and form the circuit 4 on the same surface, In addition, any power semiconductor device that is a plate-like object whose other surface can be a connection surface with the base 5 is included in the technical scope of the present invention.
チップ下はんだ７は、チップ３と基板８との間に挟まれて設けられ、チップ３を基板８上に固定すると共にチップ３で発生した熱を基板８に放出するのに供する接続部材であり、通常、チップ３と基板８との間に挿入されたはんだシートに熱処理（リフロー）が施されることによって形成される。本発明はチップ下はんだ７を構成する材料の種類に限定されることはなく、チップ下はんだ７がチップ３を基板８上に固定すると共にチップ３で発生した熱を基板８に放出するのに供する接続部材となっているパワー半導体装置であれば、本発明の技術的範囲に含まれる。 The under-chip solder 7 is provided between the chip 3 and the substrate 8 so as to fix the chip 3 on the substrate 8 and to release the heat generated in the chip 3 to the substrate 8. Usually, it is formed by subjecting the solder sheet inserted between the chip 3 and the substrate 8 to heat treatment (reflow). The present invention is not limited to the type of material constituting the under-chip solder 7, and the under-chip solder 7 fixes the chip 3 on the substrate 8 and releases the heat generated in the chip 3 to the substrate 8. Any power semiconductor device serving as a connecting member to be provided is included in the technical scope of the present invention.
ベース５は、チップ３や回路４が搭載された基板８が一方の面に搭載される板状の物体であって、通常、金属を主成分として形成される。ベース５は、その一方の面に搭載される基板８、当該基板８上の回路４と接続される端子１、さらには当該端子１が挿入されてパワー半導体装置のケースとして機能するケースふた２の荷重を機械的に支持すると共に、チップ３で発生し基板８を介して伝導された熱をパワー半導体装置の外部へ放出するのに供する。しかし、本発明はベース５を構成する材料の種類に限定されることはなく、ベース５がその一方の面に基板８を搭載することができる板状の物体となっているパワー半導体装置であれば本発明の技術的範囲に含まれる。また、ベース５がチップ３で発生する熱を放熱するのに寄与する程度以上の熱伝導率を有する板状の物体となっていればなお好適であり、そのようなパワー半導体装置の構成も本発明の技術的範囲に含まれる。 The base 5 is a plate-like object on which a substrate 8 on which the chip 3 and the circuit 4 are mounted is mounted on one surface, and is usually formed mainly of metal. The base 5 includes a substrate 8 mounted on one surface thereof, a terminal 1 connected to the circuit 4 on the substrate 8, and a case lid 2 into which the terminal 1 is inserted and functions as a case of a power semiconductor device. In addition to mechanically supporting the load, the heat generated in the chip 3 and conducted through the substrate 8 is released to the outside of the power semiconductor device. However, the present invention is not limited to the type of material constituting the base 5, and may be a power semiconductor device in which the base 5 is a plate-like object on which the substrate 8 can be mounted. Are included in the technical scope of the present invention. Further, it is more preferable that the base 5 is a plate-like object having a thermal conductivity higher than that which contributes to radiating the heat generated by the chip 3, and the configuration of such a power semiconductor device is also this. It is included in the technical scope of the invention.
基板下はんだ９は、基板８とベース５との間に挟まれて設けられ、基板８をベース５上に固定すると共に、チップ３で発生し基板８に放出された熱をベース５に放出するのに供する接続部材であり、通常、基板８とベース５との間に挿入されたはんだシートに熱処理（リフロー）が施されることによって形成される。本発明は基板下はんだ９を構成する材料の種類に限定されることはなく、基板下はんだ９が基板８をベース５上に固定すると共にチップ３で発生した熱をベース５に放出するのに供する接続部材となっているパワー半導体装置であれば、本発明の技術的範囲に含まれる。 The under-substrate solder 9 is provided so as to be sandwiched between the substrate 8 and the base 5, and fixes the substrate 8 on the base 5, and releases heat generated in the chip 3 and released to the substrate 8 to the base 5. It is a connection member for use in this process, and is usually formed by subjecting a solder sheet inserted between the substrate 8 and the base 5 to heat treatment (reflow). The present invention is not limited to the type of material constituting the under-substrate solder 9, and the under-substrate solder 9 fixes the substrate 8 on the base 5 and releases the heat generated in the chip 3 to the base 5. Any power semiconductor device serving as a connecting member to be provided is included in the technical scope of the present invention.
本実施例によれば、端子１を回路４と接続する接続部におけるメタルボンディング固定が容易にでき、固定治具を用いずとも簡単に回路４と端子１との接続位置決めが可能な製造コスト低減に寄与するパワー半導体装置を提供することができる。また、厳しい温度環境下においても部材接続信頼性を維持することが可能なパワー半導体装置を提供することができる。さらには、接続面の検査を容易ならしめ、また、送風などによる残材除去を可能ならしめる構造を有するパワー半導体装置を提供することができる。 According to the present embodiment, the metal bonding can be easily fixed at the connection portion connecting the terminal 1 to the circuit 4, and the manufacturing cost can be easily reduced without using a fixing jig. A power semiconductor device that contributes to the above can be provided. In addition, it is possible to provide a power semiconductor device capable of maintaining member connection reliability even in a severe temperature environment. Furthermore, it is possible to provide a power semiconductor device having a structure that makes it easy to inspect the connection surface and enables removal of the remaining material by blowing air or the like.
本発明の実施例２について、図面を参照しながら詳細に説明する。 Embodiment 2 of the present invention will be described in detail with reference to the drawings.
図３は本実施例に係るパワー半導体装置の上面模式図である。図４は当該パワー半導体装置の断面模式図である。 FIG. 3 is a schematic top view of the power semiconductor device according to the present embodiment. FIG. 4 is a schematic cross-sectional view of the power semiconductor device.
実施例１ではケースふた２の隙間２ａに端子１が挿入されて、ケースふた２の上から見た場合、ケースふた２の外側にメタルボンディングの端子接続部１ａがあるものについて説明したが、本発明は、パワー半導体装置を上から見た場合にメタルボンディングの端子接続部１ａがケースふた２の領域の外側に見える態様に限定されるものではなく、端子接続部１ａがケースふた２の領域の内側にある態様であっても、例えば本実施例に係る図３に示すように、ケースふた２が中央に穴を有しており、その上から見た場合にその穴の中に、メタルボンディングの端子接続部１ａが概観できる構造であればよく、そのようなパワー半導体装置の構成も本発明の技術的範囲に含まれる。尚、本実施例は、ケースふた２の形状が実施例１における形状と異なる点以外は実施例１と同様であるので、重複を避けるため説明を省略する。 In the first embodiment, the terminal 1 is inserted into the gap 2a of the case lid 2, and when viewed from above the case lid 2, the case where the metal bonding terminal connection portion 1a is located outside the case lid 2 has been described. The present invention is not limited to a mode in which the metal bonding terminal connection portion 1a is visible outside the region of the case lid 2 when the power semiconductor device is viewed from above. Even if it is an aspect inside, for example, as shown in FIG. 3 according to the present embodiment, the case lid 2 has a hole in the center, and when viewed from above, the metal bonding is formed in the hole. The structure of the power semiconductor device is also included in the technical scope of the present invention. The present embodiment is the same as the first embodiment except that the shape of the case lid 2 is different from the shape in the first embodiment, and thus the description thereof is omitted to avoid duplication.
本実施例によれば、ケースふた２全体のベース５平面方向の大きさが大きく、パワー半導体装置を上から見た場合にケースふた２全体の領域がメタルボンディングの端子接続部１ａを覆ってしまうような場合でも、実施例１と同様に、回路４と端子１との接続位置決めが容易な、製造コスト低減に寄与するパワー半導体装置を提供することができる。また、厳しい温度環境下においても部材接続信頼性を維持することが可能なパワー半導体装置を提供することができる点、さらには、接続面の検査を容易ならしめ、また、送風などによる残材除去を可能ならしめる構造を有するパワー半導体装置を提供することができる点は、実施例１と同様である。 According to this embodiment, the size of the entire case lid 2 in the plane direction of the base 5 is large, and when the power semiconductor device is viewed from above, the entire region of the case lid 2 covers the terminal connection portion 1a for metal bonding. Even in such a case, similarly to the first embodiment, it is possible to provide a power semiconductor device that can easily connect and position the circuit 4 and the terminal 1 and contribute to a reduction in manufacturing cost. In addition, it is possible to provide a power semiconductor device that can maintain the connection reliability of the members even under severe temperature environments. Furthermore, the inspection of the connection surface is facilitated, and the remaining material is removed by blowing air. Similar to the first embodiment, a power semiconductor device having a structure capable of achieving the above can be provided.
本発明の実施例３について、図面を参照しながら詳細に説明する。 Embodiment 3 of the present invention will be described in detail with reference to the drawings.
図５は本実施例に係るパワー半導体装置の断面模式図である。 FIG. 5 is a schematic cross-sectional view of the power semiconductor device according to this example.
実施例１では、端子１をケースふた２に挿入する例を示したが、それはケースふた２の隙間部２ａに挿入するものであって、ケースふた２の下面の端子はケースふた２による拘束を持たなかった。本発明はケースふた２の形状が端子によって限定されるものではなく、例えば本実施例に係る図５の断面図に示すように、ケースふた２の下面にある端子を押さえる突起物２ｂを有することも許容される。 In Example 1, although the example which inserts the terminal 1 in the case lid 2 was shown, it inserts in the clearance gap 2a of the case lid 2, and the terminal of the lower surface of the case lid 2 is restrained by the case lid 2. I didn't have it. In the present invention, the shape of the case lid 2 is not limited by the terminals. For example, as shown in the cross-sectional view of FIG. 5 according to this embodiment, the case lid 2 has a protrusion 2b that holds the terminal on the lower surface of the case lid 2. Is also acceptable.
端子の固有振動数は端子長さに反比例するため、拘束点を多くすることで、端子の固有振動数が上げられるため、稼動領域の周波数よりも固有振動数を大きくしておけば、免振することができる。尚、本実施例は、ケースふた２の形状が実施例１における形状と異なる点以外は実施例１と同様であるので、重複を避けるため説明を省略する。 Since the natural frequency of the terminal is inversely proportional to the terminal length, increasing the number of restraints increases the natural frequency of the terminal. can do. The present embodiment is the same as the first embodiment except that the shape of the case lid 2 is different from the shape in the first embodiment, and thus the description thereof is omitted to avoid duplication.
本実施例によれば、実施例１と比較して端子の共振周波数を変更することができるため、共振による信頼性低下を抑制することができる。さらに、上述した実施例１の利点も実施例１と同様に得ることができる。 According to the present embodiment, since the resonance frequency of the terminal can be changed as compared with Embodiment 1, it is possible to suppress a decrease in reliability due to resonance. Further, the advantages of the first embodiment described above can be obtained in the same manner as the first embodiment.
本発明の実施例４について、図面を参照しながら詳細に説明する。 Embodiment 4 of the present invention will be described in detail with reference to the drawings.
図６は本実施例に係るケースふた２の３次元モデルを示す図である。 FIG. 6 is a diagram showing a three-dimensional model of the case lid 2 according to the present embodiment.
実施例１では、パワー半導体装置にケースふた２を装着した後に、ケースふた２の隙間部２ａに端子１を挿入する例を示したが、ケースふた２がメタルボンディングの荷重に耐えられるよう、図６のように、端子１をケースふた２の隙間部２ａに挿入した後、隙間部２ａに隙間部２ａと同じ形状または類似の形状の部材２ｃを挿入するのが好適である。 In the first embodiment, the case 1 is shown in which the terminal 1 is inserted into the gap 2a of the case lid 2 after the case lid 2 is mounted on the power semiconductor device. However, the case lid 2 is shown in FIG. 6, after the terminal 1 is inserted into the gap 2a of the case lid 2, it is preferable to insert a member 2c having the same shape as or similar to the gap 2a into the gap 2a.
本実施例によれば、部材２ｃの隙間部２ａからはみ出す部分を大きく取ることで、部材２ｃが隙間部２ａの防塵の役割を果たすようにすることが可能である。逆に、部材２ｃを隙間部２ａよりも少し小さくすれば、部材２ｃが挿入された隙間部２ａに端子１との隙間ができるので、防塵のための樹脂埋めを容易に行うことが可能となる。さらに、上述した実施例１の利点も実施例１と同様に得ることができる。 According to the present embodiment, it is possible to make the member 2c play a role of dust-proofing the gap portion 2a by taking a large portion of the member 2c that protrudes from the gap portion 2a. On the contrary, if the member 2c is made slightly smaller than the gap 2a, a gap with the terminal 1 is formed in the gap 2a in which the member 2c is inserted, and therefore it is possible to easily fill the resin for dust prevention. . Further, the advantages of the first embodiment described above can be obtained in the same manner as the first embodiment.
本発明の実施例５について、図面を参照しながら詳細に説明する。 Embodiment 5 of the present invention will be described in detail with reference to the drawings.
図７は本実施例に係るパワー半導体装置の断面模式図である。 FIG. 7 is a schematic cross-sectional view of the power semiconductor device according to this example.
実施例１では、ケースふた２の隙間部２ａを端子１と同じ形状とした例を示したが、図７のように、ケースふた２の外部電流の出入り口付近に少し大きめの空間２ｄを設けてもよい。 In the first embodiment, the gap 2a of the case lid 2 has the same shape as that of the terminal 1. However, as shown in FIG. 7, a slightly larger space 2d is provided in the vicinity of the entrance / exit of the external current of the case lid 2. Also good.
本実施例によれば、防塵のための樹脂埋めをより一層、容易に行うことが可能となる。さらに、上述した実施例１の利点も実施例１と同様に得ることができる。 According to the present embodiment, it is possible to more easily fill the resin for dust prevention. Further, the advantages of the first embodiment described above can be obtained in the same manner as the first embodiment.
以上、本発明の各実施例について説明したが、上記各実施例はあくまでも本発明を実施する上での一例にすぎず、上記各実施例に係るパワー半導体装置の構成について、本発明の要旨を逸脱しない範囲でその一部を他の構成に置換したり、その一部を削除したり、他の構成を追加したりすることが可能であり、そのように置換・削除・追加して得られるパワー半導体装置の構成もまた本発明の技術的範囲に含まれることは言うまでもない。 The embodiments of the present invention have been described above. However, the embodiments described above are merely examples for carrying out the present invention, and the gist of the present invention regarding the configuration of the power semiconductor device according to each of the embodiments is described. It is possible to replace a part of it with another configuration, delete a part of it, or add another configuration without departing from the scope. It goes without saying that the configuration of the power semiconductor device is also included in the technical scope of the present invention.
１ 端子
２ ケースふた
３ チップ
４ 回路
５ ベース
６ ワイヤ
７ チップ下はんだ
８ 基板
９ 基板下はんだ
1 Terminal 2 Case lid 3 Chip 4 Circuit 5 Base 6 Wire 7 Chip under solder 8 Substrate 9 Substrate solder
Claims (11)
前記ケースふたに1つ以上の端子挿入口を有し、端子の回路との接続部が、上から見た場合、ケースふたに隠れることなく、概観できる
ことを特徴とするパワー半導体装置。 A power semiconductor device having a terminal, a case lid and a circuit,
A power semiconductor device, wherein the case lid has one or more terminal insertion openings, and a connection portion of the terminal with the circuit can be viewed without being hidden by the case lid when viewed from above.
前記ケースに１つ以上の端子挿入口を有し、ケースふた中央部に穴を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device having one or more terminal insertion holes in the case and a hole in a central portion of the case lid.
前記ケースふたに端子を固定する突起部を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device comprising a protrusion for fixing a terminal to the case lid.
前記ケースふたの挿入部に端子を固定するための部品を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device comprising a component for fixing a terminal to the insertion portion of the case lid.
前記ケースふたに端子を固定するための挿入部があって、その挿入部が固定する部分と樹脂埋めをする部分の大きさが違うケースふたを有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device comprising: an insertion portion for fixing a terminal to the case lid, and a case lid having a size different from a portion where the insertion portion is fixed and a portion where resin is buried.
前記ベースの一方の面に基板下はんだを介して搭載される基板と、
前記基板の前記ベースとは反対側の面にチップ下はんだを介して搭載されるチップと、
ワイヤを介して前記チップと電気的に接続されると共に前記基板の前記チップが搭載される面と同じ面に形成される回路と、
端子接続部を介して前記回路と電気的に接続される端子と
を備えたパワー半導体装置であって、
前記端子を収容しつつ、前記パワー半導体装置が前記端子を介して前記パワー半導体装置外部の装置と電気的に接続できるよう、前記端子の先端の一部を露出させるよう構成されたケースふたを更に備え、
前記端子は、前記回路と前記端子とをメタルボンディング接続するために超音波を与える部分であり、かつ、前記パワー半導体装置の外部から目視可能に構成された端子接続部を有する
ことを特徴とするパワー半導体装置。 Base and
A substrate mounted on one surface of the base via solder under the substrate;
A chip mounted on the surface of the substrate opposite to the base via a solder under the chip;
A circuit that is electrically connected to the chip via a wire and formed on the same surface of the substrate on which the chip is mounted;
A power semiconductor device comprising a terminal electrically connected to the circuit via a terminal connection portion,
A case lid configured to expose a part of the tip of the terminal so that the power semiconductor device can be electrically connected to a device outside the power semiconductor device via the terminal while accommodating the terminal. Prepared,
The terminal is a portion for applying an ultrasonic wave for metal bonding connection between the circuit and the terminal, and has a terminal connection portion configured to be visible from the outside of the power semiconductor device. Power semiconductor device.
前記ケースふたは、前記端子を挿入するための、前記端子と同じ形状の凹凸部のある隙間部を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
The case lid has a gap portion with a concavo-convex portion having the same shape as the terminal for inserting the terminal.
前記隙間部は、前記端子を前記隙間部に挿入したときの前記端子と前記隙間部のへりとの間隔が０．５ｍｍ以下である
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 7,
The gap semiconductor device is characterized in that an interval between the terminal and the edge of the gap portion when the terminal is inserted into the gap portion is 0.5 mm or less.
前記ケースふたは、前記端子を挿入するための、前記端子と異なる形状の凹凸部のある隙間部を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
The case lid has a gap portion with a concavo-convex portion having a shape different from that of the terminal for inserting the terminal.
前記端子接続部は、前記パワー半導体装置を上から見た場合に、前記ケースふたより外側に位置している
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
The power semiconductor device, wherein the terminal connection portion is located outside the case lid when the power semiconductor device is viewed from above.
前記端子接続部は、前記パワー半導体装置を上から見た場合に、前記ケースふたより内側に位置し、前記ケースふたは中央に穴を有する
ことを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
The power semiconductor device is characterized in that the terminal connecting portion is located inside the case lid when the power semiconductor device is viewed from above, and the case lid has a hole in the center.
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