JP2015082598A - Semiconductor substrate and semiconductor substrate manufacturing method - Google Patents
Semiconductor substrate and semiconductor substrate manufacturing method Download PDFInfo
- Publication number
- JP2015082598A JP2015082598A JP2013220265A JP2013220265A JP2015082598A JP 2015082598 A JP2015082598 A JP 2015082598A JP 2013220265 A JP2013220265 A JP 2013220265A JP 2013220265 A JP2013220265 A JP 2013220265A JP 2015082598 A JP2015082598 A JP 2015082598A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- hole
- layer
- electroless plating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
Abstract
Description
本発明は、３次元実装デバイスチップに用いられる半導体基板、及び、その製造方法に関する。 The present invention relates to a semiconductor substrate used for a three-dimensional mounting device chip and a manufacturing method thereof.
３次元実装による電子デバイスチップの搭載は、ＬＳＩ配線の小型化などを目的に、エレクトロニクス分野で広く利用されている。これまでの３次元実装は、ワイヤボンディングにより行われていたが、電子部品の小型化に対応すべく、ワイヤボンディングの配線スペースを無くし、より短い配線で電子デバイスチップを３次元実装する方法が検討されている。このような方法の一つとして、電子デバイスチップの半導体基板に、半導体基板を貫通する縦配線となる電極を形成し、該電極により、積層した電子デバイスチップどうしを接続する方法がある。 The mounting of electronic device chips by three-dimensional mounting is widely used in the electronics field for the purpose of miniaturizing LSI wiring. Previously, 3D mounting was performed by wire bonding, but in order to respond to the miniaturization of electronic components, a method for 3D mounting of electronic device chips with shorter wiring was investigated to eliminate the wiring space for wire bonding. Has been. As one of such methods, there is a method in which an electrode serving as a vertical wiring penetrating the semiconductor substrate is formed on the semiconductor substrate of the electronic device chip, and the stacked electronic device chips are connected by the electrode.
このような電極の形成方法として、次のような方法が知られている。まず、半導体基板の一方の面に、有底の盲穴からなるビアホールを形成し、次いで、ビアホールの内壁面を無機絶縁膜で被覆し、次いで、盲穴内に導電体を充填し、次いで、半導体基板の他方の面を研削して導電体を他方の面から露出させ、半導体基板を貫通する電極を形成する方法がある。 As a method for forming such an electrode, the following method is known. First, a via hole composed of a bottomed blind hole is formed on one surface of a semiconductor substrate, then the inner wall surface of the via hole is covered with an inorganic insulating film, and then the conductor is filled in the blind hole, and then the semiconductor There is a method of forming an electrode penetrating the semiconductor substrate by grinding the other surface of the substrate to expose the conductor from the other surface.
特許文献１には、半導体基板の上面に盲穴からなるビアホールを形成する工程と、ビアホールの内壁面を被覆する無機絶縁膜を形成する工程と、無機絶縁膜の表面に脱水縮合により一端が結合され、他端にメルカプト基又は含硫黄芳香族複素環式基を有するカップリング剤からなるカップリング層を形成する工程と、メルカプト基又は前記含硫黄芳香族複素環式基に触媒金属を結合させた後、触媒金属を活性化する工程と、無電解めっきを用いて、活性化された触媒金属上に金属薄膜からなるシード層を形成する工程と、シード層を一方の電極とする電解めっきを用いて、シード層上に前記ビアホールを埋め込む電解めっき金属からなるビアを形成する工程と、半導体基板の下面を前記ビアが表出するまで研削して、半導体基板を貫通する前記ビアを形成する工程と、を有する半導体装置の製造方法が開示されている。 Patent Document 1 includes a step of forming a via hole made of a blind hole on the upper surface of a semiconductor substrate, a step of forming an inorganic insulating film covering the inner wall surface of the via hole, and one end bonded to the surface of the inorganic insulating film by dehydration condensation. A step of forming a coupling layer comprising a coupling agent having a mercapto group or a sulfur-containing aromatic heterocyclic group at the other end, and binding a catalytic metal to the mercapto group or the sulfur-containing aromatic heterocyclic group. Then, a step of activating the catalytic metal, a step of forming a seed layer made of a metal thin film on the activated catalytic metal using electroless plating, and an electrolytic plating using the seed layer as one electrode. A step of forming a via made of electroplated metal that embeds the via hole on the seed layer, and before the semiconductor substrate is penetrated by grinding the lower surface of the semiconductor substrate until the via is exposed. A method of manufacturing a semiconductor device having a step of forming a via, is disclosed.
しかしながら、この方法の場合、半導体基板の盲穴が形成された面とは反対側の面を研削加工する必要がある。かかる研削加工は技術的に難しいため、生産性が低下したり、量産時の品質に大きく影響する傾向にあった。また、特許文献１では、半導体基板とカップリング層との密着性を、化学的結合により確保しているが、密着性は十分とは言えなかった。また、カップリング層を形成する工程が必要となるので、工数が増え、生産性が低下し易かった。 However, in this method, it is necessary to grind the surface of the semiconductor substrate opposite to the surface where the blind holes are formed. Since such grinding is technically difficult, the productivity tends to decrease or the quality during mass production tends to be greatly affected. Moreover, in patent document 1, although the adhesiveness of a semiconductor substrate and a coupling layer is ensured by the chemical bond, it cannot be said that adhesiveness is enough. Moreover, since a process for forming a coupling layer is required, the number of man-hours is increased, and the productivity is easily lowered.
また、半導体基板を貫通する電極の他の形成方法として、次の方法がある。まず。半導体基板に貫通孔を形成し、次いで、スパッタを行って貫通孔内壁にスパッタ層を形成し、次いで、スパッタ層をシード層として電解めっきを行って貫通孔内を電解めっき層で埋め込んで、半導体基板を貫通する電極を形成する方法がある。 Another method for forming an electrode penetrating the semiconductor substrate is as follows. First. A through-hole is formed in a semiconductor substrate, and then sputtering is performed to form a sputter layer on the inner wall of the through-hole. Next, electrolytic plating is performed using the sputter layer as a seed layer, and the inside of the through-hole is filled with an electrolytic plating layer. There is a method of forming an electrode penetrating the substrate.
特許文献２には、半導体基板の一表面側にＣＶＤ法やスパッタリング法により第１の金属層を形成する第１の金属層形成工程と、第１の金属層をシード層として電解めっき法により貫通孔の内側を埋め込む貫通配線材料からなる第１の金属部を半導体基板の厚み方向の途中まで析出させる第１の電解めっき工程と、第１の電解めっき工程の後で半導体基板の他表面側および貫通孔の内側で露出している部位の表面と貫通孔の内側で露出している第１の金属部の表面とに跨ってＣＶＤ法やスパッタリング法により第２の金属層を形成する第２の金属層形成工程と、第２の金属層をシード層として電解めっき法により貫通孔の内側の充足されていない空間を埋め込むように貫通配線材料からなる第２の金属部を析出させる第２の電解めっき工程とを備える半導体基板への貫通配線の形成方法が開示されている。 In Patent Document 2, a first metal layer forming step for forming a first metal layer on one surface side of a semiconductor substrate by a CVD method or a sputtering method, and a first metal layer as a seed layer are penetrated by an electrolytic plating method. A first electrolytic plating step of depositing a first metal portion made of a through wiring material filling the inside of the hole partway along a thickness direction of the semiconductor substrate; and the other surface side of the semiconductor substrate after the first electrolytic plating step; A second metal layer is formed by a CVD method or a sputtering method across the surface of the portion exposed inside the through hole and the surface of the first metal portion exposed inside the through hole. And a second electrolysis for depositing a second metal portion made of a through-wiring material so as to embed an unfilled space inside the through hole by electrolytic plating using the second metal layer as a seed layer. With plating process Method for forming a through-wiring to the semiconductor substrate provided is disclosed.
しかしながら、この方法の場合、半導体基板の厚みが厚くなり、貫通孔が深さ方向に長くなると、貫通孔内壁をＣＶＤ法やスパッタリング法により金属層で完全に被覆することが困難となる。その結果、その後の電解めっきの工程で形成される電解めっき層の内部にボイドが発生し易くなり、貫通孔内を電解めっき層で隙間なく埋め込むことが困難となる傾向にあった。 However, in the case of this method, when the thickness of the semiconductor substrate is increased and the through hole is elongated in the depth direction, it is difficult to completely cover the inner wall of the through hole with a metal layer by a CVD method or a sputtering method. As a result, voids are likely to be generated inside the electrolytic plating layer formed in the subsequent electrolytic plating process, and it tends to be difficult to fill the through holes with no gap in the electrolytic plating layer.
本発明の目的は、半導体基板を貫通する縦配線となる電極が密着性よく形成された半導体基板、及び、その製造方法を提供することにある。 An object of the present invention is to provide a semiconductor substrate in which electrodes serving as vertical wirings penetrating the semiconductor substrate are formed with good adhesion, and a method for manufacturing the same.
本発明の半導体基板は、３次元実装デバイスチップに用いられる半導体基板であって、前記半導体基板に形成された、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔と、前記半導体基板の両面及び前記貫通孔内壁を被覆する無機絶縁膜と、前記無機絶縁膜上であって、前記半導体基板の両面及び前記貫通孔内壁の少なくとも前記半導体基板の厚さ方向の途中まで形成されたスパッタ層と、前記スパッタ層及び前記無機絶縁膜の上から、少なくとも前記貫通孔内壁を被覆するように形成された無電解めっき層と、前記無電解めっき層上に、前記貫通孔内を埋め込むように形成された電解めっき層とを備えることを特徴とする。 The semiconductor substrate of the present invention is a semiconductor substrate used for a three-dimensional mounting device chip, and is formed in the semiconductor substrate, gradually reducing the diameter from the openings on both sides and extending to the inside to communicate with each other. A through hole having an inner diameter that is the most reduced in the middle, an inorganic insulating film that covers both surfaces of the semiconductor substrate and the inner wall of the through hole, and both surfaces of the semiconductor substrate and the inner wall of the through hole on the inorganic insulating film A sputtering layer formed at least halfway in the thickness direction of the semiconductor substrate, and an electroless plating layer formed so as to cover at least the inner wall of the through hole from above the sputtering layer and the inorganic insulating film, An electroplating layer formed on the electroless plating layer so as to embed the inside of the through hole is provided.
本発明の半導体基板において、前記半導体基板の厚みが２５０μｍ以上であり、前記貫通孔の最大内径が６０〜２５０μｍであることが好ましい。 In the semiconductor substrate of the present invention, it is preferable that the thickness of the semiconductor substrate is 250 μm or more, and the maximum inner diameter of the through hole is 60 to 250 μm.
本発明の半導体基板において、前記スパッタ層は、Ｃｕ、Ｎｉ、Ｔｉ、Ａｌ、Ａｇ及びＡｕから選ばれる元素を１種類以上含む金属層で構成されていることが好ましい。 In the semiconductor substrate of the present invention, the sputter layer is preferably composed of a metal layer containing one or more elements selected from Cu, Ni, Ti, Al, Ag, and Au.
本発明の半導体基板において、前記スパッタ層は、単層膜、又は、２層以上の積層膜であることが好ましい。 In the semiconductor substrate of the present invention, the sputter layer is preferably a single layer film or a laminated film of two or more layers.
本発明の半導体基板において、前記無電解めっき層は、Ｃｕ、Ｎｉ、Ａｌ、Ｓｎ、Ａｇ及びＡｕから選ばれる元素を１種類以上含む金属層で構成されていることが好ましい。 In the semiconductor substrate of the present invention, the electroless plating layer is preferably composed of a metal layer containing one or more elements selected from Cu, Ni, Al, Sn, Ag, and Au.
本発明の半導体基板において、前記半導体基板がＳｉ基板であり、前記無機絶縁膜がＳｉＯ２膜であることが好ましい。 In the semiconductor substrate of the present invention, it is preferable that the semiconductor substrate is a Si substrate and the inorganic insulating film is a SiO 2 film.
また、本発明の半導体基板の製造方法は、３次元実装デバイスチップに用いられる半導体基板の製造方法であって、半導体基板の両面から孔開け加工を行って、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔を形成する貫通孔形成工程と、前記半導体基板の両面及び前記貫通孔内壁に無機絶縁膜を形成する絶縁膜形成工程と、前記半導体基板の両面からスパッタを行い、前記半導体基板の両面及び前記貫通孔内壁の少なくとも前記半導体基板の厚さ方向の途中まで、スパッタ層を形成するスパッタ工程と、無電解めっき処理を行って、前記スパッタ層及び前記無機絶縁膜の上から、少なくとも前記貫通孔内壁を被覆するように無電解めっき層を形成する無電解めっき工程と、前記スパッタ層及び前記無電解めっき層をシード層として、電解めっき処理を行って、前記貫通孔内を電解めっき層で埋め込む電解めっき工程とを含むことを特徴とする。 The method for manufacturing a semiconductor substrate of the present invention is a method for manufacturing a semiconductor substrate used for a three-dimensional mounting device chip, wherein holes are drilled from both sides of the semiconductor substrate and the diameter is gradually reduced from the openings on both sides. A through-hole forming step for forming a through-hole having an inner diameter that is extended and communicated with the inside and having the smallest diameter in the middle of the thickness direction, and insulation for forming an inorganic insulating film on both surfaces of the semiconductor substrate and the inner wall of the through-hole A film forming step, a sputtering step of performing sputtering from both sides of the semiconductor substrate, and forming a sputter layer at least halfway in the thickness direction of the semiconductor substrate on both sides of the semiconductor substrate and the inner wall of the through hole, and electroless plating An electroless plating step of forming an electroless plating layer on the sputter layer and the inorganic insulating film so as to cover at least the inner wall of the through hole; As jitter layer and the seed layer using the electroless plating layer by performing electrolytic plating process, characterized in that it comprises an electrolytic plating step of filling the through hole by electrolytic plating layer.
本発明の半導体基板の製造方法において、前記半導体基板の厚みが２５０μｍ以上であり、前記貫通孔の最大内径が６０〜２５０μｍであることが好ましい。 In the semiconductor substrate manufacturing method of the present invention, it is preferable that the thickness of the semiconductor substrate is 250 μm or more, and the maximum inner diameter of the through hole is 60 to 250 μm.
本発明の半導体基板の製造方法において、前記半導体基板としてＳｉ基板を用い、前記絶縁膜形成工程において、熱酸化処理を行って、前記無機絶縁膜としてＳｉＯ２膜を形成することが好ましい。 In the method for manufacturing a semiconductor substrate of the present invention, it is preferable that a Si substrate is used as the semiconductor substrate, and a thermal oxidation process is performed in the insulating film forming step to form a SiO 2 film as the inorganic insulating film.
本発明の半導体基板の製造方法において、前記無電解めっき工程は、脱脂工程と、エッチング工程と、触媒付与工程と、無電解めっき液による無電解めっき層を析出させる工程とを含み、前記エッチング工程を、アルカリ系水溶液で、５〜３０秒処理して行うことが好ましい。 In the method for manufacturing a semiconductor substrate of the present invention, the electroless plating step includes a degreasing step, an etching step, a catalyst application step, and a step of depositing an electroless plating layer with an electroless plating solution, and the etching step Is preferably carried out by treating with an alkaline aqueous solution for 5 to 30 seconds.
本発明の半導体基板によれば、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔を有するので、スパッタ層を孔の内部に形成しやすくなる。また、スパッタ層上に無電解めっき層を形成することにより、貫通孔内壁の一部にスパッタ層が形成されずに無機絶縁膜が露出している部分が存在していても、無電解めっき層によって完全に覆うことができ、このスパッタ層及び無電解めっき層をシード層にして電解めっきすることにより、貫通孔全体にボイドなく充填された電解めっき層を形成することができる。
そして、貫通孔を埋設する電解めっき層は、貫通孔内部の縮径した部分によってくさび効果が得られるため、電解めっき層と半導体基板との熱応力差等の要因により、半導体基板に応力が生じても、電解めっき層が貫通孔から抜け落ち難く、電解めっき層を貫通孔内にしっかりと保持できる。
According to the semiconductor substrate of the present invention, since it has a through-hole having an inner diameter which is gradually reduced in diameter from the openings on both sides and extends into and communicates with the inner diameter that is most reduced in the thickness direction, the sputter layer is formed in the hole. Easy to form inside. In addition, by forming an electroless plating layer on the sputter layer, the electroless plating layer can be formed even if there is a portion where the sputter layer is not formed on the inner wall of the through hole and the inorganic insulating film is exposed. The electroplating layer in which the entire through hole is filled without voids can be formed by electroplating using the sputter layer and the electroless plating layer as a seed layer.
In addition, the electrolytic plating layer in which the through hole is embedded has a wedge effect due to the reduced diameter inside the through hole, so that stress is generated in the semiconductor substrate due to factors such as a difference in thermal stress between the electrolytic plating layer and the semiconductor substrate. However, the electrolytic plating layer does not easily fall out of the through hole, and the electrolytic plating layer can be securely held in the through hole.
また、本発明の半導体基板の製造方法によれば、厚さ方向の途中で最も縮径した内径を有する貫通孔及び無機絶縁膜を形成した半導体基板に対し、半導体基板の両面からスパッタを行うので、半導体基板の両面及び貫通孔内壁の少なくとも半導体基板の厚さ方向の途中まで、平滑度が高い表面においても優れた密着性を有するスパッタ層を形成できる。
そして、スパッタ層を形成したのち、無電解めっき処理を行うので、貫通孔内壁の一部にスパッタ層が形成されずに無機絶縁膜が露出している部分が存在していても、無電解めっき層によって完全に覆うことができる。また、貫通孔内壁は、貫通孔の形成加工により粗面化されているので、アンカー効果によって無電解めっき層を貫通孔内壁の無機絶縁膜上に密着性よく形成できる。更に、スパッタ層上には、無電解めっき層を密着性よく形成することができる。
そして、スパッタ層及び無電解めっき層をシード層にして電解めっきすることにより、貫通孔内壁に電解めっき層を形成していくと、貫通孔の内部の最も縮径した部分でめっき層がつながって孔が塞がり、後は、孔を埋めるようにめっき層が形成されて、貫通孔全体にボイドなく充填された電解めっき層を形成することができる。
Further, according to the method for manufacturing a semiconductor substrate of the present invention, sputtering is performed from both sides of the semiconductor substrate on the semiconductor substrate on which the through hole having the inner diameter that is the most reduced in the thickness direction and the inorganic insulating film are formed. A sputtered layer having excellent adhesion can be formed on both surfaces of the semiconductor substrate and the inner wall of the through hole at least halfway in the thickness direction of the semiconductor substrate even on the surface having high smoothness.
Then, since the electroless plating process is performed after the sputter layer is formed, the electroless plating is performed even if the sputter layer is not formed on the inner wall of the through hole and the inorganic insulating film is exposed. Can be completely covered by layers. In addition, since the inner wall of the through hole is roughened by forming the through hole, the electroless plating layer can be formed on the inorganic insulating film on the inner wall of the through hole with good adhesion by the anchor effect. Furthermore, an electroless plating layer can be formed with good adhesion on the sputtered layer.
Then, when the electroplating layer is formed on the inner wall of the through hole by electroplating using the sputter layer and the electroless plating layer as a seed layer, the plating layer is connected at the most reduced diameter inside the through hole. After the hole is closed, a plating layer is formed so as to fill the hole, and an electrolytic plating layer filled without voids in the entire through hole can be formed.
本発明の半導体基板は、デバイスチップを積層して３次元実装する、３次元実装デバイスチップに用いられるものである。図１を用いて本発明の半導体基板について説明する。 The semiconductor substrate of the present invention is used for a three-dimensional mounting device chip in which device chips are stacked and three-dimensionally mounted. The semiconductor substrate of the present invention will be described with reference to FIG.
図１に示されるように、半導体基板１には、両面の開口部１０ａから次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径Ｌ３を有する貫通孔１０が形成されている。 As shown in FIG. 1, the semiconductor substrate 1 has a through hole 10 having an inner diameter L <b> 3 that is gradually reduced in diameter from the openings 10 a on both sides and that extends to and communicates with the inside, and that has the smallest diameter L3 in the thickness direction. Is formed.
半導体基板１の材質としては、特に限定は無い。例えば、Ｓｉ基板、ＳｉＣ基板、ＳｉＯ２基板、ＧａＮ基板、ＡｌＮ基板、ダイヤモンド基板等が挙げられる。 The material for the semiconductor substrate 1 is not particularly limited. Examples thereof include a Si substrate, a SiC substrate, a SiO 2 substrate, a GaN substrate, an AlN substrate, and a diamond substrate.
半導体基板１の厚み、すなわち、貫通孔１０の半導体基板１の厚み方向の長さＬ１は、２５０μｍ以上が好ましく、２５０〜７００μｍがより好ましく、２５０〜４５０μｍが特に好ましい。本発明では、貫通孔のＬ１が２５０μｍ以上であっても貫通孔１０の内壁に無電解めっき層を密着性よく形成できる。 The thickness of the semiconductor substrate 1, that is, the length L1 of the through hole 10 in the thickness direction of the semiconductor substrate 1 is preferably 250 μm or more, more preferably 250 to 700 μm, and particularly preferably 250 to 450 μm. In the present invention, the electroless plating layer can be formed on the inner wall of the through-hole 10 with good adhesion even if the through-hole L1 is 250 μm or more.
半導体基板１両面の開口部１０ａ、すなわち、貫通孔１０の最大内径Ｌ２は、６０〜２５０μｍが好ましく、８０〜１５０μｍがより好ましい。貫通孔のＬ２が６０μｍ未満であると、太鼓型の貫通孔形成が困難になる傾向にあり、２５０μｍを超えるとめっき層で埋め込む際にボイドの形成が出来易くなる傾向にある。 The opening 10a on both sides of the semiconductor substrate 1, that is, the maximum inner diameter L2 of the through hole 10 is preferably 60 to 250 μm, and more preferably 80 to 150 μm. If the L2 of the through hole is less than 60 μm, the formation of a drum-shaped through hole tends to be difficult, and if it exceeds 250 μm, the void tends to be easily formed when embedded with a plating layer.
貫通孔１０の最小内径Ｌ３は、好ましくは５５〜２４５μｍの範囲、より好ましくは７５〜１４５μｍの範囲で、最大内径Ｌ２よりも短いことが好ましい。貫通孔１０のＬ３が、５０μｍ未満であると、最大内径Ｌ２に対し、加工困難な範囲となる傾向にあり、２４５μｍを超えると、貫通孔１０内を後述する電解めっき層で埋め込むのに時間を要する傾向にあり、生産性が低下することがある。 The minimum inner diameter L3 of the through hole 10 is preferably in the range of 55 to 245 μm, more preferably in the range of 75 to 145 μm, and is preferably shorter than the maximum inner diameter L2. If the L3 of the through hole 10 is less than 50 μm, the maximum inner diameter L2 tends to be difficult to work. If it exceeds 245 μm, it takes time to fill the inside of the through hole 10 with an electroplating layer to be described later. It tends to be necessary, and productivity may be reduced.
貫通孔１０の表面粗さＲａは、０．１μｍ以上が好ましく、１．０〜５．０μｍがより好ましい。貫通孔１０の表面粗さＲａが０．１μｍ以上であれば、貫通孔内壁の一部にスパッタ層が形成されずに無機絶縁膜が露出している部分が存在していても、無電解めっき層で貫通孔内壁を密着性よく被覆できる。 The surface roughness Ra of the through hole 10 is preferably 0.1 μm or more, and more preferably 1.0 to 5.0 μm. If the surface roughness Ra of the through hole 10 is 0.1 μm or more, the electroless plating is performed even if the sputter layer is not formed on the inner wall of the through hole and the inorganic insulating film is exposed. The inner wall of the through hole can be coated with a layer with good adhesion.
半導体基板１の両面及び貫通孔１０内壁は、ＳｉＯ２、Ａｌ２Ｏ３等の無機絶縁膜２０で被覆されている。 Both surfaces of the semiconductor substrate 1 and the inner walls of the through holes 10 are covered with an inorganic insulating film 20 such as SiO 2 or Al 2 O 3 .
無機絶縁膜２０の膜厚は１．０μｍ以上が好ましく、２．０〜５．０μｍがより好ましい。無機絶縁膜２０の膜厚が１．０μｍ未満であると、絶縁性を確保することが困難となる傾向にある。 The thickness of the inorganic insulating film 20 is preferably 1.0 μm or more, and more preferably 2.0 to 5.0 μm. When the thickness of the inorganic insulating film 20 is less than 1.0 μm, it tends to be difficult to ensure insulation.
無機絶縁膜２０上であって、半導体基板１の両面、及び、貫通孔１０内壁には、Ｃｕ、Ｎｉ、Ｔｉ、Ａｌ、Ａｇ及びＡｕから選ばれる元素を１種類以上含む金属層で構成されたスパッタ層３０が形成されている。スパッタ層３０は、単層膜であってもよいし、２層以上の積層膜であってもよい。 On the inorganic insulating film 20, the both surfaces of the semiconductor substrate 1 and the inner wall of the through hole 10 are composed of a metal layer containing one or more elements selected from Cu, Ni, Ti, Al, Ag, and Au. A sputter layer 30 is formed. The sputter layer 30 may be a single layer film or a laminated film of two or more layers.
スパッタ層３０の膜厚は、０．０１〜１．０μｍが好ましく、０．０５〜０．２μｍがより好ましい。スパッタ層３０の膜厚が０．０１μｍ未満であると、後述する無電解めっき層４０との密着性が不足する傾向にある。スパッタ層３０の膜厚が大きくなると、成膜に時間を要し、生産性が低下するので、上限は１．０μｍが好ましい。 The film thickness of the sputter layer 30 is preferably 0.01 to 1.0 μm, and more preferably 0.05 to 0.2 μm. When the film thickness of the sputter layer 30 is less than 0.01 μm, the adhesion with the electroless plating layer 40 described later tends to be insufficient. When the film thickness of the sputter layer 30 is increased, it takes time to form the film and the productivity is lowered. Therefore, the upper limit is preferably 1.0 μm.
なお、図１では、貫通孔１０内壁には、半導体基板１の厚さ方向の少なくとも途中までスパッタ層３０が形成されている。貫通孔１０内壁の全体がスパッタ層３０で完全に被覆されていることが好ましいが、スパッタ層３０が形成されていない部分があってもよい。貫通孔１０のＬ１が大きくなるに伴い、貫通孔１０内壁にスパッタ層３０が形成され難くなる。特に、貫通孔１０のＬ１が２５０μｍを超えると、貫通孔１０内壁をスパッタ層３０で完全に被覆することが困難となる。 In FIG. 1, a sputter layer 30 is formed on the inner wall of the through hole 10 at least partway in the thickness direction of the semiconductor substrate 1. The entire inner wall of the through hole 10 is preferably completely covered with the sputter layer 30, but there may be a portion where the sputter layer 30 is not formed. As L1 of the through hole 10 increases, it becomes difficult to form the sputter layer 30 on the inner wall of the through hole 10. In particular, when L1 of the through hole 10 exceeds 250 μm, it becomes difficult to completely cover the inner wall of the through hole 10 with the sputter layer 30.
貫通孔１０内壁の、スパッタ層３０の表面及び無機絶縁膜２０が露出した表面には、Ｃｕ、Ｎｉ、Ａｌ、Ｓｎ、Ａｇ及びＡｕから選ばれる元素を１種類以上含む金属層で構成された無電解めっき層４０が形成されており、貫通孔１０内壁の全面が無電解めっき層４０で被覆されている。また、半導体基板１の両面のスパッタ層３０上にも無電解めっき層４０が形成されている。 On the inner wall of the through hole 10, the surface of the sputtered layer 30 and the exposed surface of the inorganic insulating film 20 are made of a metal layer containing one or more elements selected from Cu, Ni, Al, Sn, Ag, and Au. An electrolytic plating layer 40 is formed, and the entire inner wall of the through hole 10 is covered with the electroless plating layer 40. An electroless plating layer 40 is also formed on the sputtered layers 30 on both sides of the semiconductor substrate 1.
無電解めっき層４０の膜厚は、０．１〜１０．０μｍが好ましく、１．０〜５．０μｍがより好ましい。無電解めっき層４０の膜厚が０．１μｍ未満であると、めっき未付着部が発生する傾向にある。無電解めっき層４０の膜厚が１０．０μｍを超えるとめっき残留応力が大きくなり、密着不良となる傾向にある。 The film thickness of the electroless plating layer 40 is preferably 0.1 to 10.0 μm, and more preferably 1.0 to 5.0 μm. When the film thickness of the electroless plating layer 40 is less than 0.1 μm, a plating non-adhered portion tends to occur. If the film thickness of the electroless plating layer 40 exceeds 10.0 μm, the plating residual stress tends to increase, resulting in poor adhesion.
貫通孔１０内壁の、無電解めっき層４０上には、Ｃｕ、Ｎｉ、Ａｌ、Ｓｎ、Ａｇ及びＡｕから選ばれる元素を１種類以上含む金属層で構成された電解めっき層５０が形成されており、貫通孔１０内が電解めっき層５０で埋め込められている。また、半導体基板１の両面の無電解めっき層４０上にも電解めっき層５０が形成されている。なお、半導体基板１の両面に形成された、スパッタ層３０、無電解めっき層４０及び電解めっき層５０からなる金属層は、所望のパターンとなるようにエッチングされて、パターン電極となる。 On the electroless plating layer 40 on the inner wall of the through hole 10, an electrolytic plating layer 50 composed of a metal layer containing one or more elements selected from Cu, Ni, Al, Sn, Ag and Au is formed. The inside of the through hole 10 is embedded with the electrolytic plating layer 50. Electrolytic plating layers 50 are also formed on the electroless plating layers 40 on both sides of the semiconductor substrate 1. In addition, the metal layer which consists of the sputter | spatter layer 30, the electroless-plating layer 40, and the electroplating layer 50 formed on both surfaces of the semiconductor substrate 1 is etched so that it may become a desired pattern, and becomes a pattern electrode.
電解めっき層５０の膜厚は、貫通孔１０のサイズにより異なるが、例えば、貫通孔の最大内径Ｌ２が６０〜２５０μｍである場合は、３０〜２００μｍが好ましく、丁度貫通孔１０を埋めることを考えると、３０〜１２５μｍがより好ましい。 The thickness of the electrolytic plating layer 50 varies depending on the size of the through hole 10. For example, when the maximum inner diameter L2 of the through hole is 60 to 250 μm, 30 to 200 μm is preferable, and it is considered that the through hole 10 is just filled. And 30-125 micrometers is more preferable.
本発明の半導体基板１によれば、貫通孔１０を埋設する電解めっき層５０等の金属層に対して、貫通孔１０内部の縮径した部分によってくさび効果が得られるため、金属層と半導体基板１との熱膨張差等の要因により、両者の間で熱応力が生じても、金属層が貫通孔から抜け落ち難く、金属層を貫通孔１０内にしっかりと保持できる。 According to the semiconductor substrate 1 of the present invention, since the wedge effect is obtained by the reduced diameter portion inside the through hole 10 with respect to the metal layer such as the electrolytic plating layer 50 in which the through hole 10 is embedded, the metal layer and the semiconductor substrate Even if a thermal stress occurs between the two due to factors such as a difference in thermal expansion from 1, it is difficult for the metal layer to fall out of the through hole, and the metal layer can be securely held in the through hole 10.
次に、本発明の半導体基板の製造方法について説明する。 Next, the manufacturing method of the semiconductor substrate of this invention is demonstrated.
まず、図２（ａ）に示すように、半導体基板１の両面から孔開け加工を行って、両面の開口部１０ａから次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径Ｌ３を有する貫通孔１０を形成する。 First, as shown in FIG. 2 (a), holes are drilled from both sides of the semiconductor substrate 1, gradually reduced in diameter from the openings 10a on both sides, and extended to communicate with each other. A through hole 10 having a reduced inner diameter L3 is formed.
このような貫通孔は、例えば、半導体基板の両面に、貫通孔形成箇所に開口が設けられたマスクを形成し、半導体基板１の両面から従来公知の方法で異方性エッチングを行って形成する方法が挙げられる。 Such a through hole is formed, for example, by forming a mask having openings at the through hole forming portions on both surfaces of the semiconductor substrate and performing anisotropic etching from both surfaces of the semiconductor substrate 1 by a conventionally known method. A method is mentioned.
次に、図２（ｂ）に示すように、半導体基板１の両面及び貫通孔１０内壁に無機絶縁膜２０を形成する。無機絶縁膜２０の形成方法は特に限定は無い。熱酸化処理、オゾン酸化、プラズマ酸化、ラジカル酸化、陽極酸化等の方法で形成できる。例えば、半導体基板１がＳｉ基板の場合、酸素雰囲気下で９６０〜１１００℃で熱酸化処理を行うことで、半導体基板１の両面及び貫通孔１０内壁に、ＳｉＯ２膜からなる無機絶縁膜２０を形成できる。 Next, as shown in FIG. 2B, the inorganic insulating film 20 is formed on both surfaces of the semiconductor substrate 1 and the inner wall of the through hole 10. The formation method of the inorganic insulating film 20 is not particularly limited. It can be formed by a method such as thermal oxidation treatment, ozone oxidation, plasma oxidation, radical oxidation, or anodic oxidation. For example, when the semiconductor substrate 1 is a Si substrate, an inorganic insulating film 20 made of a SiO 2 film is formed on both surfaces of the semiconductor substrate 1 and the inner walls of the through holes 10 by performing a thermal oxidation process at 960 to 1100 ° C. in an oxygen atmosphere. Can be formed.
次に、図２（ｃ）に示すように、半導体基板１の両面からスパッタを行って、半導体基板１の両面及び貫通孔１０内壁の少なくとも半導体基板１の厚さ方向の途中まで、スパッタ層３０を形成する。スパッタ条件は、特に限定は無い。ターゲット材としては、Ｃｕ、Ｎｉ、Ａｌ、Ｓｎ、Ａｇ、Ａｕ及びこれらの合金が好ましく用いられる。スパッタは、片面ずつ交互に行っても良く、両面同時に行ってもよい。 Next, as shown in FIG. 2C, sputtering is performed from both sides of the semiconductor substrate 1, and at least halfway in the thickness direction of the semiconductor substrate 1 on both sides of the semiconductor substrate 1 and the inner wall of the through hole 10. Form. The sputtering conditions are not particularly limited. As the target material, Cu, Ni, Al, Sn, Ag, Au and alloys thereof are preferably used. Sputtering may be performed alternately on each side or simultaneously on both sides.
次に、図２（ｄ）に示すように、無電解めっき処理を行って、スパッタ層３０及び無機絶縁膜２０の上から、貫通孔１０内壁を被覆するように無電解めっき層４０を形成すると共に、半導体基板１の両面に形成されたスパッタ層３０上に無電解めっき層４０を形成する。 Next, as shown in FIG. 2D, an electroless plating process is performed to form an electroless plating layer 40 on the sputter layer 30 and the inorganic insulating film 20 so as to cover the inner wall of the through hole 10. At the same time, an electroless plating layer 40 is formed on the sputtered layer 30 formed on both surfaces of the semiconductor substrate 1.
無電解めっき処理は、従来公知の方法で行うことができる。例えば、脱脂工程と、エッチング工程と、触媒付与工程と、無電解めっき液による無電解めっき層を析出させる析出工程とを経て無電解めっき処理を行う方法が挙げられる。 The electroless plating treatment can be performed by a conventionally known method. For example, the method of performing an electroless-plating process through the degreasing process, the etching process, the catalyst provision process, and the precipitation process which deposits the electroless-plating layer by an electroless-plating liquid is mentioned.
上記脱脂工程では、表面の油脂成分などを除去するために、洗浄効果を有する脱脂洗浄液で処理する。脱脂洗浄液としては、例えば、塩酸、硫酸、りん酸、硝酸、水酸化ナトリウム、けい酸ナトリウム、りん酸ナトリウム、有機溶剤、界面活性剤等が挙げられる。処理条件は特に限定は無いが、例えば、２０〜８０℃の脱脂洗浄液に、０．１〜１０分間接触させて浸漬して処理する方法等が挙げられる。 In the degreasing step, the surface is treated with a degreasing cleaning liquid having a cleaning effect in order to remove oil components on the surface. Examples of the degreasing solution include hydrochloric acid, sulfuric acid, phosphoric acid, nitric acid, sodium hydroxide, sodium silicate, sodium phosphate, an organic solvent, and a surfactant. Although there are no particular limitations on the treatment conditions, for example, there may be mentioned a method of treating by immersing in a degreasing cleaning solution at 20 to 80 ° C. for 0.1 to 10 minutes.
上記エッチング工程では、シアン化ナトリウムやフッ化アンモン等のアルカリ系水溶液を、上記脱脂工程後の半導体基板１に接触させて、半導体基板１の表面を処理する。処理条件は、２０〜８０℃のアルカリ系水溶液に、５〜３０秒接触させて処理することが好ましい。処理時間が５秒未満であると、次工程での触媒の付着性が低下する傾向にある。処理時間が３０秒を超えると、貫通孔１０の内壁や半導体基板１の両面に形成されたスパッタ層３０が剥離する恐れがある。 In the etching process, the surface of the semiconductor substrate 1 is treated by bringing an alkaline aqueous solution such as sodium cyanide or ammonium fluoride into contact with the semiconductor substrate 1 after the degreasing process. It is preferable to process by making it contact for 5 to 30 seconds to 20-80 degreeC alkaline aqueous solution. If the treatment time is less than 5 seconds, the adhesion of the catalyst in the next step tends to decrease. When the processing time exceeds 30 seconds, the sputter layer 30 formed on the inner wall of the through hole 10 or both surfaces of the semiconductor substrate 1 may be peeled off.
上記触媒付与工程では、Ｐｄ、Ｐｔ、Ｒｕ、Ａｇ等の触媒を含む溶液を、上記エッチング工程後の半導体基板１に接触させて、半導体基板１の表面に触媒を吸着させる。処理条件は特に限定は無く、従来公知の方法で行うことができる。 In the catalyst application step, a solution containing a catalyst such as Pd, Pt, Ru, or Ag is brought into contact with the semiconductor substrate 1 after the etching step, and the catalyst is adsorbed on the surface of the semiconductor substrate 1. The treatment conditions are not particularly limited, and can be performed by a conventionally known method.
上記析出工程では、Ｃｕ、Ｎｉ、Ａｌ、Ｓｎ、Ａｇ及びＡｕから選ばれる元素を含む無電解めっき液を、上記触媒付与工程後の半導体基板１に接触させて、半導体基板１の表面に金属を析出させ、無電解めっき層を形成する。無電解めっき液には、上記元素の他に、Ｐ、Ｂ等のその他合金化可能な金属等を含んでいてもよい。析出条件は、特に限定ない。例えば、Ｎｉを８８〜９４質量％、Ｐを６〜１２質量％含有する無電解めっき液を用いて、無電解Ｎｉめっき層を形成する場合を例に挙げて説明すると、無電解めっき浴に、８０〜９５℃で、５〜２５分間浸漬して形成する方法が挙げられる。他の金属の場合においても同様にして形成できる。 In the deposition step, an electroless plating solution containing an element selected from Cu, Ni, Al, Sn, Ag and Au is brought into contact with the semiconductor substrate 1 after the catalyst application step, and a metal is deposited on the surface of the semiconductor substrate 1. Precipitate to form an electroless plating layer. The electroless plating solution may contain other alloyable metals such as P and B in addition to the above elements. The deposition conditions are not particularly limited. For example, the case where an electroless Ni plating layer is formed using an electroless plating solution containing 88 to 94% by mass of Ni and 6 to 12% by mass of P will be described as an example. The method of immersing and forming at 80-95 degreeC for 5 to 25 minutes is mentioned. In the case of other metals, they can be formed in the same manner.
次に、図２（ｅ）に示すように、スパッタ層３０及び無電解めっき層４０をシード層として、電解めっき処理を行って、貫通孔１０内を電解めっき層５０で埋め込むと共に、半導体基板１の両面にも電解めっき層５０を形成する。 Next, as shown in FIG. 2E, electrolytic plating is performed using the sputter layer 30 and the electroless plating layer 40 as a seed layer to fill the through hole 10 with the electrolytic plating layer 50, and the semiconductor substrate 1 The electrolytic plating layer 50 is also formed on both sides of the substrate.
電解めっき処理は、従来公知の方法で行うことができる。例えば、電解めっき層５０として、電解Ｃｕめっき層を形成する場合、シード層を酸等で洗浄し、硫酸銅を含有する溶液中で、銅をカソード電極として用いて、０．５〜１０．０Ａ／ｄｍ２の電流密度で電解銅めっきを行なうことで、貫通孔１０内を電解Ｃｕめっき層で埋め込むことができる。 The electrolytic plating treatment can be performed by a conventionally known method. For example, when an electrolytic Cu plating layer is formed as the electrolytic plating layer 50, the seed layer is washed with an acid or the like, and copper is used as a cathode electrode in a solution containing copper sulfate. By performing electrolytic copper plating at a current density of / dm 2, the inside of the through hole 10 can be embedded with an electrolytic Cu plating layer.
本発明によれば、貫通孔１０及び無機絶縁膜２０を形成した半導体基板１に対し、半導体基板１の両面からスパッタを行うので、半導体基板１の両面及び貫通孔１０内壁の少なくとも半導体基板の厚さ方向の途中まで、平滑度が高い表面においても優れた密着性を有するスパッタ層３０を形成できる。そして、スパッタ層３０を形成したのち、無電解めっき処理を行うので、半導体基板の両面には、スパッタ層３０上に無電解めっき層４０が形成され、貫通孔１０内壁には、スパッタ層３０上、もしくは、無機絶縁膜２０上に無電解めっき層４０が形成される。無電解めっき層４０は、スパッタ層３０上に密着性よく形成できる。また、貫通孔１０内壁は、貫通孔１０の形成加工により粗面化されているので、貫通孔１０内壁の一部が、スパッタ層が形成されずに無機絶縁膜２０が露出している部分が存在していても、アンカー効果によって、貫通孔１０内壁の無機絶縁膜２０上に無電解めっき層４０を密着性よく形成できる。そして、このように形成したスパッタ層３０及び無電解めっき層４０をシード層として、電解めっき処理を行うことで、貫通孔１０の内部の最も縮径した部分でめっき層がつながって孔が塞がり、後は、孔を埋めるようにめっき層が形成されて、貫通孔１０全体にボイドなく充填された電解めっき層５０を形成することができる。 According to the present invention, the semiconductor substrate 1 on which the through hole 10 and the inorganic insulating film 20 are formed is sputtered from both sides of the semiconductor substrate 1, so that at least the thickness of the semiconductor substrate on both sides of the semiconductor substrate 1 and the inner wall of the through hole 10. In the middle of the vertical direction, the sputtered layer 30 having excellent adhesion can be formed even on a surface having high smoothness. Since the electroless plating process is performed after the sputter layer 30 is formed, the electroless plating layer 40 is formed on the sputter layer 30 on both sides of the semiconductor substrate, and the sputter layer 30 is formed on the inner wall of the through hole 10. Alternatively, the electroless plating layer 40 is formed on the inorganic insulating film 20. The electroless plating layer 40 can be formed on the sputter layer 30 with good adhesion. In addition, since the inner wall of the through hole 10 is roughened by forming the through hole 10, a part of the inner wall of the through hole 10 is a portion where the sputter layer is not formed and the inorganic insulating film 20 is exposed. Even if it exists, the electroless plating layer 40 can be formed with good adhesion on the inorganic insulating film 20 on the inner wall of the through hole 10 by the anchor effect. And by performing the electrolytic plating process using the sputter layer 30 and the electroless plating layer 40 formed in this way as a seed layer, the plating layer is connected at the most reduced diameter portion inside the through hole 10 to close the hole, After that, a plating layer is formed so as to fill the hole, and the electrolytic plating layer 50 in which the entire through hole 10 is filled without voids can be formed.
厚さ３５０μｍのＳｉ基板の両面に、レジストを形成し、パターニングを行って、レジストの貫通孔形成箇所に開口を形成した。次に、エッチング液としてＫＯＨ溶液を用い、基板の両面から異方性エッチングを行って孔開け加工を行い、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔を形成した。貫通孔は、開口部の直径が１２０μｍであり、最も縮径した部分の直径が１１５μｍであった。孔開け加工を行ったのち、Ｓｉ基板の両面からレジストを除去した。 A resist was formed on both sides of a 350 μm thick Si substrate, and patterning was performed to form openings at positions where the through holes were formed in the resist. Next, using a KOH solution as an etchant, anisotropic etching is performed from both sides of the substrate to perform drilling, the diameter gradually decreases from the openings on both sides, and extends and communicates with each other. A through hole having an inner diameter that was the most reduced was formed. The diameter of the through hole of the through hole was 120 μm, and the diameter of the most contracted portion was 115 μm. After drilling, the resist was removed from both sides of the Si substrate.
次に、１０００℃で１０時間加熱処理を行い、半導体基板の両面及び貫通孔内壁に、ＳｉＯ２膜を形成した。 Next, heat treatment was performed at 1000 ° C. for 10 hours to form SiO 2 films on both surfaces of the semiconductor substrate and the inner walls of the through holes.
次に、ターゲットとしてＣｕを用い、半導体基板の一方の面に、出力０．６ｋＷ、時間７分、Ａｒガス流量２０ｓｃｃｍ、圧力０．８Ｐａの条件でスパッタを行い、次いで、他方の面にも、同条件でスパッタを行った。半導体基板の両面及び貫通孔内壁の開口部から深さ約１２５μｍまでは、スパッタ層が形成されていたが、貫通孔内部の約１００μｍはスパッタ層が形成されていなかった。 Next, using Cu as a target, sputtering was performed on one surface of the semiconductor substrate under the conditions of an output of 0.6 kW, a time of 7 minutes, an Ar gas flow rate of 20 sccm, and a pressure of 0.8 Pa. Sputtering was performed under the same conditions. A sputtered layer was formed from both sides of the semiconductor substrate and the opening of the inner wall of the through hole to a depth of about 125 μm, but a sputtered layer was not formed about 100 μm inside the through hole.
次に、無電解めっき処理を行って無電解めっき層を形成した。無電解めっき処理は、界面活性剤で脱脂を行い、次いで、フッ化アンモニウム水溶液を用いて５秒間エッチングを行い、次いで、３０℃のＳｎ置換の後、３０℃のＰｄ触媒溶液に２分間浸漬してＰｄを吸着させ、次いで、８５℃のＮｉ−Ｐ無電解浴に５分間浸漬して行った。貫通孔内壁は、無電解めっき層で被覆されていた。 Next, an electroless plating treatment was performed to form an electroless plating layer. In the electroless plating treatment, degreasing is performed using a surfactant, etching is performed for 5 seconds using an aqueous ammonium fluoride solution, and then immersion is performed for 2 minutes in a Pd catalyst solution at 30 ° C. after Sn substitution at 30 ° C. Pd was adsorbed, and then immersed in an Ni-P electroless bath at 85 ° C. for 5 minutes. The inner wall of the through hole was covered with an electroless plating layer.
次に、スパッタ層及び無電解めっき層をシード層として電解Ｃｕめっき処理を行い、貫通孔内を電解Ｃｕめっき層で埋め込むと共に、半導体基板の両面にも電解Ｃｕめっき層を形成した。電解Ｃｕめっき層は、半導体基板に対して密着性よく形成されていた。 Next, an electrolytic Cu plating process was performed using the sputtered layer and the electroless plating layer as a seed layer, the inside of the through hole was filled with the electrolytic Cu plating layer, and an electrolytic Cu plating layer was formed on both sides of the semiconductor substrate. The electrolytic Cu plating layer was formed with good adhesion to the semiconductor substrate.
１：半導体基板
１０：貫通孔
２０：無機絶縁膜
３０：スパッタ層
４０：無電解めっき層
５０：電解めっき層
1: Semiconductor substrate 10: Through hole 20: Inorganic insulating film 30: Sputtering layer 40: Electroless plating layer 50: Electrolytic plating layer
Claims (10)
前記半導体基板に形成された、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔と、
前記半導体基板の両面及び前記貫通孔内壁を被覆する無機絶縁膜と、
前記無機絶縁膜上であって、前記半導体基板の両面及び前記貫通孔内壁の少なくとも前記半導体基板の厚さ方向の途中まで形成されたスパッタ層と、
前記スパッタ層及び前記無機絶縁膜の上から、少なくとも前記貫通孔内壁を被覆するように形成された無電解めっき層と、
前記無電解めっき層上に、前記貫通孔内を埋め込むように形成された電解めっき層とを備えることを特徴とする半導体基板。 A semiconductor substrate used for a three-dimensional mounting device chip,
A through-hole formed in the semiconductor substrate, gradually reducing the diameter from the openings on both sides, extending into and communicating with the inside, and having an inner diameter that is most reduced in the middle of the thickness direction;
An inorganic insulating film covering both surfaces of the semiconductor substrate and the inner wall of the through hole;
On the inorganic insulating film, a sputter layer formed on both surfaces of the semiconductor substrate and at least part of the inner wall of the through hole in the thickness direction of the semiconductor substrate;
An electroless plating layer formed so as to cover at least the inner wall of the through hole from above the sputter layer and the inorganic insulating film;
A semiconductor substrate comprising: an electroplating layer formed on the electroless plating layer so as to be embedded in the through hole.
半導体基板の両面から孔開け加工を行って、両面の開口部から次第に縮径して内部に伸びて連通し、厚さ方向の途中で最も縮径した内径を有する貫通孔を形成する貫通孔形成工程と、
前記半導体基板の両面及び前記貫通孔内壁に無機絶縁膜を形成する絶縁膜形成工程と、
前記半導体基板の両面からスパッタを行い、前記半導体基板の両面及び前記貫通孔内壁の少なくとも前記半導体基板の厚さ方向の途中まで、スパッタ層を形成するスパッタ工程と、
無電解めっき処理を行って、前記スパッタ層及び前記無機絶縁膜の上から、少なくとも前記貫通孔内壁を被覆するように無電解めっき層を形成する無電解めっき工程と、
前記スパッタ層及び前記無電解めっき層をシード層として、電解めっき処理を行って、前記貫通孔内を電解めっき層で埋め込む電解めっき工程とを含むことを特徴とする半導体基板の製造方法。 A method of manufacturing a semiconductor substrate used for a three-dimensional mounting device chip,
A through hole is formed by drilling from both sides of a semiconductor substrate, gradually reducing the diameter from the openings on both sides, extending into and communicating with the inside, and forming a through hole having an inner diameter that is most reduced in the thickness direction. Process,
An insulating film forming step of forming an inorganic insulating film on both surfaces of the semiconductor substrate and the inner wall of the through hole;
Sputtering from both sides of the semiconductor substrate, forming a sputter layer to both sides of the semiconductor substrate and at least halfway through the inner wall of the through hole in the thickness direction of the semiconductor substrate;
Performing an electroless plating treatment, and forming an electroless plating layer on the sputter layer and the inorganic insulating film so as to cover at least the inner wall of the through hole; and
A method of manufacturing a semiconductor substrate, comprising: performing an electroplating process using the sputter layer and the electroless plating layer as a seed layer, and embedding the through hole with an electroplating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013220265A JP6213143B2 (en) | 2013-10-23 | 2013-10-23 | Semiconductor substrate and method for manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013220265A JP6213143B2 (en) | 2013-10-23 | 2013-10-23 | Semiconductor substrate and method for manufacturing semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015082598A true JP2015082598A (en) | 2015-04-27 |
| JP6213143B2 JP6213143B2 (en) | 2017-10-18 |
Family
ID=53013040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013220265A Active JP6213143B2 (en) | 2013-10-23 | 2013-10-23 | Semiconductor substrate and method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6213143B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016213253A (en) * | 2015-04-30 | 2016-12-15 | 大日本印刷株式会社 | Through electrode substrate and interposer using through electrode substrate and semiconductor device |
| JP2017077628A (en) * | 2015-10-19 | 2017-04-27 | セイコーエプソン株式会社 | Liquid ejection head and manufacturing method of liquid ejection head |
| JP2018107423A (en) * | 2016-12-27 | 2018-07-05 | 大日本印刷株式会社 | Perforated substrate, mounting substrate including perforated substrate, and manufacturing method of perforated substrate |
| JP2018125348A (en) * | 2017-01-30 | 2018-08-09 | 大日本印刷株式会社 | Through-electrode substrate, method for manufacturing the same, and semiconductor device |
| JP2018160697A (en) * | 2018-07-06 | 2018-10-11 | 大日本印刷株式会社 | Through electrode substrate |
| JP2019004085A (en) * | 2017-06-16 | 2019-01-10 | 大日本印刷株式会社 | Through electrode board, through electrode board equipped-mounting board, and manufacturing method of through electrode board |
| JP2020109207A (en) * | 2020-02-25 | 2020-07-16 | 大日本印刷株式会社 | Method for manufacturing through electrode substrate |
| CN112106187A (en) * | 2018-05-25 | 2020-12-18 | 凸版印刷株式会社 | Glass circuit board and method for manufacturing same |
| CN112260055A (en) * | 2019-07-02 | 2021-01-22 | 株式会社日立电力解决方案 | Double-sided mounting substrate, method for manufacturing double-sided mounting substrate, and semiconductor laser |
| US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| JP2022009249A (en) * | 2017-06-16 | 2022-01-14 | 大日本印刷株式会社 | Through electrode substrate, mounting substrate including through electrode substrate, and manufacturing method of through electrode substrate |
| US11760682B2 (en) | 2019-02-21 | 2023-09-19 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510655A (en) * | 1990-11-26 | 1996-04-23 | The Boeing Company | Silicon wafers containing conductive feedthroughs |
| JPH11120554A (en) * | 1997-10-14 | 1999-04-30 | Mitsubishi Chemical Corp | Production of substrate for magnetic recording medium |
| JP2001044197A (en) * | 1999-08-04 | 2001-02-16 | Sharp Corp | Semiconductor device and manufacture thereof |
| JP2001085434A (en) * | 1999-09-14 | 2001-03-30 | Hitachi Ltd | Method for plating semiconductor substrate |
| JP2005008954A (en) * | 2003-06-19 | 2005-01-13 | Canon Inc | Electroless plating method |
| JP2007005401A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Semiconductor device and its manufacturing method |
| JP2007005403A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Method of forming through wiring in semiconductor substrate |
| JP2007523464A (en) * | 2003-09-25 | 2007-08-16 | インテル コーポレイション | Deep via seed repair using electroless plating chemistry |
| JP2008053568A (en) * | 2006-08-25 | 2008-03-06 | Nec Electronics Corp | Semiconductor device and method for manufacturing the same |
| JP2008121107A (en) * | 2006-07-07 | 2008-05-29 | Rohm & Haas Electronic Materials Llc | Formaldehyde free electroless copper composition |
| JP2009088193A (en) * | 2007-09-28 | 2009-04-23 | Fujikura Ltd | Through wiring substrate, semiconductor package, and method of manufacturing through wiring substrate |
| JP2009525613A (en) * | 2006-02-03 | 2009-07-09 | マイクロン テクノロジー， インク． | Method for manufacturing and filling conductive vias and conductive vias so formed |
| JP2009295851A (en) * | 2008-06-06 | 2009-12-17 | Nec Electronics Corp | Semiconductor device, and method for manufacturing thereof |
| WO2010109746A1 (en) * | 2009-03-27 | 2010-09-30 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| JP2010532562A (en) * | 2007-07-05 | 2010-10-07 | オー・アー・セー・マイクロテック・アクチボラゲット | Low resistance through-wafer vias |
| JP2010538159A (en) * | 2007-08-31 | 2010-12-09 | ゼタコア インコーポレイテッド | Surface treatment method and fabricated apparatus for promoting metal plating |
| JP2012026029A (en) * | 2010-06-23 | 2012-02-09 | C Uyemura & Co Ltd | Aluminum oxide film remover and method for surface treatment of aluminum or aluminum alloy |
| JP2013106015A (en) * | 2011-11-17 | 2013-05-30 | Taiyo Yuden Co Ltd | Semiconductor device and manufacturing method of the same |
-
2013
- 2013-10-23 JP JP2013220265A patent/JP6213143B2/en active Active
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510655A (en) * | 1990-11-26 | 1996-04-23 | The Boeing Company | Silicon wafers containing conductive feedthroughs |
| JPH11120554A (en) * | 1997-10-14 | 1999-04-30 | Mitsubishi Chemical Corp | Production of substrate for magnetic recording medium |
| JP2001044197A (en) * | 1999-08-04 | 2001-02-16 | Sharp Corp | Semiconductor device and manufacture thereof |
| JP2001085434A (en) * | 1999-09-14 | 2001-03-30 | Hitachi Ltd | Method for plating semiconductor substrate |
| JP2005008954A (en) * | 2003-06-19 | 2005-01-13 | Canon Inc | Electroless plating method |
| JP2007523464A (en) * | 2003-09-25 | 2007-08-16 | インテル コーポレイション | Deep via seed repair using electroless plating chemistry |
| JP2007005401A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Semiconductor device and its manufacturing method |
| JP2007005403A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Method of forming through wiring in semiconductor substrate |
| JP2009525613A (en) * | 2006-02-03 | 2009-07-09 | マイクロン テクノロジー， インク． | Method for manufacturing and filling conductive vias and conductive vias so formed |
| JP2008121107A (en) * | 2006-07-07 | 2008-05-29 | Rohm & Haas Electronic Materials Llc | Formaldehyde free electroless copper composition |
| JP2008053568A (en) * | 2006-08-25 | 2008-03-06 | Nec Electronics Corp | Semiconductor device and method for manufacturing the same |
| JP2010532562A (en) * | 2007-07-05 | 2010-10-07 | オー・アー・セー・マイクロテック・アクチボラゲット | Low resistance through-wafer vias |
| JP2010538159A (en) * | 2007-08-31 | 2010-12-09 | ゼタコア インコーポレイテッド | Surface treatment method and fabricated apparatus for promoting metal plating |
| JP2009088193A (en) * | 2007-09-28 | 2009-04-23 | Fujikura Ltd | Through wiring substrate, semiconductor package, and method of manufacturing through wiring substrate |
| JP2009295851A (en) * | 2008-06-06 | 2009-12-17 | Nec Electronics Corp | Semiconductor device, and method for manufacturing thereof |
| WO2010109746A1 (en) * | 2009-03-27 | 2010-09-30 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| JP2012026029A (en) * | 2010-06-23 | 2012-02-09 | C Uyemura & Co Ltd | Aluminum oxide film remover and method for surface treatment of aluminum or aluminum alloy |
| JP2013106015A (en) * | 2011-11-17 | 2013-05-30 | Taiyo Yuden Co Ltd | Semiconductor device and manufacturing method of the same |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016213253A (en) * | 2015-04-30 | 2016-12-15 | 大日本印刷株式会社 | Through electrode substrate and interposer using through electrode substrate and semiconductor device |
| JP2017077628A (en) * | 2015-10-19 | 2017-04-27 | セイコーエプソン株式会社 | Liquid ejection head and manufacturing method of liquid ejection head |
| JP2018107423A (en) * | 2016-12-27 | 2018-07-05 | 大日本印刷株式会社 | Perforated substrate, mounting substrate including perforated substrate, and manufacturing method of perforated substrate |
| JP2018125348A (en) * | 2017-01-30 | 2018-08-09 | 大日本印刷株式会社 | Through-electrode substrate, method for manufacturing the same, and semiconductor device |
| JP7236059B2 (en) | 2017-06-16 | 2023-03-09 | 大日本印刷株式会社 | Through electrode substrate, mounting substrate provided with through electrode substrate, and method for manufacturing through electrode substrate |
| JP2019004085A (en) * | 2017-06-16 | 2019-01-10 | 大日本印刷株式会社 | Through electrode board, through electrode board equipped-mounting board, and manufacturing method of through electrode board |
| JP2022009249A (en) * | 2017-06-16 | 2022-01-14 | 大日本印刷株式会社 | Through electrode substrate, mounting substrate including through electrode substrate, and manufacturing method of through electrode substrate |
| US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US11201109B2 (en) | 2018-04-09 | 2021-12-14 | Corning Incorporated | Hermetic metallized via with improved reliability |
| CN112106187A (en) * | 2018-05-25 | 2020-12-18 | 凸版印刷株式会社 | Glass circuit board and method for manufacturing same |
| JP2018160697A (en) * | 2018-07-06 | 2018-10-11 | 大日本印刷株式会社 | Through electrode substrate |
| US11760682B2 (en) | 2019-02-21 | 2023-09-19 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
| CN112260055A (en) * | 2019-07-02 | 2021-01-22 | 株式会社日立电力解决方案 | Double-sided mounting substrate, method for manufacturing double-sided mounting substrate, and semiconductor laser |
| CN112260055B (en) * | 2019-07-02 | 2024-04-09 | 株式会社日立电力解决方案 | Double-sided mounting substrate, method for manufacturing double-sided mounting substrate, and semiconductor laser |
| JP7014241B2 (en) | 2020-02-25 | 2022-02-01 | 大日本印刷株式会社 | Manufacturing method of through silicon via board |
| JP2020109207A (en) * | 2020-02-25 | 2020-07-16 | 大日本印刷株式会社 | Method for manufacturing through electrode substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6213143B2 (en) | 2017-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6213143B2 (en) | Semiconductor substrate and method for manufacturing semiconductor substrate | |
| TWI391061B (en) | Wiring substrate and manufacturing method thereof | |
| KR20140094006A (en) | Embedded metal structures in ceramic substrates | |
| JP2016213296A (en) | Printed Wiring Board | |
| JP4307408B2 (en) | Method for hole-filling plating of base material having fine holes and / or fine grooves | |
| JP2014053608A (en) | Circuit board and production method of the same | |
| JP2017204527A (en) | Wiring circuit board and manufacturing method of the same | |
| JP2006339609A (en) | Wiring board and manufacturing method of the same | |
| JP4647505B2 (en) | Structure, wiring board, and method of manufacturing structure with wiring | |
| US8524512B2 (en) | Method for repairing copper diffusion barrier layers on a semiconductor solid substrate and repair kit for implementing this method | |
| KR100964030B1 (en) | Method for forming a through-hole electrode and structure therefore | |
| JP5191331B2 (en) | Through-hole filling method | |
| JPH07321111A (en) | Method of forming electroless plated interconnection for integrated circuit | |
| JP2002053971A (en) | Plating method, plating structure, method for producing semiconductor device, and semiconductor device | |
| JP2004197228A (en) | Pore-filling plating method for base material having fine pore and/or fine groove | |
| JP6622835B2 (en) | Wiring substrate manufacturing method | |
| KR101378756B1 (en) | Manufacturing method of printed circuit board which enables electroplating finishing process without lead line | |
| JP2015090980A (en) | Composite metal film, and method of circuit pattern formation of printed circuit board using the same | |
| JP2008153556A (en) | Manufacturing method of heatsink substrate for electric circuit | |
| WO2018097184A1 (en) | Electrolytic nickel (alloy) plating solution | |
| CN102623393B (en) | Method for filling micropores by utilizing tin whisker growth | |
| KR101102789B1 (en) | Method of electroplating the hole for the semi-additive process with a heterogeneous metal seed layer | |
| JP2008088521A (en) | Method for filling vias having different depths with plating | |
| JP2017005052A (en) | Substrate and method of manufacturing circuit board | |
| CN109154093B (en) | Electrolytic nickel (alloy) plating solution |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160315 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170327 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170404 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170526 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170613 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170724 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170822 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170904 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6213143 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |