JP2015070255A - Photovoltaic element and manufacturing method therefor - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000010408 film Substances 0.000 claims abstract description 148
- 239000004065 semiconductor Substances 0.000 claims abstract description 88
- 239000010409 thin film Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000013078 crystal Substances 0.000 claims abstract description 40
- 238000004544 sputter deposition Methods 0.000 claims abstract description 26
- 229910003437 indium oxide Inorganic materials 0.000 claims abstract description 22
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 19
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 34
- 238000005477 sputtering target Methods 0.000 claims description 23
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 12
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 239000010955 niobium Substances 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims 1
- 238000010248 power generation Methods 0.000 abstract description 22
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 239000000243 solution Substances 0.000 description 10
- 238000010030 laminating Methods 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- OEIMLTQPLAGXMX-UHFFFAOYSA-I tantalum(v) chloride Chemical compound Cl[Ta](Cl)(Cl)(Cl)Cl OEIMLTQPLAGXMX-UHFFFAOYSA-I 0.000 description 8
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000000843 powder Substances 0.000 description 6
- 238000001878 scanning electron micrograph Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000007733 ion plating Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 239000002244 precipitate Substances 0.000 description 5
- 239000002243 precursor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XURCIPRUUASYLR-UHFFFAOYSA-N Omeprazole sulfide Chemical compound N=1C2=CC(OC)=CC=C2NC=1SCC1=NC=C(C)C(OC)=C1C XURCIPRUUASYLR-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004050 hot filament vapor deposition Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 239000012266 salt solution Substances 0.000 description 4
- 229910021642 ultra pure water Inorganic materials 0.000 description 4
- 239000012498 ultrapure water Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910000000 metal hydroxide Inorganic materials 0.000 description 3
- 150000004692 metal hydroxides Chemical class 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000010298 pulverizing process Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 229910001887 tin oxide Inorganic materials 0.000 description 3
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 239000011268 mixed slurry Substances 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- VXUYXOFXAQZZMF-UHFFFAOYSA-N titanium(IV) isopropoxide Chemical compound CC(C)O[Ti](OC(C)C)(OC(C)C)OC(C)C VXUYXOFXAQZZMF-UHFFFAOYSA-N 0.000 description 2
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CUJAZYOPZISSKK-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[O--].[O--].[Ti+4].[In+3].[Ta+5] Chemical compound [O--].[O--].[O--].[O--].[O--].[O--].[Ti+4].[In+3].[Ta+5] CUJAZYOPZISSKK-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000005431 greenhouse gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- WMCMKBBLRYJDNO-UHFFFAOYSA-N indium(3+) oxygen(2-) tantalum(5+) Chemical compound [O--].[O--].[O--].[O--].[In+3].[Ta+5] WMCMKBBLRYJDNO-UHFFFAOYSA-N 0.000 description 1
- PSCMQHVBLHHWTO-UHFFFAOYSA-K indium(iii) chloride Chemical compound Cl[In](Cl)Cl PSCMQHVBLHHWTO-UHFFFAOYSA-K 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 239000003002 pH adjusting agent Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
- C23C14/086—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Abstract
Description
本発明は、ヘテロ接合を有する光発電素子（太陽電池）及びその製造方法に関する。 The present invention relates to a photovoltaic device (solar cell) having a heterojunction and a method for manufacturing the photovoltaic device.
ＣＯ２等の温室効果ガスを発生しないクリーンな発電手段として、また、原子力発電に代わる操業安全性の高い発電手段として、光発電素子（太陽電池）が注目されている。光発電素子の一つとして、発電効率の高いヘテロ接合を有する光発電素子（ヘテロ接合型の光発電素子）がある。ヘテロ接合とは、例えば単結晶半導体と非晶質半導体との接合をいい、この接合により拡散電位が形成される。 Photovoltaic elements (solar cells) are attracting attention as clean power generation means that does not generate greenhouse gases such as CO 2 and as power generation means with high operational safety in place of nuclear power generation. As one of the photovoltaic elements, there is a photovoltaic element having a heterojunction with high power generation efficiency (heterojunction photovoltaic element). The heterojunction refers to, for example, a junction between a single crystal semiconductor and an amorphous semiconductor, and a diffusion potential is formed by this junction.
一方、光発電素子の電極には、透光性と導電性とが必要であるため、通常、透明導電膜が用いられる。透明導電膜を形成する材料としては、低抵抗性（導電性）を有するインジウム錫酸化物（Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ：ＩＴＯ）が広く使用されている。このような中、透明導電膜の導電性等をより高めるべく各種材料が開発されており、例えば水素及びセリウムを含む酸化インジウムから形成された透明導電膜が提案されている（特許文献１参照）。 On the other hand, a transparent conductive film is usually used for the electrode of the photovoltaic device because it requires translucency and conductivity. As a material for forming the transparent conductive film, indium tin oxide (ITO) having low resistance (conductivity) is widely used. Under such circumstances, various materials have been developed in order to further increase the conductivity and the like of the transparent conductive film. For example, a transparent conductive film formed of indium oxide containing hydrogen and cerium has been proposed (see Patent Document 1). .
また、透明導電膜は、スパッタリング法により成膜されることが一般的であるが、スパッタリング法によれば、積層される側の層（通常、非晶質半導体の層）の劣化が生じやすい。従って、このような事情も考慮し、特許文献１においてはイオンプレーティング法により透明導電膜を成膜することが記載されている。しかし、イオンプレーティング法は、スパッタリング法に比してコスト増になるという不都合がある。 In addition, the transparent conductive film is generally formed by a sputtering method, but the sputtering method tends to cause deterioration of a layer on the side to be laminated (usually an amorphous semiconductor layer). Therefore, in consideration of such circumstances, Patent Document 1 describes forming a transparent conductive film by an ion plating method. However, the ion plating method has a disadvantage that the cost is increased as compared with the sputtering method.
加えて、ＩＴＯ等からなる膜は、結晶化させて抵抗を下げるために比較的高温（例えば２００℃以上）で成膜することや、成膜後熱処理することが必要となる。しかし、ヘテロ接合型の光発電素子においては、２００℃以上といった高温で透明導電膜を積層又は処理すると、非晶質半導体の結晶化が生じることなどにより性能が劣化する傾向にある。 In addition, a film made of ITO or the like needs to be formed at a relatively high temperature (for example, 200 ° C. or higher) and heat-treated after the film formation in order to crystallize and lower the resistance. However, in a heterojunction photovoltaic device, when a transparent conductive film is laminated or processed at a high temperature of 200 ° C. or higher, performance tends to deteriorate due to crystallization of an amorphous semiconductor.
本発明はかかる事情に鑑みてなされたもので、透明導電膜をスパッタリング法により成膜しても高い発電効率を有するヘテロ接合型の光発電素子、及びこのような光発電素子の製造方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and provides a heterojunction photovoltaic device having high power generation efficiency even when a transparent conductive film is formed by sputtering, and a method for manufacturing such a photovoltaic device. The purpose is to do.
前記目的に沿う第１の発明に係る光発電素子は、ｎ型結晶半導体基板と、該ｎ型結晶半導体基板の一側にこの順に積層されるｐ型非晶質系半導体薄膜及び第１の透明導電膜と、前記ｎ型結晶半導体基板の他側にこの順に積層されるｎ型非晶質系半導体薄膜及び第２の透明導電膜とを備える光発電素子において、
前記第１及び第２の透明導電膜のいずれかは、少なくともタンタルがドープされた酸化インジウムから形成されている透明導電膜（α）である。
The photovoltaic device according to the first invention that meets the above object includes an n-type crystal semiconductor substrate, a p-type amorphous semiconductor thin film stacked in this order on one side of the n-type crystal semiconductor substrate, and a first transparent element. In a photovoltaic device comprising a conductive film, an n-type amorphous semiconductor thin film stacked in this order on the other side of the n-type crystal semiconductor substrate, and a second transparent conductive film,
One of the first and second transparent conductive films is a transparent conductive film (α) formed of indium oxide doped with at least tantalum.
第１の発明に係る光発電素子によれば、少なくともタンタルがドープされた酸化インジウムにより透明導電膜（α）を形成することで、発電効率を高めることができる。具体的には、透明導電膜（α）は、比較的低温で結晶化し、低抵抗性が得られる。このため、スパッタリング法により高温処理を経ることなく低抵抗性に優れる透明導電膜（α）を得ることができ、高い発電効率を有するヘテロ接合型の光発電素子を得ることができる。 According to the photovoltaic device of the first invention, the power generation efficiency can be increased by forming the transparent conductive film (α) from indium oxide doped with at least tantalum. Specifically, the transparent conductive film (α) is crystallized at a relatively low temperature, and low resistance is obtained. For this reason, the transparent conductive film (α) having excellent low resistance can be obtained without high temperature treatment by sputtering, and a heterojunction photovoltaic device having high power generation efficiency can be obtained.
第１の発明に係る光発電素子において、前記透明導電膜（α）における前記タンタルの含有量が酸化物換算で０．１質量％以上５質量％以下であることが好ましい。透明導電膜（α）にタンタルを前記範囲で含有させることにより、低抵抗性と熱安定性等とをバランスよく高めることができる。 In the photovoltaic device according to the first invention, the tantalum content in the transparent conductive film (α) is preferably 0.1% by mass or more and 5% by mass or less in terms of oxide. By including tantalum in the above range in the transparent conductive film (α), low resistance, thermal stability, and the like can be improved in a balanced manner.
第１の発明に係る光発電素子において、前記酸化インジウムには、チタン、バナジウム及びニオブからなる群より選ばれる少なくとも１種の元素（ｘ）がさらにドープされていることが好ましい。元素（ｘ）がさらにドープされていることで、膜の均質性、低温結晶性、低抵抗性等をさらに高めることができる。 In the photovoltaic device according to the first invention, it is preferable that the indium oxide is further doped with at least one element (x) selected from the group consisting of titanium, vanadium and niobium. When the element (x) is further doped, the homogeneity, low temperature crystallinity, low resistance, etc. of the film can be further enhanced.
第１の発明に係る光発電素子において、前記透明導電膜（α）における前記タンタル及び前記元素（ｘ）それぞれの含有量が酸化物換算で共に０．１質量％以上であり、かつ前記タンタル及び前記元素（ｘ）の合計含有量が酸化物換算で５質量％以下であることが好ましい。タンタル及び元素（ｘ）の含有量を前記範囲とすることにより、低抵抗性と熱安定性等とをよりバランスよく高めることができる。 In the photovoltaic device according to the first invention, the contents of the tantalum and the element (x) in the transparent conductive film (α) are both 0.1% by mass or more in terms of oxides, and the tantalum and The total content of the element (x) is preferably 5% by mass or less in terms of oxide. By setting the contents of tantalum and element (x) in the above range, low resistance, thermal stability, and the like can be improved in a balanced manner.
第１の発明に係る光発電素子において、前記第１及び第２の透明導電膜が共に前記透明導電膜（α）であることが好ましい。このように両面に透明導電膜（α）を用いることで、発電効率に加え、生産性等もより高めることができる。 In the photovoltaic device according to the first invention, it is preferable that both the first and second transparent conductive films are the transparent conductive film (α). Thus, by using the transparent conductive film (α) on both sides, productivity and the like can be further increased in addition to the power generation efficiency.
第１の発明に係る光発電素子において、前記ｎ型結晶半導体基板がテクスチャー構造を有する面を備えることが好ましい。ｎ型結晶半導体基板がテクスチャー構造を有する面を有すると、光の乱反射による光閉じ込め効果が生じ、発電効率等をさらに高めることができる。 In the photovoltaic device according to the first invention, it is preferable that the n-type crystal semiconductor substrate has a surface having a texture structure. When the n-type crystal semiconductor substrate has a surface having a texture structure, a light confinement effect due to irregular reflection of light occurs, and the power generation efficiency and the like can be further increased.
第１の発明に係る光発電素子において、前記透明導電膜（α）が形成温度２００℃未満のスパッタリング法により形成されていることが好ましい。このように形成温度２００℃未満で透明導電膜（α）を成膜することにより、高い発電効率を有するヘテロ接合型光発電素子とすることができる。また、スパッタリング法を用いることで、生産性の高い光発電素子とすることができる。 In the photovoltaic device according to the first invention, the transparent conductive film (α) is preferably formed by a sputtering method having a formation temperature of less than 200 ° C. Thus, by forming a transparent conductive film (α) at a formation temperature of less than 200 ° C., a heterojunction photovoltaic device having high power generation efficiency can be obtained. Further, by using a sputtering method, a photovoltaic device with high productivity can be obtained.
前記目的に沿う第２の発明に係る光発電素子の製造方法は、ｎ型結晶半導体基板と、該ｎ型結晶半導体基板の一側にこの順に積層されるｐ型非晶質系半導体薄膜及び第１の透明導電膜と、前記ｎ型結晶半導体基板の他側にこの順に積層されるｎ型非晶質系半導体薄膜及び第２の透明導電膜とを備える光発電素子の製造方法において、
主成分が酸化インジウムであり、酸化タンタルを含むスパッタリングターゲットを用いたスパッタリング法により、前記第１及び第２の透明導電膜の少なくともいずれかを形成する工程を有し、
該工程における形成温度が２００℃未満である。
A photovoltaic device manufacturing method according to a second aspect of the invention that meets the above-described object is an n-type crystal semiconductor substrate, a p-type amorphous semiconductor thin film stacked in this order on one side of the n-type crystal semiconductor substrate, In a method for manufacturing a photovoltaic device, comprising: 1 transparent conductive film; an n-type amorphous semiconductor thin film stacked in this order on the other side of the n-type crystal semiconductor substrate; and a second transparent conductive film.
A step of forming at least one of the first and second transparent conductive films by a sputtering method using a sputtering target containing indium oxide as a main component and containing tantalum oxide;
The formation temperature in this step is less than 200 ° C.
第２の発明に係る光発電素子の製造方法によれば、生産コストを抑え、高い発電効率を有する光発電素子を得ることができる。 According to the photovoltaic element manufacturing method according to the second aspect of the present invention, it is possible to obtain a photovoltaic element having a low generation cost and high power generation efficiency.
ここで、「非晶質系」とは、非晶質のみならず、微結晶を含む意味である。「微結晶」とは、ラマン分光法により結晶ピークが観察されるものを意味する。また、「形成温度」とは、スパッタリングを行う際の基板温度、及び必要に応じて行われるスパッタリングによる膜積層後の熱処理温度をいう。 Here, “amorphous” means not only amorphous but also microcrystals. “Microcrystal” means a crystal peak observed by Raman spectroscopy. The “forming temperature” refers to a substrate temperature at the time of sputtering and a heat treatment temperature after film deposition by sputtering performed as necessary.
第１の発明に係る光発電素子は高い発電効率を有し、特に透明導電膜（α）をスパッタリング法により成膜しても十分な発電効率を有することから、低コストで生産することができる。また、第２の発明に係る光発電素子の製造方法によれば、高い発電効率を有する光発電素子を低コストで製造することができる。 The photovoltaic device according to the first invention has high power generation efficiency, and particularly has sufficient power generation efficiency even when the transparent conductive film (α) is formed by sputtering, so that it can be produced at low cost. . Moreover, according to the method for manufacturing a photovoltaic device according to the second invention, a photovoltaic device having high power generation efficiency can be manufactured at low cost.
続いて、添付した図面を参照しながら本発明を具体化した実施の形態について説明する。 Next, embodiments of the present invention will be described with reference to the accompanying drawings.
（光発電素子）
図１に示すように、本発明の第１の実施の形態に係る光発電素子１０は、板状の多層構造体である。光発電素子１０は、ｎ型結晶半導体基板１１と、ｎ型結晶半導体基板１１の一側（図１における上側）にこの順で積層される第１の真性非晶質系半導体薄膜１２、ｐ型非晶質系半導体薄膜１３及び第１の透明導電膜１４と、ｎ型結晶半導体基板１１の他側（図１における下側）にこの順で積層される第２の真性非晶質系半導体薄膜１５、ｎ型非晶質系半導体薄膜１６及び第２の透明導電膜１７とを有する。さらに、光発電素子１０は、第１の透明導電膜１４の表面（一側）に配設される集電極１８と、第２の透明導電膜１７の表面（他側）に配設される集電極１９とを有する。
(Photovoltaic element)
As shown in FIG. 1, the photovoltaic device 10 according to the first exemplary embodiment of the present invention is a plate-like multilayer structure. The photovoltaic device 10 includes an n-type crystal semiconductor substrate 11, a first intrinsic amorphous semiconductor thin film 12 stacked in this order on one side of the n-type crystal semiconductor substrate 11 (upper side in FIG. 1), a p-type A second intrinsic amorphous semiconductor thin film laminated in this order on the other side (lower side in FIG. 1) of the amorphous semiconductor thin film 13 and the first transparent conductive film 14 and the n-type crystal semiconductor substrate 11 15 and an n-type amorphous semiconductor thin film 16 and a second transparent conductive film 17. Further, the photovoltaic element 10 is a collector electrode 18 disposed on the surface (one side) of the first transparent conductive film 14 and a collector electrode disposed on the surface (other side) of the second transparent conductive film 17. And an electrode 19.
ｎ型結晶半導体基板１１としては、ｎ型の半導体特性を有する結晶体の基板であれば特に限定されず公知のものを用いることができる。ｎ型結晶半導体基板１１を構成する結晶半導体としては、シリコン（Ｓｉ）の他、ＳｉＣ、ＳｉＧｅ、ＳｉＮ等を挙げることができるが、生産性等の点からシリコンが好ましい。ｎ型結晶半導体基板１１は、単結晶体であってもよいし、多結晶体であってもよい。 The n-type crystal semiconductor substrate 11 is not particularly limited as long as it is a crystalline substrate having n-type semiconductor characteristics, and a known substrate can be used. Examples of the crystal semiconductor constituting the n-type crystal semiconductor substrate 11 include SiC (SiGe), SiN, etc. in addition to silicon (Si), but silicon is preferable from the viewpoint of productivity. The n-type crystal semiconductor substrate 11 may be a single crystal or a polycrystal.
ｎ型結晶半導体基板１１の一側の面には、テクスチャー構造が形成されている。このテクスチャー構造は他側の面にも形成されていてもよい。このテクスチャー構造は、光の乱反射による光閉じ込めを有効にする。このテクスチャー構造としては、具体的にはｎ型結晶半導体基板１１の上下（一側及び他側）の面の略全面を覆うように多数のピラミッド形状を有する凹凸構造が不規則に配置されている。前記凹凸構造（テクスチャー構造）の高さ（大きさ）は不揃いであって、隣り合う凹凸の一部が重なっていてもよい。また、頂点や谷部が丸みを帯びていてもよい。この凹凸の高さとしては、数μｍ〜数十μｍ程度である。このようなテクスチャー構造は、例えば、約１〜５質量％の水酸化ナトリウムを含むエッチング液に基板材料を浸漬し、基板材料の（１００）面を異方性エッチングすることにより得ることが出来る。 A texture structure is formed on one surface of the n-type crystal semiconductor substrate 11. This texture structure may also be formed on the other surface. This texture structure enables light confinement due to diffuse reflection of light. Specifically, as this texture structure, a concavo-convex structure having a large number of pyramid shapes is irregularly arranged so as to cover substantially the entire upper and lower surfaces (one side and the other side) of the n-type crystal semiconductor substrate 11. . The height (size) of the concavo-convex structure (texture structure) may be uneven, and adjacent concavo-convex portions may overlap. Moreover, a vertex and a trough part may be roundish. The height of the unevenness is about several μm to several tens of μm. Such a texture structure can be obtained, for example, by immersing the substrate material in an etching solution containing about 1 to 5% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
第１の真性非晶質系半導体薄膜１２は、ｎ型結晶半導体基板１１の一側に積層されている。第１の真性非晶質系半導体薄膜１２を構成する半導体としては、シリコン（Ｓｉ）の他、ＳｉＣ、ＳｉＧｅ、ＳｉＮ等を挙げることができるが、生産性等の点からシリコンが好ましい。真性非晶質系半導体薄膜１２の膜厚としては特に限定されないが、例えば１ｎｍ以上１０ｎｍ以下とすることができ、４ｎｍ以下が好ましい。この膜厚が１ｎｍ未満の場合は、欠陥が発生しやすくなることなどにより、キャリアの再結合が生じやすくなる。また、この膜厚が１０ｎｍを超える場合は、短絡電流の低下や、光吸収量の増加が生じやすくなる。 The first intrinsic amorphous semiconductor thin film 12 is stacked on one side of the n-type crystal semiconductor substrate 11. Examples of the semiconductor constituting the first intrinsic amorphous semiconductor thin film 12 include silicon (Si), SiC, SiGe, SiN, etc., but silicon is preferable from the viewpoint of productivity. The thickness of the intrinsic amorphous semiconductor thin film 12 is not particularly limited, but can be, for example, 1 nm or more and 10 nm or less, and preferably 4 nm or less. When the film thickness is less than 1 nm, recombination of carriers is likely to occur due to defects easily occurring. Moreover, when this film thickness exceeds 10 nm, it becomes easy to produce the fall of a short circuit current and the increase in light absorption.
ｐ型非晶質系半導体薄膜１３は、第１の真性非晶質系半導体薄膜１２の一側に積層されている。ｐ型非晶質系半導体薄膜１３を構成する半導体としては、ｐ型非晶質系シリコンのほか、それぞれｐ型非晶質系のＳｉＣ、ＳｉＧｅ、ＳｉＮ等を挙げることができるが、生産性等の点からｐ型非晶質系シリコンが好ましい。ｐ型非晶質系半導体薄膜１３の膜厚としては特に限定されないが、例えば１ｎｍ以上６ｎｍ未満が好ましく、２ｎｍ以上５ｎｍ以下がさらに好ましい。このような範囲の膜厚とすることで、キャリアの再結合の発生と直列抵抗とをバランスよく低減することができる。 The p-type amorphous semiconductor thin film 13 is laminated on one side of the first intrinsic amorphous semiconductor thin film 12. Examples of the semiconductor constituting the p-type amorphous semiconductor thin film 13 include p-type amorphous silicon, p-type amorphous SiC, SiGe, SiN and the like. From this point, p-type amorphous silicon is preferable. The thickness of the p-type amorphous semiconductor thin film 13 is not particularly limited, but is preferably 1 nm or more and less than 6 nm, for example, and more preferably 2 nm or more and 5 nm or less. By setting the film thickness within such a range, occurrence of carrier recombination and series resistance can be reduced in a balanced manner.
第１の透明導電膜１４（透明導電膜（α））は、ｐ型非晶質系半導体薄膜１３の一側に積層されている。第１の透明導電膜１４を構成する材料は、少なくともタンタルがドープされた酸化インジウムであり、チタン、バナジウム及びニオブからなる群より選ばれる少なくとも１種の元素（ｘ）がさらにドープされていることが好ましい。元素（ｘ）の中では、チタンがより好ましい。第１の透明導電膜１４には、本発明の効果を阻害しない範囲で他の元素（例えば、錫等）がさらに含まれていてもよい。 The first transparent conductive film 14 (transparent conductive film (α)) is laminated on one side of the p-type amorphous semiconductor thin film 13. The material constituting the first transparent conductive film 14 is indium oxide doped with at least tantalum, and is further doped with at least one element (x) selected from the group consisting of titanium, vanadium and niobium. Is preferred. Of the elements (x), titanium is more preferable. The first transparent conductive film 14 may further contain other elements (for example, tin and the like) as long as the effects of the present invention are not impaired.
第１の透明導電膜１４におけるタンタルの含有量としては、酸化物（Ｔａ２Ｏ５）換算で０．１質量％以上５質量％以下が好ましく、０．５質量％以上３質量％以下がより好ましい。また、第１の透明導電膜１４における元素（ｘ）の含有量としては、酸化物（ＴｉＯ２、Ｖ２Ｏ５及びＮｂ２Ｏ５）換算で０．１質量％以上５質量％以下が好ましく、０．５質量％以上３質量％以下がより好ましい。さらには、タンタル及び元素（ｘ）の合計含有量は酸化物換算で５質量％以下が好ましく、３質量％以下がより好ましい。各ドーパント（タンタル及び元素（ｘ））の含有量が上記下限未満の場合は、各ドーパントを添加させた効果（低温での結晶性、低抵抗性、熱安定性等）が十分に発揮されない場合がある。一方、各ドーパントの含有量が上記上限を超える場合は、低抵抗性、成膜性、透光性等が低下する傾向にある。なお、第１の透明導電膜１４における酸化インジウムの含有量としては、９０質量％以上が好ましく、９５質量％以上がより好ましく、９７質量％以上９９．９質量％以下がさらに好ましい。 The content of tantalum in the first transparent conductive film 14 is preferably 0.1% by mass or more and 5% by mass or less, more preferably 0.5% by mass or more and 3% by mass or less in terms of oxide (Ta 2 O 5 ). preferable. Further, the content of the element (x) in the first transparent conductive film 14 is preferably 0.1% by mass or more and 5% by mass or less in terms of oxides (TiO 2 , V 2 O 5 and Nb 2 O 5 ). 0.5 mass% or more and 3 mass% or less is more preferable. Furthermore, the total content of tantalum and element (x) is preferably 5% by mass or less, more preferably 3% by mass or less in terms of oxide. When the content of each dopant (tantalum and element (x)) is less than the above lower limit, the effects of adding each dopant (crystallinity at low temperature, low resistance, thermal stability, etc.) are not sufficiently exhibited. There is. On the other hand, when the content of each dopant exceeds the above upper limit, low resistance, film formability, translucency, and the like tend to decrease. In addition, as content of indium oxide in the 1st transparent conductive film 14, 90 mass% or more is preferable, 95 mass% or more is more preferable, 97 mass% or more and 99.9 mass% or less are further more preferable.
第１の透明導電膜１４の主成分である酸化インジウムは結晶化されている。この結晶性の酸化インジウムの面内長軸平均結晶粒径としては、１０ｎｍ以上３００ｎｍ未満が好ましく、４０ｎｍ以上２００ｎｍ以下がより好ましい。面内長軸平均結晶粒径とは、走査型電子顕微鏡（ＳＥＭ）から得られる像において、面内に存在する各結晶粒子の最も長い径を測定し、この測定値が大きい上位２０粒子の測定値を数平均したものをいう。第１の透明導電膜１４が、このように小さい粒径の結晶性酸化インジウムから主に構成されることで、結晶性の高く、移動度の高い膜となる。なお、このように粒径の小さい結晶が形成されることは、ドープされるタンタルに由来すると考えられる。 Indium oxide which is the main component of the first transparent conductive film 14 is crystallized. The in-plane long axis average crystal grain size of the crystalline indium oxide is preferably 10 nm or more and less than 300 nm, and more preferably 40 nm or more and 200 nm or less. The in-plane long axis average crystal grain size is the measurement of the top 20 particles having the largest measured value by measuring the longest diameter of each crystal particle present in the plane in an image obtained from a scanning electron microscope (SEM). This is the number averaged value. When the first transparent conductive film 14 is mainly composed of crystalline indium oxide having such a small particle diameter, a film having high crystallinity and high mobility is obtained. In addition, it is thought that the crystal having such a small particle diameter is derived from doped tantalum.
第１の透明導電膜１４の膜厚としては、特に限定されないが、透光性と集電性とを両立させることができるなどの点から４０ｎｍ以上１００ｎｍ以下が好ましい。また、第１の透明導電膜１４の比抵抗値としては、５×１０−５Ω・ｃｍ以上１×１０−３Ω・ｃｍ以下が好ましく、５×１０−４Ω・ｃｍ以下がより好ましい。 Although it does not specifically limit as a film thickness of the 1st transparent conductive film 14, 40 nm or more and 100 nm or less are preferable from the point of being able to make translucency and current collection compatible. In addition, the specific resistance value of the first transparent conductive film 14 is preferably 5 × 10 −5 Ω · cm to 1 × 10 −3 Ω · cm, and more preferably 5 × 10 −4 Ω · cm.
第２の真性非晶質系半導体薄膜１５は、ｎ型結晶半導体基板１１の他側に積層されている。第２の真性非晶質系半導体薄膜１５を構成する半導体は、第１の真性非晶質系半導体薄膜１２と同様とすることができる。第２の真性非晶質系半導体薄膜１５の膜厚としては、例えば１ｎｍ以上１０ｎｍ以下とすることができる。 The second intrinsic amorphous semiconductor thin film 15 is stacked on the other side of the n-type crystal semiconductor substrate 11. The semiconductor constituting the second intrinsic amorphous semiconductor thin film 15 can be the same as the first intrinsic amorphous semiconductor thin film 12. The film thickness of the second intrinsic amorphous semiconductor thin film 15 can be, for example, 1 nm or more and 10 nm or less.
ｎ型非晶質系半導体薄膜１６は、第２の真性非晶質系半導体薄膜１５の他側に積層されている。ｎ型非晶質系半導体薄膜１６を構成する半導体としては、ｎ型非晶質系シリコンのほか、それぞれｎ型非晶質系のＳｉＣ、ＳｉＧｅ、ＳｉＮ等を挙げることができるが、生産性等の点からｎ型非晶質系シリコンが好ましい。ｎ型非晶質系半導体薄膜１６の膜厚としては特に限定されないが、例えば１ｎｍ以上１５ｎｍ以下が好ましく、２ｎｍ以上１０ｎｍ以下がさらに好ましい。このような範囲の膜厚とすることで、キャリアの再結合の発生と直列抵抗とをバランスよく低減することができる。 The n-type amorphous semiconductor thin film 16 is laminated on the other side of the second intrinsic amorphous semiconductor thin film 15. Examples of the semiconductor constituting the n-type amorphous semiconductor thin film 16 include n-type amorphous silicon, n-type amorphous SiC, SiGe, SiN and the like. From this point, n-type amorphous silicon is preferable. The thickness of the n-type amorphous semiconductor thin film 16 is not particularly limited, but is preferably 1 nm to 15 nm, for example, and more preferably 2 nm to 10 nm. By setting the film thickness within such a range, occurrence of carrier recombination and series resistance can be reduced in a balanced manner.
第２の透明導電膜１７（透明導電膜（α））は、ｎ型非晶質系半導体薄膜１６の他側に積層されている。第２の透明導電膜１７を形成する材料（組成）、特性、好ましい膜厚等は、第１の透明導電膜１４と同様である。但し、第１の透明導電膜１４と第２の透明導電膜１７とは、組成、膜厚等が異なっていてもよい。 The second transparent conductive film 17 (transparent conductive film (α)) is laminated on the other side of the n-type amorphous semiconductor thin film 16. The material (composition), characteristics, preferable film thickness, and the like for forming the second transparent conductive film 17 are the same as those of the first transparent conductive film 14. However, the first transparent conductive film 14 and the second transparent conductive film 17 may have different compositions, film thicknesses, and the like.
集電極１８、１９は、互いに平行かつ等間隔に形成される複数のバスバー電極、及びこれらのバスバー電極に直交し、互いに平行かつ等間隔に形成される複数のフィンガー電極を有する。 The collector electrodes 18 and 19 have a plurality of bus bar electrodes formed in parallel with each other at equal intervals, and a plurality of finger electrodes orthogonal to these bus bar electrodes and formed in parallel with each other at equal intervals.
バスバー電極及びフィンガー電極は、それぞれ線状又は帯状であり、導電性材料から形成されている。この導電性材料としては、銀ペースト等の導電性接着剤や、銅線等の金属導線を用いることができる。各バスバー電極の幅としては、例えば０．５ｍｍ以上２ｍｍ以下程度であり、各フィンガー電極の幅としては、例えば１０μｍ以上３００μｍ以下程度である。また、各フィンガー電極間の間隔としては、例えば０．５ｍｍ以上４ｍｍ以下程度である。 The bus bar electrode and the finger electrode each have a linear shape or a strip shape, and are formed of a conductive material. As this conductive material, a conductive adhesive such as a silver paste or a metal conductive wire such as a copper wire can be used. The width of each bus bar electrode is, for example, about 0.5 mm to 2 mm, and the width of each finger electrode is, for example, about 10 μm to 300 μm. Moreover, as a space | interval between each finger electrode, it is about 0.5 mm or more and 4 mm or less, for example.
なお、使用の際光入射面と反対側に位置する集電極１８又は１９は、バスバー電極とフィンガー電極とからなる構造ではなく、全面に導電性材料が積層された構造とすることもできる。このような構造の集電極はめっきや金属箔の積層等により形成することができる。他側の集電極をこのような構造にすることで、他側の集電効率を高めることができる。また、一側からの入射光のうち、ｐｎ接合部分を透過した入射光が、全面積層された集電極全面により反射するため発電効率を高めることができる。 In addition, the collector electrode 18 or 19 positioned on the opposite side to the light incident surface in use may be a structure in which a conductive material is laminated on the entire surface, instead of a structure including a bus bar electrode and a finger electrode. The collector electrode having such a structure can be formed by plating, metal foil lamination, or the like. By making the collector electrode on the other side into such a structure, the current collection efficiency on the other side can be increased. In addition, among incident light from one side, incident light transmitted through the pn junction portion is reflected by the entire surface of the collector electrode laminated on the entire surface, so that power generation efficiency can be improved.
このような構造を有する光発電素子１０は、通常、複数を直列に接続して使用される。複数の光発電装置１０を直列接続して使用することで、発電電圧を高めることができる。 The photovoltaic elements 10 having such a structure are usually used by connecting a plurality of photovoltaic elements 10 in series. By using a plurality of photovoltaic power generation devices 10 connected in series, the generated voltage can be increased.
光発電素子１０における光入射面は特に限定されず、通常、一側（図１における上側）であるが、他側（図１における下側）を光入射面としてもよい。光発電素子１０によれば、少なくともタンタルがドープされた酸化インジウムにより透明導電膜１４、１７が形成されているため、発電効率が優れる。 The light incident surface of the photovoltaic element 10 is not particularly limited, and is normally one side (the upper side in FIG. 1), but the other side (the lower side in FIG. 1) may be the light incident surface. According to the photovoltaic device 10, since the transparent conductive films 14 and 17 are formed of indium oxide doped with at least tantalum, the power generation efficiency is excellent.
（光発電素子の製造方法）
次いで、本発明の第２の実施の形態に係る光発電素子の製造方法について説明する。光発電素子１０は、ｎ型結晶半導体基板１１の一側に第１の真性非晶質系半導体薄膜１２を積層する工程、さらにｐ型非晶質系半導体薄膜１３を積層する工程、さらに第１の透明導電膜１４を積層する工程、ｎ型結晶半導体基板１１の他側に第２の真性非晶質系半導体薄膜１５を積層する工程、さらにｎ型非晶質系半導体薄膜１６を積層する工程、さらに第２の透明導電膜１７を積層する工程、及び第１の透明導電膜１４の一側表面及び第２の透明導電膜１７の他側表面に集電極１８、１９を配設する工程を有する。なお、各工程の順は、光発電素子１０の層構造を得ることができる順である限り特に限定されるものではない。
(Method for manufacturing photovoltaic device)
Next, a method for manufacturing a photovoltaic device according to the second embodiment of the present invention will be described. The photovoltaic element 10 includes a step of laminating a first intrinsic amorphous semiconductor thin film 12 on one side of an n-type crystal semiconductor substrate 11, a step of laminating a p-type amorphous semiconductor thin film 13, and a first step. A step of laminating the transparent conductive film 14, a step of laminating the second intrinsic amorphous semiconductor thin film 15 on the other side of the n-type crystal semiconductor substrate 11, and a step of laminating the n-type amorphous semiconductor thin film 16. Further, a step of laminating the second transparent conductive film 17 and a step of disposing the collector electrodes 18 and 19 on the one side surface of the first transparent conductive film 14 and the other side surface of the second transparent conductive film 17. Have. In addition, the order of each process will not be specifically limited as long as it is the order which can obtain the layer structure of the photovoltaic device 10. FIG.
第１及び第２の真性非晶質系半導体膜１２、１５を積層する方法としては、例えば、化学気相成長法（例えばプラズマＣＶＤ法や触媒ＣＶＤ法（別名ホットワイヤＣＶＤ法）等）などの公知の方法が挙げられる。プラズマＣＶＤ法による場合、原料ガスとしては例えばＳｉＨ４とＨ２との混合ガスを用いることができる。 As a method of laminating the first and second intrinsic amorphous semiconductor films 12 and 15, for example, chemical vapor deposition (for example, plasma CVD method or catalytic CVD method (also called hot wire CVD method)), etc. A well-known method is mentioned. In the case of the plasma CVD method, for example, a mixed gas of SiH 4 and H 2 can be used as the source gas.
ｐ型非晶質系半導体薄膜１３及びｎ型非晶質系半導体薄膜１６を積層する方法としても、例えば、化学気相成長法（例えばプラズマＣＶＤ法や触媒ＣＶＤ法（別名ホットワイヤＣＶＤ法）等）などの公知の方法により成膜することができる。プラズマＣＶＤ法による場合、原料ガスとしてはｐ型非晶質系半導体薄膜１３においては例えばＳｉＨ４とＨ２とＢ２Ｈ６との混合ガスを、ｎ型非晶質系半導体薄膜１６においては例えばＳｉＨ４とH２とＰＨ３との混合ガスを用いることができる。 As a method of laminating the p-type amorphous semiconductor thin film 13 and the n-type amorphous semiconductor thin film 16, for example, a chemical vapor deposition method (for example, plasma CVD method or catalytic CVD method (also called hot wire CVD method)) The film can be formed by a known method such as When the plasma CVD method is used, the source gas is, for example, a mixed gas of SiH 4 , H 2, and B 2 H 6 in the p-type amorphous semiconductor thin film 13, and in the n-type amorphous semiconductor thin film 16, for example, A mixed gas of SiH 4 , H 2, and PH 3 can be used.
第１及び第２の透明導電膜１４、１７を積層する方法としては、例えばスパッタリング法、真空蒸着法、イオンプレーティング法（反応性プラズマ蒸着法）等を挙げることができるが、スパッタリング法によることが好ましい。スパッタリング法は、膜厚制御性等に優れ、また、イオンプレーティング法等に比べて低コストで行うことができる。 Examples of the method of laminating the first and second transparent conductive films 14 and 17 include a sputtering method, a vacuum deposition method, an ion plating method (reactive plasma deposition method), and the like. Is preferred. The sputtering method is excellent in film thickness controllability and the like, and can be performed at a lower cost than the ion plating method.
第１及び第２の透明導電膜１４、１７の形成に用いられるスパッタリングターゲットとしては、主成分が酸化インジウムであり、酸化タンタル及び好ましくは元素（ｘ）の酸化物を含むものが用いられる。スパッタリングターゲットにおける各成分の成分比は、所望する第１及び第２の透明導電膜１４、１７の成分比に応じて適宜調整することができる。また、スパッタリングターゲットには、さらに他の成分（例えば酸化錫等）が含まれていてもよい。なお、スパッタリング法により第１又は第２の透明導電膜１４、１７を形成した場合、各透明導電膜１４、１７における金属成分の含有量（含有比）は、用いたスパッタリングターゲットと実質的に同一であるとみなす。 As a sputtering target used for forming the first and second transparent conductive films 14 and 17, a sputtering target containing indium oxide as a main component and containing tantalum oxide and preferably an oxide of element (x) is used. The component ratio of each component in the sputtering target can be appropriately adjusted according to the desired component ratio of the first and second transparent conductive films 14 and 17. Further, the sputtering target may further contain other components (for example, tin oxide). In addition, when the 1st or 2nd transparent conductive films 14 and 17 are formed by sputtering method, content (content ratio) of the metal component in each transparent conductive films 14 and 17 is substantially the same as the used sputtering target. It is considered.
前記スパッタリングターゲットは、例えば、インジウム酸化物の前駆体と、タンタル酸化物の前駆体とを含む溶液を調製する工程（ａ）、前記溶液にアルカリ化合物を添加して、金属水酸化物の沈殿物を得る工程（ｂ）、得られた金属水酸化物の沈殿物を洗浄及び乾燥し、金属酸化物の粉末を得る工程（ｃ）、及び得られた金属酸化物の粉末を粉砕後焼結する工程（ｄ）を含む方法により得ることができる。前記インジウム酸化物の前駆体としては硝酸インジウム、塩化インジウム等を挙げることができ、前記タンタル酸化物の前駆体としては塩化タンタル等を挙げることができる。工程（ａ）で得られた溶液のｐＨとしては、１〜４が好ましい。また、この溶液には、他の成分（例えば、元素（ｘ）の酸化物又はその前駆体、ｐＨ調整剤等）を添加してもよい。工程（ｂ）においてアルカリ化合物を添加した後の溶液のｐＨとしては、７〜１０が好ましい。また、工程（ｄ）における焼結温度は１２５０〜１６００℃程度、焼結時間は１０〜２０時間程度とすることができる。 The sputtering target includes, for example, a step (a) of preparing a solution containing an indium oxide precursor and a tantalum oxide precursor, adding an alkali compound to the solution, and depositing a metal hydroxide Step (b) to obtain a metal hydroxide, washing and drying the obtained metal hydroxide precipitate (c) to obtain a metal oxide powder, and sintering the obtained metal oxide powder after pulverization It can be obtained by a method including step (d). Examples of the indium oxide precursor include indium nitrate and indium chloride, and examples of the tantalum oxide precursor include tantalum chloride. As pH of the solution obtained at the process (a), 1-4 are preferable. Moreover, you may add another component (For example, the oxide of an element (x) or its precursor, a pH adjuster etc.) to this solution. The pH of the solution after adding the alkali compound in the step (b) is preferably 7 to 10. Moreover, the sintering temperature in a process (d) can be about 1250-1600 degreeC, and sintering time can be about 10 to 20 hours.
スパッタリング法は、公知のスパッタリング装置を用いて行うことができる。スパッタリング装置のチャンバー内の初期真空度としては、１×１０−７〜１×１０−５Ｔｏｒｒ程度とすることができる。積層（蒸着）の際の基板温度としては、特に限定されないが、２００℃未満が好ましく、０℃以上８０℃以下がより好ましく、室温でよい。スパッタリングにより膜を積層後、必要に応じて、熱処理を行うことができる。この熱処理温度としては、５０℃以上２００℃未満が好ましく、１６０℃以下がより好ましい。ここで、透明導電膜１４、１７の形成においては、形成温度（スパッタリングの際の基板温度、及びその後必要に応じて行われる熱処理温度）２００℃未満（より好ましくは、１６０℃以下。下限としては、例えば２０℃）で行うことができ、透明導電膜１４、１７は前記組成からなるため、このような比較的低温での形成においても、結晶化が進行し、低抵抗の膜を得ることができる。また、形成温度が２００℃未満であるため、他の非晶質系半導体薄膜等に与える影響が抑えられ、高い発電効率を有するヘテロ接合型光発電素子を得ることができる。 The sputtering method can be performed using a known sputtering apparatus. The initial degree of vacuum in the chamber of the sputtering apparatus can be about 1 × 10 −7 to 1 × 10 −5 Torr. Although it does not specifically limit as board | substrate temperature in the case of lamination | stacking (vapor deposition), Less than 200 degreeC is preferable, 0 degreeC or more and 80 degrees C or less are more preferable, and room temperature may be sufficient. After the films are stacked by sputtering, heat treatment can be performed as necessary. The heat treatment temperature is preferably 50 ° C. or higher and lower than 200 ° C., more preferably 160 ° C. or lower. Here, in the formation of the transparent conductive films 14 and 17, the formation temperature (the substrate temperature during sputtering and the heat treatment temperature performed thereafter as necessary) is less than 200 ° C. (more preferably, 160 ° C. or less. Since the transparent conductive films 14 and 17 have the above-described composition, crystallization progresses even in the formation at such a relatively low temperature, and a low-resistance film can be obtained. it can. Moreover, since the formation temperature is less than 200 ° C., the influence on other amorphous semiconductor thin films and the like can be suppressed, and a heterojunction photovoltaic device having high power generation efficiency can be obtained.
集電極１８、１９の配設は公知の方法で行うことができる。集電極１８、１９の材料として導電性接着剤が用いられている場合、スクリーン印刷やグラビアオフセット印刷等の印刷法により形成することができる。また、集電極１８、１９に金属導線を用いる場合、導電性接着剤や低融点金属（半田等）によりの透明導電膜１４、１７上に固定することができる。 The collector electrodes 18 and 19 can be disposed by a known method. When a conductive adhesive is used as a material for the collector electrodes 18 and 19, it can be formed by a printing method such as screen printing or gravure offset printing. Moreover, when using a metal conducting wire for the collector electrodes 18 and 19, it can fix on the transparent conductive films 14 and 17 with a conductive adhesive or a low melting point metal (solder etc.).
本発明は前記した実施の形態に限定されるものではなく、本発明の要旨を変更しない範囲でその構成を変更することもできる。例えば、光発電素子１０が有する第１の真性非晶質系半導体薄膜１２及び第２の真性非晶質系半導体薄膜１５は必須の構成要件ではない。また、第１の透明導電膜１４又は第２の透明導電膜１７は、少なくともタンタルがドープされた酸化インジウム以外の透明導電材料からから形成されていてもよい。この透明導電材料としては、ＩＴＯ、タングステンドープインジウム酸化物（Ｉｎｄｉｕｍ Ｔｕｎｇｓｔｅｎ Ｏｘｉｄｅ：ＩＷＯ）等を挙げることができる。 The present invention is not limited to the above-described embodiment, and the configuration thereof can be changed without changing the gist of the present invention. For example, the first intrinsic amorphous semiconductor thin film 12 and the second intrinsic amorphous semiconductor thin film 15 included in the photovoltaic device 10 are not essential components. The first transparent conductive film 14 or the second transparent conductive film 17 may be formed of a transparent conductive material other than indium oxide doped with at least tantalum. Examples of the transparent conductive material include ITO and tungsten-doped indium oxide (IWO).
以下、実施例及び比較例を挙げて、本発明の内容をより具体的に説明する。なお、本発明は以下の実施例に限定されるものではない。 Hereinafter, the contents of the present invention will be described more specifically with reference to examples and comparative examples. In addition, this invention is not limited to a following example.
＜製造例１＞
硝酸インジウム（Ｉｎ（ＮＯ３）３）溶液に酸化タンタルの含有量が１質量％となる量の塩化タンタルを添加した。さらに、超純水を添加して５０℃で１２時間攪拌し、ｐＨ３のＩｎ／Ｔａ混合塩溶液を得た。次いで、前記混合塩溶液にＮＨ３ＯＨ水溶液を添加しｐＨ９とした後、４０℃で２０時間反応を進行させ、Ｉｎ／Ｔａ混合水酸化物の沈殿物を得た。前記沈殿物を分離し、超純水で三回洗浄し、１２０℃の熱風で乾燥させてインジウムタンタル酸化物（Ｉｎ−Ｔａ−Ｏ）粉末を得た。次いで、得られたＩｎ−Ｔａ−Ｏ粉末をポリビニルアルコール樹脂と共に湿式ボールミルで１２時間粉砕混合した。粉砕混合後の混合スラリーを乾燥し、モールドを用いて加圧成型し、得られた成型体を１６００℃、１２時間で焼結させ、焼結体（スパッタリングターゲット）を得た。
得られたスパッタリングターゲットをＤＣマグネトロンスパッタに装着させ、チャンバー内の初期真空度を１×１０−６Ｔｏｒｒ以下とし室温で１００ｎｍの厚みでガラス基板上にＩｎ−Ｔａ−Ｏ系薄膜を蒸着させた。その後、Ｉｎ−Ｔａ−Ｏ系薄膜を大気雰囲気下で１５０℃、２時間熱処理し、透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は４．０５×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、４．０％以内の抵抗変化であった。
<Production Example 1>
Tantalum chloride was added to an indium nitrate (In (NO 3 ) 3 ) solution so that the content of tantalum oxide was 1% by mass. Furthermore, ultrapure water was added and stirred at 50 ° C. for 12 hours to obtain a pH 3 In / Ta mixed salt solution. Next, an NH 3 OH aqueous solution was added to the mixed salt solution to adjust the pH to 9, and then the reaction was allowed to proceed at 40 ° C. for 20 hours to obtain an In / Ta mixed hydroxide precipitate. The precipitate was separated, washed three times with ultrapure water, and dried with hot air at 120 ° C. to obtain indium tantalum oxide (In—Ta—O) powder. Next, the obtained In-Ta-O powder was pulverized and mixed with a polyvinyl alcohol resin in a wet ball mill for 12 hours. The mixed slurry after pulverization and mixing was dried and pressure-molded using a mold, and the obtained molded body was sintered at 1600 ° C. for 12 hours to obtain a sintered body (sputtering target).
The obtained sputtering target was attached to DC magnetron sputtering, the initial vacuum degree in the chamber was set to 1 × 10 −6 Torr or less, and an In—Ta—O-based thin film was deposited on a glass substrate with a thickness of 100 nm at room temperature. Thereafter, the In—Ta—O-based thin film was heat-treated at 150 ° C. for 2 hours in an air atmosphere to obtain a transparent conductive film. The crystallinity of the surface of the obtained transparent conductive film could be confirmed by SEM observation, and the specific resistance was 4.05 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 4.0%.
＜製造例２＞
酸化タンタルの含有量が３質量％となる量の塩化タンタルを添加したこと以外は、製造例１と同様の方法によりスパッタリングターゲットを得た。得られたスパッタリングターゲットを用い、製造例１と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は５．２２×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、３．８％以内の抵抗変化であった。
<Production Example 2>
A sputtering target was obtained by the same method as in Production Example 1 except that tantalum chloride was added in an amount that would result in a tantalum oxide content of 3% by mass. A transparent conductive film was obtained by the same method as in Production Example 1 using the obtained sputtering target. The surface of the obtained transparent conductive film was confirmed to have crystallinity by SEM observation, and the specific resistance was 5.22 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 3.8%.
＜製造例３＞
酸化タンタルの含有量が５質量％となる量の塩化タンタルを添加したこと以外は、製造例１と同様の方法によりスパッタリングターゲットを得た。得られたスパッタリングターゲットを用い、製造例１と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は６．４３×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、３．５％以内の抵抗変化であった。
<Production Example 3>
A sputtering target was obtained by the same method as in Production Example 1 except that tantalum chloride was added in an amount that would result in a tantalum oxide content of 5% by mass. A transparent conductive film was obtained by the same method as in Production Example 1 using the obtained sputtering target. The crystallinity of the surface of the obtained transparent conductive film could be confirmed by SEM observation, and the specific resistance was 6.43 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 3.5%.
＜製造例４＞
酸化タンタルの含有量が１０質量％となる量の塩化タンタルを添加したこと以外は、製造例１と同様の方法によりスパッタリングターゲットを得た。得られたスパッタリングターゲットを用い、製造例１と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は７．０８×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、３．６％以内の抵抗変化であった。
<Production Example 4>
A sputtering target was obtained by the same method as in Production Example 1 except that tantalum chloride was added in an amount such that the tantalum oxide content was 10% by mass. A transparent conductive film was obtained by the same method as in Production Example 1 using the obtained sputtering target. The crystallinity of the surface of the obtained transparent conductive film could be confirmed by SEM observation, and the specific resistance was 7.08 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 3.6%.
＜製造例５＞
硝酸インジウム（Ｉｎ（ＮＯ３）３）溶液に酸化タンタルの含有量が０．５質量％となる量の塩化タンタル及び酸化チタンの含有量が０．５質量％となる量のオルトチタン酸テトライソプロピルを添加した。さらに、超純水を添加して５０℃で１２時間攪拌し、ｐＨ３．２のＩｎ／Ｔａ／Ｔｉ混合塩溶液を得た。次いで、前記混合塩溶液にＮＨ３ＯＨ水溶液を添加しｐＨ９とした後、４０℃で２０時間反応を進行させ、Ｉｎ／Ｔａ／Ｔｉ混合水酸化物の沈殿物を得た。前記沈殿物を分離し、超純水で三回洗浄し、１２０℃の熱風で乾燥させてインジウムタンタルチタン酸化物（Ｉｎ−Ｔａ−Ｔｉ−Ｏ）粉末を得た。次いで、得られたＩｎ−Ｔａ−Ｔｉ−Ｏ粉末をポリビニルアルコール樹脂と共に湿式ボールミルで１２時間粉砕混合した。粉砕混合後の混合スラリーを乾燥し、ＣＩＰを用いて加圧成型し、得られた成型体を１４５０℃、１２時間で焼結させ、焼結体（スパッタリングターゲット）を得た。
得られたスパッタリングターゲットをＤＣマグネトロンスパッタに装着させ、チャンバー内の初期真空度を１×１０−６Ｔｏｒｒ以下とし室温で１００ｎｍの厚みでガラス基板上にＩｎ−Ｔａ−Ｔｉ−Ｏ系薄膜を蒸着させた。その後、Ｉｎ−Ｔａ−Ｔｉ−Ｏ系薄膜を大気雰囲気下で１５０℃、２時間熱処理し、透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は３．７８×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、３．２％以内の抵抗変化であった。
<Production Example 5>
Tetraisopropyl orthotitanate in an amount of 0.5% by mass of tantalum chloride and titanium oxide in an amount of 0.5% by mass of tantalum oxide in an indium nitrate (In (NO 3 ) 3 ) solution Was added. Furthermore, ultrapure water was added and stirred at 50 ° C. for 12 hours to obtain an In / Ta / Ti mixed salt solution having a pH of 3.2. Next, an NH 3 OH aqueous solution was added to the mixed salt solution to adjust the pH to 9, and then the reaction was allowed to proceed at 40 ° C. for 20 hours to obtain an In / Ta / Ti mixed hydroxide precipitate. The precipitate was separated, washed three times with ultrapure water, and dried with hot air at 120 ° C. to obtain indium tantalum titanium oxide (In—Ta—Ti—O) powder. Next, the obtained In—Ta—Ti—O powder was pulverized and mixed with a polyvinyl alcohol resin in a wet ball mill for 12 hours. The mixed slurry after pulverization and mixing was dried and pressure-molded using CIP, and the obtained molded body was sintered at 1450 ° C. for 12 hours to obtain a sintered body (sputtering target).
The obtained sputtering target was attached to DC magnetron sputtering, the initial vacuum degree in the chamber was set to 1 × 10 −6 Torr or less, and an In—Ta—Ti—O-based thin film was deposited on a glass substrate with a thickness of 100 nm at room temperature. It was. Thereafter, the In—Ta—Ti—O-based thin film was heat-treated at 150 ° C. for 2 hours in an air atmosphere to obtain a transparent conductive film. The surface of the obtained transparent conductive film was confirmed to have crystallinity by SEM observation, and the specific resistance was 3.78 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 3.2%.
＜製造例６＞
酸化タンタルの含有量が１．５質量％となる量の塩化タンタル、及び酸化チタンの含有量が１．５質量％となる量のオルトチタン酸テトライソプロピルを添加したこと以外は、製造例５と同様の方法によりスパッタリングターゲットを得た。得られたスパッタリングターゲットを用い、製造例５と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は４．１２×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、２．８％以内の抵抗変化であった。
<Production Example 6>
Production Example 5 except that tantalum chloride with an amount of tantalum oxide of 1.5% by mass and tetraisopropyl orthotitanate with an amount of titanium oxide of 1.5% by mass were added. A sputtering target was obtained by the same method. Using the obtained sputtering target, a transparent conductive film was obtained in the same manner as in Production Example 5. Crystallinity of the surface of the obtained transparent conductive film could be confirmed by SEM observation, and the specific resistance was 4.12 × 10 −4 Ω · cm. Further, the resistance change after the obtained transparent conductive film was stored at 80 ° C. under a room temperature of 85% for 5 days was a resistance change within 2.8%.
＜製造例７＞
酸化インジウムの含有量が８９．１％、酸化錫の含有量が９．９％、酸化タンタルの含有量が１質量％となるように硝酸インジウム、塩化錫及び塩化タンタルを混合して溶液を得たこと以外は製造例５と同様の方法によりスパッタリングターゲットを得た。得られたスパッタリングターゲットを用い、製造例５と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認でき、比抵抗は４．２５×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、４．３％以内の抵抗変化であった。
<Production Example 7>
A solution is obtained by mixing indium nitrate, tin chloride and tantalum chloride so that the indium oxide content is 89.1%, the tin oxide content is 9.9%, and the tantalum oxide content is 1% by mass. A sputtering target was obtained by the same method as in Production Example 5 except that. Using the obtained sputtering target, a transparent conductive film was obtained in the same manner as in Production Example 5. Crystallinity of the surface of the obtained transparent conductive film could be confirmed by SEM observation, and the specific resistance was 4.25 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 4.3%.
＜比較製造例１＞
酸化インジウムの含有量が９０質量％、酸化錫の含有量が１０質量％のインジウム錫酸化物スパッタリングターゲットを用い、製造例５と同様の方法により透明導電膜を得た。得られた透明導電膜の表面はＳＥＭ観察により結晶性が確認できず、比抵抗は７．１９×１０−４Ω・ｃｍであった。また、得られた透明導電膜を８０℃、８５％の室度下で５日間保管した後の抵抗変化を測定した結果、１２．９％以内の抵抗変化であった。
<Comparative Production Example 1>
A transparent conductive film was obtained in the same manner as in Production Example 5 using an indium tin oxide sputtering target having an indium oxide content of 90% by mass and a tin oxide content of 10% by mass. As for the surface of the obtained transparent conductive film, crystallinity could not be confirmed by SEM observation, and the specific resistance was 7.19 × 10 −4 Ω · cm. Moreover, as a result of measuring the resistance change after storing the obtained transparent conductive film at 80 ° C. under a room temperature of 85% for 5 days, the resistance change was within 12.9%.
得られた各透明導電膜の評価結果を再度以下の表１に示す。 The evaluation results of the obtained transparent conductive films are again shown in Table 1 below.
比較製造例１の透明導電膜（Ｉｎ−Ｓｎ−Ｏ）の熱処理前後のＳＥＭ画像を図２に示す。また、製造例の透明導電膜（Ｉｎ−Ｔａ−Ｏ）及び透明導電膜（Ｉｎ−Ｔａ−Ｔｉ−Ｏ）の熱処理前後のＳＥＭ画像をそれぞれ図３、図４に示す。透明導電膜（Ｉｎ−Ｓｎ−Ｏ）は熱処理前は非晶質であり、１５０℃の熱処理を施しても結晶化が進行しないことがわかる。一方、透明導電膜（Ｉｎ−Ｔａ−Ｏ）及び透明導電膜（Ｉｎ−Ｔａ−Ｔｉ−Ｏ）においては、熱処理前の状態で既に結晶化されており、１５０℃の熱処理によりより結晶化が進むことがわかる。なお、図３、図４における熱処理後のＳＥＭ画像を元にした面内長軸平均結晶粒径は、共に約１００ｎｍであった。 FIG. 2 shows SEM images before and after the heat treatment of the transparent conductive film (In—Sn—O) of Comparative Production Example 1. 3 and 4 show SEM images before and after the heat treatment of the transparent conductive film (In-Ta-O) and the transparent conductive film (In-Ta-Ti-O) in the production example, respectively. It can be seen that the transparent conductive film (In—Sn—O) is amorphous before heat treatment, and crystallization does not proceed even when heat treatment at 150 ° C. is performed. On the other hand, the transparent conductive film (In—Ta—O) and the transparent conductive film (In—Ta—Ti—O) are already crystallized in the state before the heat treatment, and the crystallization proceeds further by the heat treatment at 150 ° C. I understand that. The in-plane long axis average crystal grain size based on the SEM images after heat treatment in FIGS. 3 and 4 was both about 100 nm.
＜比較例１〜２、実施例１＞
ｎ型単結晶シリコン基板の一側に、第１の真性非晶質系シリコン薄膜（膜厚６ｎｍ）、ｐ型非晶質系シリコン薄膜（膜厚４ｎｍ）及び第１の透明導電膜（膜厚６５ｎｍ）をこの順に積層した。なお、ｎ型単結晶シリコン基板は、両面に無数のピラミッド形状を有する微細な凹凸構造（テクスチャー構造）が形成されたものを用いた。この凹凸構造は、約３質量％の水酸化ナトリウムを含むエッチング液に基板材料を浸漬し、基板材料の（１００）面を異方性エッチングすることにより形成した。
ついで、ｎ型単結晶シリコン基板の他側に、第２の真性非晶質系シリコン薄膜（膜厚６ｎｍ）、ｎ型非晶質系シリコン薄膜（膜厚８ｎｍ）及び第２の透明導電膜（膜厚６５ｎｍ）をこの順に積層した。各シリコン薄膜は、プラズマＣＶＤ法により積層した。各実施例及び比較例における第１及び第２の透明導電膜は、以下の材料及び方法により積層した。
<Comparative Examples 1-2, Example 1>
A first intrinsic amorphous silicon thin film (film thickness 6 nm), a p-type amorphous silicon thin film (film thickness 4 nm), and a first transparent conductive film (film thickness) are formed on one side of an n-type single crystal silicon substrate. 65 nm) was laminated in this order. In addition, the n-type single crystal silicon substrate used what formed the fine uneven structure (texture structure) which has innumerable pyramid shape on both surfaces. This concavo-convex structure was formed by immersing the substrate material in an etching solution containing about 3% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
Then, on the other side of the n-type single crystal silicon substrate, a second intrinsic amorphous silicon thin film (film thickness 6 nm), an n-type amorphous silicon thin film (film thickness 8 nm), and a second transparent conductive film ( A film thickness of 65 nm) was laminated in this order. Each silicon thin film was laminated by a plasma CVD method. The first and second transparent conductive films in each example and comparative example were laminated by the following materials and methods.
比較例１：ＩＴＯ（Ｓｎ＝１０質量％）、スパッタリング法
比較例２：ＩＴＯ（Ｓｎ＝５質量％）、イオンプレーティング法
実施例１：Ｉｎ−Ｔａ−Ｔｉ−Ｏ材料（製造例５のスパッタリングターゲット）、スパッタリング法（製造例５の成膜条件）
Comparative Example 1: ITO (Sn = 10 mass%), sputtering method Comparative Example 2: ITO (Sn = 5 mass%), ion plating method Example 1: In-Ta-Ti-O material (Sputtering of Production Example 5) Target), sputtering method (film formation conditions of Production Example 5)
次いで、第１及び第２の透明導電膜の表面（外側の面）にそれぞれ、集電極として、平行な複数のバスバー電極と、このバスバー電極にそれぞれ直交する複数のフィンガー電極を形成した。この集電極は、銀ペーストを用いてスクリーン印刷により形成した。このようにして、比較例１〜２、及び実施例１の光発電素子を得た。 Next, a plurality of parallel bus bar electrodes and a plurality of finger electrodes respectively orthogonal to the bus bar electrodes were formed as collector electrodes on the surfaces (outer surfaces) of the first and second transparent conductive films. This collector electrode was formed by screen printing using a silver paste. Thus, the photovoltaic device of Comparative Examples 1-2 and Example 1 was obtained.
得られた各光発電素子の最大出力（Ｐｍａｘ）を測定した。測定結果として、比較例１を基準とした値を図５に示す。なお、一側を光入射面とした場合（ｐ層が光入射側に積層されているヘテロ接合構造、Ｆｒｏｎｔ ｅｍｉｔｔｅｒ）、及び他側を光入射面とした場合（ｐ層が光入射側とは反対側に積層されているヘテロ接合構造、Ｒｅａｒ ｅｍｉｔｔｅｒ）それぞれを測定した。 The maximum output (Pmax) of each obtained photovoltaic device was measured. As a measurement result, values based on Comparative Example 1 are shown in FIG. In addition, when one side is a light incident surface (a heterojunction structure in which a p layer is laminated on the light incident side, a front emitter), and when the other side is a light incident surface (the p layer is a light incident side) Each of the heterojunction structures (Rear emitters) stacked on the opposite side was measured.
図５に示されるように、実施例１の光発電素子は、ＩＴＯで透明導電膜を形成した比較例１、２と比べて高い最大出力を有する。また、スパッタリング法により高性能の透明導電膜を形成しているため低コストで効率的に生産することができる。 As shown in FIG. 5, the photovoltaic device of Example 1 has a higher maximum output than Comparative Examples 1 and 2 in which a transparent conductive film is formed of ITO. Moreover, since a high-performance transparent conductive film is formed by a sputtering method, it can be efficiently produced at low cost.
１０：光発電素子、１１：ｎ型結晶半導体基板、１２：第１の真性非晶質系半導体薄膜、１３：ｐ型非晶質系半導体薄膜、１４：第１の透明導電膜、１５：第２の真性非晶質系半導体薄膜、１６：ｎ型非晶質系半導体薄膜、１７：第２の透明導電膜、１８、１９：集電極 10: photovoltaic device, 11: n-type crystal semiconductor substrate, 12: first intrinsic amorphous semiconductor thin film, 13: p-type amorphous semiconductor thin film, 14: first transparent conductive film, 15: first 2 intrinsic amorphous semiconductor thin film, 16: n-type amorphous semiconductor thin film, 17: second transparent conductive film, 18, 19: collector electrode
Claims (8)
前記第１及び第２の透明導電膜のいずれかは、少なくともタンタルがドープされた酸化インジウムから形成されている透明導電膜（α）であることを特徴とする光発電素子。 an n-type crystal semiconductor substrate, a p-type amorphous semiconductor thin film and a first transparent conductive film stacked in this order on one side of the n-type crystal semiconductor substrate, and this on the other side of the n-type crystal semiconductor substrate In a photovoltaic device comprising an n-type amorphous semiconductor thin film and a second transparent conductive film, which are sequentially laminated,
Either of the first and second transparent conductive films is a transparent conductive film (α) formed of indium oxide doped with at least tantalum.
主成分が酸化インジウムであり、酸化タンタルを含むスパッタリングターゲットを用いたスパッタリング法により、前記第１及び第２の透明導電膜の少なくともいずれかを形成する工程を有し、
該工程における形成温度が２００℃未満であることを特徴とする光発電素子の製造方法。 an n-type crystal semiconductor substrate, a p-type amorphous semiconductor thin film and a first transparent conductive film stacked in this order on one side of the n-type crystal semiconductor substrate, and this on the other side of the n-type crystal semiconductor substrate In a method for manufacturing a photovoltaic device comprising an n-type amorphous semiconductor thin film and a second transparent conductive film, which are sequentially laminated,
A step of forming at least one of the first and second transparent conductive films by a sputtering method using a sputtering target containing indium oxide as a main component and containing tantalum oxide;
The formation temperature in this process is less than 200 degreeC, The manufacturing method of the photovoltaic device characterized by the above-mentioned.
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| WO2018179595A1 (en) * | 2017-03-31 | 2018-10-04 | Ｊｘ金属株式会社 | Sputtering target, sputtering target production method, amorphous film, amorphous film production method, crystalline film, and crystalline film production method |
| JP2021177511A (en) * | 2020-05-07 | 2021-11-11 | 株式会社カネカ | Solar cell, solar cell module, and solar cell manufacturing method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI579138B (en) * | 2015-07-09 | 2017-04-21 | 國立臺灣師範大學 | Strengthened hetero-connected structure and method of making the same |
| CN112110721B (en) * | 2020-09-21 | 2022-07-01 | 先导薄膜材料（广东）有限公司 | Preparation method of indium tin tantalum oxide target material |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02309511A (en) * | 1989-05-24 | 1990-12-25 | Showa Denko Kk | Transparent conductive film |
| JP3447163B2 (en) * | 1995-11-30 | 2003-09-16 | 出光興産株式会社 | Transparent conductive laminate |
| WO2006095733A1 (en) * | 2005-03-09 | 2006-09-14 | Idemitsu Kosan Co., Ltd. | Amorphous transparent conductive film, target and production method for amorphous conductive film |
| JP4568254B2 (en) * | 2006-07-20 | 2010-10-27 | 三洋電機株式会社 | Solar cell module |
| JP5279814B2 (en) * | 2008-03-19 | 2013-09-04 | 三洋電機株式会社 | Solar cell and manufacturing method thereof |
| JP5170009B2 (en) * | 2009-06-24 | 2013-03-27 | 住友金属鉱山株式会社 | Indium oxide sputtering target and method for producing the same |
| JP5502412B2 (en) * | 2009-09-30 | 2014-05-28 | 三洋電機株式会社 | Method for manufacturing photovoltaic device |
-
2013
- 2013-10-01 JP JP2013206484A patent/JP2015070255A/en active Pending
-
2014
- 2014-09-29 WO PCT/JP2014/076640 patent/WO2015050264A1/en active Application Filing
- 2014-09-30 TW TW103133977A patent/TW201521216A/en unknown
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018179595A1 (en) * | 2017-03-31 | 2018-10-04 | Ｊｘ金属株式会社 | Sputtering target, sputtering target production method, amorphous film, amorphous film production method, crystalline film, and crystalline film production method |
| KR20180121478A (en) * | 2017-03-31 | 2018-11-07 | 제이엑스금속주식회사 | Sputtering target, method of producing sputtering target, amorphous film, method of producing amorphous film, method of producing crystalline film and crystalline film |
| JP2018172733A (en) * | 2017-03-31 | 2018-11-08 | Ｊｘ金属株式会社 | Sputtering target, production method of sputtering target, amorphous film, production method of amorphous film, crystalline film and production method of crystalline film |
| KR102166104B1 (en) * | 2017-03-31 | 2020-10-15 | 제이엑스금속주식회사 | Sputtering target, method of producing sputtering target, method of producing amorphous film, method of producing amorphous film, method of producing crystalline film and crystalline film |
| JP2021177511A (en) * | 2020-05-07 | 2021-11-11 | 株式会社カネカ | Solar cell, solar cell module, and solar cell manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201521216A (en) | 2015-06-01 |
| WO2015050264A1 (en) | 2015-04-09 |
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