JP2015050202A - 光半導体装置およびその製造方法 - Google Patents
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Abstract
Description
Ion Etching)法を用いることができる。マスク40を除いたメサストライプ11の高さは、一例として2.0μmである。メサストライプ11の側面のn型InP基板10の主面に対する角度θ0は例えば94°である。メサストライプ11を形成した後、ドライエッチングによるダメージなどを除去するため、ウェットエッチングを行う。このウェットエッチングにより、角度θ0が大きくなる。
圧力:85.0Torr
ガス:水素雰囲気、および少量のホスフィン(PH3)
ホスフィン(PH3)の分圧:2.8Torr
温度:650℃〜670℃
時間:10分〜20分
以上の条件において熱処理を行うことで、メサストライプ11をテーパー形状にする。上記状態において、n型InP基板10の表面原子であるリン(P)が移動し、メサストライプ11の底部に成長することで、テーパー形状が形成される。これにより角度θ1およびθ2が形成される。
11 メサストライプ
12 n型クラッド層
14 InGaAsP層
16 活性層
18、26 p型クラッド層
20 p型半導体層
22 高抵抗半導体層
24 n型InPブロック層
28 コンタクト層
30 保護膜
32 p型電極
34 n型電極
40 マスク
100 半導体レーザ
Claims (7)
- 基板、前記基板の上に設けられたn型クラッド層、活性層およびp型クラッド層を含むメサ構造と、
前記メサ構造の側面から前記基板の前記メサ構造以外の平面部にかけて、前記平面部における厚さが5nm〜45nmのp型半導体層と、
前記p型半導体層上に設けられ、前記メサ構造を埋め込む高抵抗半導体層と、を具備し、
前記平面部において、前記p型半導体層の厚みと前記p型半導体層のp型ドーパントの濃度との積は、2.5×1019nm/cm3以下であり、
前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記基板の主面に対する角度は、前記活性層の側面の前記主面に対する角度より小さく、
前記メサ構造の前記主面に対する角度が変わる部分は、前記活性層の下端から0.1μm以上0.5μm以下離れていることを特徴とする光半導体装置。 - 前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記基板の主面に対する角度は38°以上78°以下であり、前記活性層の側面の前記主面に対する角度は80°以上115°以下であることを特徴とする請求項1記載の光半導体装置。
- 前記基板は、InPであり、
前記p型半導体層は、InP又はInPに格子整合したInGaAs、InGaAsP、InAlAs、InAlAsP、InAlGaAs、InAlGaAsPのいずれかであり、
前記p型半導体層のp型ドーパントはZn、MgまたはBeであることを特徴とする請求項1または2記載の光半導体装置。 - 前記基板の主面は、(100)面±1°であり、
前記メサ構造は、前記主面上に設けられることを特徴とする請求項1から3のいずれか一項記載の光半導体装置。 - 基板の上に順に形成されたn型クラッド層、活性層、およびp型クラッド層に対して選択的にエッチング処理を施すことによってメサ構造を形成する工程と、
前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記基板の主面に対する角度を、前記活性層の側面の前記主面に対する角度より小さくする工程と、
前記メサ構造の側面から前記基板の前記メサ構造以外の平面部にかけて、前記平面部における厚さが5nm〜45nmのp型半導体層を形成する工程と、
前記p型半導体層上に、前記メサ構造を埋め込む高抵抗半導体層を形成する工程と、を含み、
前記平面部において、前記p型半導体層の厚みと前記p型半導体層のp型ドーパントの濃度との積は、2.5×1019nm/cm3以下であり、
前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記主面に対する角度を小さくする工程は、前記メサ構造に熱処理を行う工程を含むことを特徴とする光半導体装置の製造方法。 - 基板の上に順に形成されたn型クラッド層、活性層、およびp型クラッド層に対して選択的にエッチング処理を施すことによってメサ構造を形成する工程と、
前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記基板の主面に対する角度を、前記活性層の側面の前記主面に対する角度より小さくする工程と、
前記メサ構造の側面から前記基板の前記メサ構造以外の平面部にかけて、前記平面部における厚さが5nm〜45nmのp型半導体層を形成する工程と、
前記p型半導体層上に、前記メサ構造を埋め込む高抵抗半導体層を形成する工程と、を含み、
前記平面部において、前記p型半導体層の厚みと前記p型半導体層のp型ドーパントの濃度との積は、2.5×1019nm/cm3以下であり、
前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記主面に対する角度を小さくする工程は、前記メサ構造を形成する工程に含まれ、
前記エッチング処理の条件を変えることにより、前記角度を小さくすることを特徴とする光半導体装置の製造方法。 - 前記メサ構造の前記活性層より下の部分における側面の少なくとも一部の前記主面に対する角度は38°以上78°以下であり、前記活性層の側面の前記主面に対する角度は80°以上115°以下であることを特徴とする請求5または6記載の光半導体装置の製造方法。
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JP2013084733A (ja) * | 2011-10-07 | 2013-05-09 | Sumitomo Electric Ind Ltd | 量子カスケード半導体レーザを作製する方法 |
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JP3225942B2 (ja) * | 1999-01-21 | 2001-11-05 | 日本電気株式会社 | 半導体光素子、その製造方法及び半導体光学装置 |
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JPH01146390A (ja) * | 1987-10-29 | 1989-06-08 | American Teleph & Telegr Co <Att> | 半導体デバイス |
JPH0758403A (ja) * | 1993-08-17 | 1995-03-03 | Nec Corp | 高抵抗埋め込み半導体レーザ |
JPH08264878A (ja) * | 1995-03-20 | 1996-10-11 | Fujitsu Ltd | 埋込型半導体レーザ装置及びその製造方法 |
JP2000012975A (ja) * | 1998-06-23 | 2000-01-14 | Matsushita Electric Ind Co Ltd | 半導体レーザ装置及びその製造方法 |
US20040121500A1 (en) * | 2002-12-10 | 2004-06-24 | Triquint Technology Holding Co. | Optical device and method of manufacture thereof |
JP2007013100A (ja) * | 2005-05-30 | 2007-01-18 | Mitsubishi Electric Corp | 半導体レーザ |
JP2010245502A (ja) * | 2009-03-18 | 2010-10-28 | Ricoh Co Ltd | 面発光レーザ、面発光レーザアレイ、光走査装置及び画像形成装置 |
JP2011249767A (ja) * | 2010-04-27 | 2011-12-08 | Sumitomo Electric Device Innovations Inc | 光半導体装置の製造方法 |
JP2013084733A (ja) * | 2011-10-07 | 2013-05-09 | Sumitomo Electric Ind Ltd | 量子カスケード半導体レーザを作製する方法 |
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