JP2015026341A - 論理演算装置 - Google Patents
論理演算装置 Download PDFInfo
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- JP2015026341A JP2015026341A JP2013157090A JP2013157090A JP2015026341A JP 2015026341 A JP2015026341 A JP 2015026341A JP 2013157090 A JP2013157090 A JP 2013157090A JP 2013157090 A JP2013157090 A JP 2013157090A JP 2015026341 A JP2015026341 A JP 2015026341A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
このように、本実施の形態のこの例では、出力ユニット40が、時分割的にNビットのビット列が出力されるタイミングにおいて、前回出力したビットを用いて、メモリデバイスにアクセスして取り出したビット間の論理演算結果と、その反転ビットとの一方を選択的に出力する手段として機能している。
Claims (4)
- N(Nは、N≧2の整数)ビット長のビット列の入力を受け入れて、前記入力されるビット列が表すアドレスに、当該入力されるビット列に含まれる各ビット間の論理演算結果を表すビットをその一部に含む多ビット長のデータを格納してなるルックアップテーブルを記憶するメモリデバイスと、
前記メモリデバイスにアクセスし、前記受け入れたビット列が表すアドレスに格納されたデータに含まれるビットを出力する出力手段と、
を含む論理演算装置。 - 請求項1記載の論理演算装置であって、
前記メモリデバイスに格納されたデータには、前記入力されるビット列に含まれる各ビット間の論理演算結果と、その反転ビットとが含まれ、
前記出力手段は、当該ビット間の論理演算結果と、その反転ビットとの一方を選択的に出力する論理演算装置。 - 請求項2記載の論理演算装置であって、
M(Mは、M>Nなる整数)ビット長のビット列の入力を受けて、当該ビット列からNビットのビット列を抽出して、当該抽出したNビットのビット列を時分割的に前記メモリデバイスに出力する分割手段をさらに含み、
時分割的に前記Nビットのビット列が出力されるタイミングにおいて、前記出力手段が、前回出力したビットを用いて、メモリデバイスにアクセスして取り出したビット間の論理演算結果と、その反転ビットとの一方を選択的に出力する論理演算装置。 - 請求項1から3のいずれか一項に記載の論理演算装置であって、
前記メモリデバイスに格納された論理演算結果は、入力ビット列に含まれる各ビット間の排他的論理和の演算結果である論理演算装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013157090A JP6219631B2 (ja) | 2013-07-29 | 2013-07-29 | 論理演算装置 |
TW103119252A TWI562059B (en) | 2013-07-29 | 2014-06-03 | Arithmetic logic unit |
EP14831256.4A EP3029839B1 (en) | 2013-07-29 | 2014-06-09 | Arithmetic logic device |
US14/908,339 US9866219B2 (en) | 2013-07-29 | 2014-06-09 | Device for logic operation |
CN201480042802.7A CN105432018B (zh) | 2013-07-29 | 2014-06-09 | 逻辑运算装置 |
PCT/JP2014/065245 WO2015015905A1 (ja) | 2013-07-29 | 2014-06-09 | 論理演算装置 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2013157090A JP6219631B2 (ja) | 2013-07-29 | 2013-07-29 | 論理演算装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2015026341A true JP2015026341A (ja) | 2015-02-05 |
JP2015026341A5 JP2015026341A5 (ja) | 2016-09-01 |
JP6219631B2 JP6219631B2 (ja) | 2017-10-25 |
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JP2013157090A Active JP6219631B2 (ja) | 2013-07-29 | 2013-07-29 | 論理演算装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9866219B2 (ja) |
EP (1) | EP3029839B1 (ja) |
JP (1) | JP6219631B2 (ja) |
CN (1) | CN105432018B (ja) |
TW (1) | TWI562059B (ja) |
WO (1) | WO2015015905A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10990389B2 (en) * | 2019-04-29 | 2021-04-27 | Micron Technology, Inc. | Bit string operations using a computing tile |
US10778245B1 (en) * | 2019-08-20 | 2020-09-15 | Micron Technology, Inc. | Bit string conversion |
US11227641B1 (en) * | 2020-07-21 | 2022-01-18 | Micron Technology, Inc. | Arithmetic operations in memory |
Citations (5)
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JPH02236637A (ja) * | 1988-08-19 | 1990-09-19 | Fuji Xerox Co Ltd | プログラマブル・ファジィ論理回路 |
JPH0457112A (ja) * | 1990-06-26 | 1992-02-24 | Mitsubishi Electric Corp | 演算装置 |
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JP2003281516A (ja) * | 2002-03-22 | 2003-10-03 | Canon Inc | 画像処理装置及びその方法 |
JP2008124843A (ja) * | 2006-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 無線受信装置 |
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US6049223A (en) * | 1995-03-22 | 2000-04-11 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US6487190B1 (en) * | 1996-06-27 | 2002-11-26 | Interdigital Technology Corporation | Efficient multichannel filtering for CDMA modems |
JP3533825B2 (ja) | 1996-04-26 | 2004-05-31 | 日本電信電話株式会社 | 論理演算ユニットおよび論理演算装置 |
US6555398B1 (en) * | 1999-10-22 | 2003-04-29 | Magic Corporation | Software programmable multiple function integrated circuit module |
US6463003B2 (en) * | 2000-06-07 | 2002-10-08 | Advanced Micro Devices, Inc. | Power saving scheme for burst mode implementation during reading of data from a memory device |
US7111224B1 (en) * | 2001-02-28 | 2006-09-19 | Xilinx, Inc. | FPGA configuration memory with built-in error correction mechanism |
US20030068038A1 (en) * | 2001-09-28 | 2003-04-10 | Bedros Hanounik | Method and apparatus for encrypting data |
US7157933B1 (en) * | 2004-02-14 | 2007-01-02 | Herman Schmit | Configurable circuits, IC's, and systems |
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US7129864B2 (en) * | 2004-12-31 | 2006-10-31 | Intel Corporation | Fast compact decoder for huffman codes |
JP2008527878A (ja) * | 2005-01-14 | 2008-07-24 | エヌエックスピー ビー ヴィ | チャネル符号化 |
US7768430B1 (en) * | 2008-05-20 | 2010-08-03 | Altera Corporation | Look-up table based memory |
US7663957B2 (en) * | 2008-05-27 | 2010-02-16 | Via Technologies, Inc. | Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor |
JP5261738B2 (ja) * | 2009-01-15 | 2013-08-14 | 国立大学法人広島大学 | 半導体装置 |
US9747105B2 (en) * | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
CN104012000B (zh) * | 2011-10-24 | 2017-03-08 | 天工方案公司 | 双模式功率放大器控制接口 |
-
2013
- 2013-07-29 JP JP2013157090A patent/JP6219631B2/ja active Active
-
2014
- 2014-06-03 TW TW103119252A patent/TWI562059B/zh active
- 2014-06-09 WO PCT/JP2014/065245 patent/WO2015015905A1/ja active Application Filing
- 2014-06-09 CN CN201480042802.7A patent/CN105432018B/zh active Active
- 2014-06-09 EP EP14831256.4A patent/EP3029839B1/en active Active
- 2014-06-09 US US14/908,339 patent/US9866219B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02236637A (ja) * | 1988-08-19 | 1990-09-19 | Fuji Xerox Co Ltd | プログラマブル・ファジィ論理回路 |
JPH0457112A (ja) * | 1990-06-26 | 1992-02-24 | Mitsubishi Electric Corp | 演算装置 |
US6181164B1 (en) * | 1999-01-08 | 2001-01-30 | Xilinx, Inc. | Linear feedback shift register in a programmable gate array |
JP2003281516A (ja) * | 2002-03-22 | 2003-10-03 | Canon Inc | 画像処理装置及びその方法 |
JP2008124843A (ja) * | 2006-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 無線受信装置 |
Also Published As
Publication number | Publication date |
---|---|
CN105432018A (zh) | 2016-03-23 |
JP6219631B2 (ja) | 2017-10-25 |
EP3029839B1 (en) | 2018-05-30 |
EP3029839A4 (en) | 2017-04-19 |
US9866219B2 (en) | 2018-01-09 |
CN105432018B (zh) | 2019-01-08 |
TWI562059B (en) | 2016-12-11 |
EP3029839A1 (en) | 2016-06-08 |
WO2015015905A1 (ja) | 2015-02-05 |
US20160211851A1 (en) | 2016-07-21 |
TW201506779A (zh) | 2015-02-16 |
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